Managing and controlling the use of hardware resources on integrated circuits

Abstract

Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information.

Description

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a flowchart of an exemplary RTL synthesis flow according to exemplary embodiments of the disclosed technology.

FIG. 2 is a schematic block diagram show an exemplary resource management framework that can be used to perform the implementer assignment process in FIG. 1.

FIG. 3 is a schematic block diagram of the components of the implementation suggestor component in the exemplary resource management framework of FIG. 2.

FIGS. 4A and 4C illustrate three different implementations as may be suggested by the implementation suggestor component of FIG. 3 for an exemplary multiplier circuit having inputs of varying bit size.

FIG. 5 is a first image of an exemplary graphical user interface as may be used in connection with the exemplary resource management framework of FIG. 2.

FIG. 6 is a second image of an exemplary graphical user interface as may be used in connection with the exemplary resource management framework of FIG. 2.

FIG. 7 is a third image of an exemplary graphical user interface as may be used in connection with the exemplary resource management framework of FIG. 2.

FIG. 8 is a fourth image of an exemplary graphical user interface as may be used in connection with the exemplary resource management framework of FIG. 2.

FIG. 9 is a fifth image of an exemplary graphical user interface as may be used in connection with the exemplary resource management framework of FIG. 2.

FIG. 10 is a schematic block diagram of a network as may be used to perform any of the disclosed methods.

FIG. 11 is a schematic block diagram of a distributed computing network as may be used to perform any of the disclosed methods.

FIG. 12 is a flowchart illustrating how RTL synthesis using any of the disclosed techniques can be performed in the network of FIG. 10 or FIG. 11.

Claims

1. A method for performing RTL synthesis in a computer-implemented synthesis tool, comprising: receiving a register-transfer-level (“RTL”) description of a circuit to be implemented in a target architecture, the target architecture having a limited number of hardware resources available in a class of hardware resources;determining assignment information indicative of how operator instances in the RTL description are to be implemented using the hardware resources in the class of hardware resources; anddisplaying to a user one or more of a total number of hardware resources in the class that have been assigned using a user-selected implementation constraint, a total number of hardware resources in the class that have been assigned without using a user-selected implementation constraint, or a total number of hardware resources in the class that are remaining after accounting for current assignments,wherein the displaying is performed prior to a gate-level netlist being generated according to the assignment information.

2. The method of claim 1, wherein the class of hardware resources is a first class of hardware resources, the method further comprising, modifying the assignment information such that at least one of the operator instances is to be implemented using hardware resources in a second class of hardware resources;calculating how many of the hardware resources in the first class of hardware resources have been assigned after the modification; anddisplaying an updated indication of the total number of hardware resources in the first class that are remaining after accounting for current assignments.

3. The method of claim 2, wherein the modifying is performed in accordance with an implementation constraint selected by the user.

4. The method of claim 1, further comprising displaying an indication that the hardware resources in the class of hardware resources have been overmapped.

5. The method of claim 1, wherein the target architecture is one or more field programmable gate arrays (“FPGAs”).

6. The method of claim 1, wherein the class of hardware resources is one of embedded memory blocks, embedded multiplier blocks, embedded DSP blocks, or logic fabric.

7. One or more computer-readable media comprising computer-executable instructions for causing a computer system to perform the method of claim 1.

8. One or more computer-readable media storing a gate-level netlist generated by the method of claim 1.

9. A method for performing RTL synthesis in a computer-implemented synthesis tool, comprising: receiving a register-transfer-level (“RTL”) description of a circuit to be implemented in a target architecture, wherein the target architecture comprises a fixed number of available hardware resources in a class of hardware resources;determining one or more operator instances from the RTL description received, at least some of the operator instances being implementable by the hardware resources in the class of hardware resources; anddisplaying to a user an indication of the operator instances implementable by the hardware resources in the class of hardware resources.

10. The method of claim 9, wherein the displaying is performed prior to initially synthesizing the RTL description into a gate-level netlist.

11. The method of claim 9, further comprising displaying an indication of the number of the hardware resources available in the class of hardware resources.

12. The method of claim 9, further comprising, assigning at least one of the operator instances to be implemented using at least one of the hardware resources in the class of hardware resources;calculating how many of the hardware resources have been assigned; anddisplaying an indication of the number of the hardware resources assigned.

13. The method of claim 12, wherein the assigning is performed in accordance with an implementation constraint selected by the user.

14. The method of claim 12, further comprising displaying an indication that the hardware resources have been overmapped if the number of the hardware resources assigned exceeds a number of the hardware resources available in the class of hardware resources.

15. The method of claim 9, further comprising displaying an indication of a number of the hardware resources in the class of hardware resources to which operator instances have not been assigned.

16. The method of claim 9, wherein the target architecture is one or more field programmable gate arrays (“FPGAs”).

17. One or more computer-readable media comprising computer-executable instructions for causing a computer system to perform the method of claim 9.

18. One or more computer-readable media storing a gate-level netlist generated by the method of claim 9.

19. A method for performing synthesis in an RTL synthesis tool, comprising: receiving a description of a circuit to be implemented in a target architecture;determining a plurality of operator instances from the description received, the plurality of operator instances being implementable by one or more hardware resources available in the target architecture; andproviding a graphical user interface that displays to a user one or more of the operator instances and allows the user to associate an implementation constraint with at least one of the operator instances, the implementation constraint being selectable from a list of one or more implementation constraints known to be usable for the at least one of the operator instances.

20. The method of claim 19, wherein the implementation constraint indicates that an associated operator instance is to be implemented in the target architecture using one of a set of one or more implementation methods, the set of one or more implementation methods consisting of a subset of all implementation methods available for implementing the associated operator instance in the target architecture.

21. The method of claim 19, further comprising producing a gate-level netlist implementing operator instances in accordance with one or more associated implementation constraints.

22. The method of claim 19, wherein the graphical user interface displays an associated timing delay or resource usage cost for the implementation constraint.

23. The method of claim 19, -further comprising: assigning the operator instances to respective hardware resources available in the target architecture; anddisplaying in the graphical user interface information about resource usage in the target architecture resulting from the assignment, wherein the displaying is performed before a gate-level netlist is generated from the assignment.

24. The method of claim 23, wherein the information about resource usage includes one or more of a total number of hardware resources available in the target architecture in a class of hardware resources, a total number of hardware resources in the class that have been assigned using a user-selected implementation constraint, a total number of hardware resources in the class that have been assigned without using a user-selected implementation constraint, or a total number resources in the class that are remaining after accounting for the assignment.

25. The method of claim 23, wherein the information about resource usage includes a total number of hardware resources in a class of hardware resources made unavailable for assignment.

26. The method of claim 19, wherein the description is a register-transfer-level (“RTL”) description.

27. The method of claim 19, wherein the description is a gate-level netlist that includes one or more preserved operators.

28. The method of claim 19, wherein the target architecture is one or more field programmable gate arrays (“FPGAs”).

29. One or more computer-readable media comprising computer-executable instructions for causing a computer system to perform the method of claim 19.

30. One or more computer-readable media storing a gate-level netlist generated by the method of claim 19.

31. A method for performing RTL synthesis in a computer-implemented synthesis tool, comprising: receiving a register-transfer-level (“RTL”) description of a circuit to be implemented in a target architecture, wherein the target architecture comprises a fixed number of hardware resources in a class of hardware resources;determining one or more operator instances from the RTL description received, at least some of the operator instances being implementable by the hardware resources in the class of hardware resources; andprior to initially synthesizing the RTL description into a gate-level netlist, automatically determining assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources and providing a graphical user interface that allows a user to view and modify the assignment information.

32. The method of claim 31, further comprising displaying in the graphical user interface one or more of a total number of hardware resources available in the target architecture in the class of hardware resources, a total number of hardware resources in the class that have been assigned using a user-selected implementation constraint, a total number of hardware resources in the class that have been automatically assigned without using a user-selected implementation constraint, or a total number resources in the class that are remaining after accounting for the assignment information.

33. One or more computer-readable media comprising computer-executable instructions for causing a computer system to perform the method of claim 31.

34. One or more computer-readable media storing a gate-level netlist generated by the method of claim 31.

35. An RTL synthesis system, comprising: a database comprising data indicative of available hardware resources in one or more types of field programmable gate arrays (“FPGAs”);memory storing a register-transfer-level (“RTL”) description of a circuit to be implemented in a selected one of the FPGAs; anda graphical user interface that allows a user to view how one or more operator instances defined by the RTL description are assigned to be implemented by the available hardware resources of the selected one of the FPGAs and displays to the user how many of the available hardware resources in the selected one of the FPGAs remain available after accounting for the assignments.

36. The RTL synthesis system of claim 35, wherein the graphical user interface allows the user to view how the one or more operator instances defined by the RTL description are assigned to be implemented by the available hardware resources of the selected one of the FPGAs and displays to the user how many of the available hardware resources in the selected one of the FPGAs remain available after accounting for the assignments prior to synthesis of the RTL description into a gate-level netlist.

37. The RTL synthesis system of claim 35, further comprising an implementation suggestor component that automatically assigns operator instances to the available hardware resources.

38. The RTL synthesis system of claim 37, wherein the assignments made by the implementation suggestor component are based at least in part on heuristics developed from benchmarking experiments with the selected one of the FPGAs.

39. The RTL synthesis system of claim 37, wherein the graphical user interface allows a user to associate an implementation constraint with one or more respective operator instances defined by the RTL description, and wherein the implementation suggestor component assigns one or more operator instances to corresponding hardware resources in accordance with the respective implementation constraints.

40. The RTL synthesis system of claim 35, wherein, prior to synthesis of the RTL description into the gate-level netlist, the graphical user interface allows the user to modify how at least some of the operators are allocated to the available hardware resources and updates the display of how many of the available hardware resources remain available to account for the modification.

41. The RTL synthesis system of claim 35, wherein the graphical user interface allows the user to set a budget for a class of hardware resources that limits how many hardware resources in the class of hardware resources can be assigned to implement the one or more operator instances defined by the RTL description.