Patent Application
20250113570
A manufacturing method for a power semiconductor device is provided. Further, a power semiconductor device is also provided.
Documents US 2019/0296146 A1 and US 2002/0034852 A1 refer to semiconductor devices with differently doped regions.
A problem to be solved is to provide a power semiconductor device having improved electric behaviour.
This object is achieved, inter alia, by a manufacturing method any by a power semiconductor device as specified in the independent patent claims. Further exemplary embodiments are specified in the dependent patent claims.
For example, in the method described herein low-energy electron radiation is used in order to improve flat band voltage, VFB, and reduce carbon, C, defects at an oxide-SiC interface, for example, at a SiO2/SiC interface.
In at least one embodiment, the method is for producing a power semiconductor device and comprises the following steps, for example, in the stated sequence:
Despite the high bulk mobility of SiC, low inversion-channel mobilities u have been reported in SiC metal-oxide-semiconductor field-effect transistors, MOSFETs, leading to a much higher on-state resistance than what is expected from bulk SiC properties. This discrepancy has been attributed to the large density of interface states, Dit, at an SiO2/SiC interface, which is one to three orders of magnitude higher than in the case of an SiO2/Si interface. The nature of Dit close to the edge of the conduction band is generally attributed to the presence of C-related defects and intrinsic oxide acceptor defects. The presence of carbon in the SiC epilayer is due to injection during oxidation. The injected C atoms form clusters that give rise to acceptor levels close to the conduction band. These levels shorten charge carriers' lifetime and act as scattering centers, thus reducing μ.
In order to improve the electronic properties of a SiC MOSFET, the concentration of C defects, Dit, at the SiO2/n-type 4H—SiC interface should be reduced.
In the method described herein, pre-oxidation low-energy electron irradiation for defect reduction at the SiO2/n-type 4H—SiC interface is used.
For n-type channel MOSFETs, different ways of reducing Dit are possible, such as the post-oxidation annealing, POA, and pre-oxidation implantation, POI. POA in either N2O or POCl3 ambient, or POI, by either N, P or Sb donor impurities, results in a decrease of Dit in the upper part of SiC band gap (1011 cm−2 eV−1 for POA, low 1012 cm−2 eV−1 for POI) and increase of μ (90 cm2 V−1 s−1 for POA, 20 cm2 V−1 s−1 to 100 cm2 V−1 s−1 for POI). The reason for the reduction of Dit, and subsequent μ increase, has been explained in terms of N or P atoms passivating the C-clusters or in terms of counter-doping. Nevertheless, both POA and POI have some drawbacks: the concentration of incorporated N or P is difficult to control by POA and flat-band voltage, VFB, shift, due to the introduction of N or P or Sb in SiO2, can occur. In addition, since P is more easily incorporated into SiC than N, normally-on devices can be obtained.
One idea of the present method is, inter alia, to employ low energy electron irradiation in order to create a C-poor, that is, a layer rich of voids of C, also referred to as a VC-rich layer. This will act as a sink for C, leading to an improved VFB and the reduction of Dit at the SiO2/4H—SiC interface.
In order to produce VC, low energy electron irradiation is employed, for example, with an energy between 116 keV and 210 keV. This is the minimum energy required in order to produce the displacement of C atoms, that is, VC. In this way, virtually no other defects will be formed, either complex or Si-related, as occur after impurity implantation or higher energy electron irradiation.
Following irradiation, [VC] increases and the displaced carbon interstitial (CI) atoms will be in-diffused deep in the bulk by thermal annealing treatment at, for example, at most 500° C. Although CI is mobile even at room temperature, a thermal treatment can prevent C atoms displaced by irradiation from clustering during oxidation.
For an Al implanted n-type 4H—SiC epilayer, [VC] is 6×1015 cm−3. After dry oxidation at 1150° C. for 2 h, [VC] becomes 3×1015 cm−3, meaning that about 3×1015 cm−3 [CI] have been injected during oxidation. This means that prior to the formation of, for example, a 65 nm thick SiO2, the as-grown n-type epilayer should be irradiated with an electron dose such that [VC] is at least 3×1015 cm−3, for example. In this way, a C-poor layer is formed and during oxidation, little CI will cluster to form Dit.
With the method described herein, for example, the following benefits could be achieved:
According to at least one embodiment, a kinetic energy of electrons of the low-energy electron radiation is at least 116 keV. Alternatively or additionally, this energy is at most 210 keV. This means, for example, that at least 90% or at least 99% or at least 99.9% of the electrons of the low-energy electron radiation have said kinetic energy. By having such an energy, C atoms of the SiC lattice can specifically be addressed by the radiation to be moved away from the top side.
According to at least one embodiment, a dose of the low-energy electron radiation in the first portion is at least 1010 cm−2 or is at least 1012 cm−2 or is at least 1014 cm−2. Alternatively or additionally, it is possible that said dose is at most 1017 cm−2 or is at most 1016 cm−2 or at most 1015 cm−2.
According to at least one embodiment, the electrical insulation layer contains oxygen. For example, the electrical insulation layer is an oxide layer, in particular a layer of a metal oxide or of a semiconductor oxide. The electrical insulation layer may be of a stoichiometric oxide.
According to at least one embodiment, the electrical insulation layer is of SiO2. Otherwise, the electrical insulation layer can be of Al2O3, NOx, Y2O3, ZrO2, HfO2, La2O3, Ta2O5 or TiO2.
According to at least one embodiment, the electrical insulation layer is produced by thermal growth. For example, in gas phase the constituents of the electrical insulation layer are provided, which are, for example, Si and O in the case of SiO2. For example, a temperature during producing the electrical insulation layer is at least 600° C. or at least 800° C. or at least 1000° C. Alternatively or additionally, this temperature is at most 1500° C. or at most 1300° C. or at most 1150° C.
According to at least one embodiment, the producing the electrical insulation layer includes annealing a previously applied material of the electrical insulation layer. It is possible that all or most of the material of the electrical insulation layer has been applied on the top side of the semiconductor body prior to the annealing.
For example, a temperature during annealing the electrical insulation layer is at least 200° C. or at least 300° C. or at least 400° C. Alternatively or additionally, this temperature is at most 1000° C. or at most 800° C. or at most 600° C. For example, the annealing takes at least 0.5 h or at least 1 h and/or the annealing takes at most 12 h or at most 4 h. It is possible that a temperature during the annealing is lower than during application of the material of the electrical insulation layer.
Optionally, during annealing and/or during thermal growth at least one temperature ramp may be applied.
According to at least one embodiment, the annealing is done in a nitrogen-containing atmosphere. For example, the annealing is done in an N2 atmosphere, which may be free or virtually free of oxygen, or even in air or in one of N2O, NO, O2 or O3. The same may apply for the thermal growth of the electrical insulation layer.
According to at least one embodiment, the irradiating the at least one first portion is done in a nitrogen-containing atmosphere, which may be free or virtually free of oxygen, or which may be air or also in one of N2O, NO, O2 or O3.
According to at least one embodiment, the top side of the semiconductor body is a planar surface of the semiconductor body. Hence, the power semiconductor device may be of planar design.
According to at least one embodiment, the method further includes the step of forming one or more trenches into the semiconductor body. For example, the at least one trench is formed into the semiconductor body prior to irradiating the at least one first portion. The at least one trench may be produced by etching. Thus, the resulting power semiconductor device could be of a trench design.
According to at least one embodiment, the at least one first portion includes side walls and a bottom face of the at least one trench. It is possible that the at least one first region is limited to the side walls and/or to the bottom face of the at least one trench.
According to at least one embodiment, the method includes that prior to irradiating the at least one first portion, a mask material is applied on the top side. By means of the mask material, regions of the top side to be irradiated can be defined, or a penetration depth of the low-energy electron radiation into the semiconductor body may be adjusted by means of the mask material or by means of a thickness of the mask material, for a specified material.
According to at least one embodiment, during irradiating the at least one first portion the at least one first portion is free of the mask material while remaining portions of the top side are partially or completely covered by the mask material. If the penetration depth of the low-energy electron radiation into the semiconductor body is to be adjusted by means of the mask material in the first portion, too, it is possible that the at least one first portion is partially provided with the mask material, possible with a reduced thickness compared with the other regions of the top side. Even the whole at least one first portion may be covered with a thin layer of the mask material.
Using not only one, but a plurality of different mask materials is also possible.
According to at least one embodiment, by means of the low-energy electron radiation in the at least one first portion carbon atoms are moved from the top side into the semiconductor body. That is, after irradiating the at least one first portion, the semiconductor body may be of non-stoichiometric SiC. That is, in this area the semiconductor body may have a thin layer of Si0.5+xC0.5−x, wherein x may be at least 0.001 or at least 0.01 and/or x is at most 0.1 or at most 0.02. Said layer may have a thickness of at least 10 nm or of at least 100 nm. Alternatively or additionally, said thickness is at most 1 μm or at most 0.2 μm.
A power semiconductor device is additionally provided. The power semiconductor device is produced, for example, by means of the method as indicated in connection with at least one of the above-stated embodiments. Features of the power semiconductor device are therefore also disclosed for the method and vice versa.
In at least one embodiment, the power semiconductor device comprises a semiconductor body based on SiC and an electrical insulation layer applied in at least one first portion of a top side of the semiconductor body, wherein next to the electrical insulation layer the semiconductor body is silicon-enriched and, thus, poor of carbon, for example, compared with stoichiometric SiC.
According to at least one embodiment, the power semiconductor device is a metal-insulator-semiconductor field-effect transistor, MISFET, or an insulated gate-bipolar transistor, IGBT.
According to at least one embodiment, the power semiconductor device is configured for an operating voltage of at least 0.6 kV or of at least 1.2 kV. Alternatively or additionally, the power semiconductor device is configured for an operating voltage of at most 10 kV or of at most 6 kV.
According to at least one embodiment, the power semiconductor device is configured for an operating current of at least 10 A or of at least 0.1 kA or of at least 1 kA. Alternatively or additionally, the power semiconductor device is configured for an operating current of at most 20 kA or of at most 5 kA.
According to at least one embodiment, the power semiconductor device is a device selected from the following group: a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a gate turn-off thyristor (GTO), a gate commutated thyristor (GCT), a junction gate field-effect transistor (JFET).
The power semiconductor device is, for example, configured to be used to convert direct current, for example, from a battery to alternating current, for example, for an electric motor. The power semiconductor device may be used, for example, in vehicles like hybrid vehicles or plug-in electric vehicles or also in railways, like commuter trains.
A method described herein and a power semiconductor device described herein are explained in greater detail below by way of exemplary embodiments with reference to the drawings. Elements which are the same in the individual figures are indicated with the same reference numerals. The relationships between the elements are not shown to scale, however, but rather individual elements may be shown exaggeratedly large to assist in understanding.
In
According to
For example, the semiconductor body 2 includes a well region 24 which may be of n-type 4H—SiC. Further there can be two p-type regions in the semiconductor body 2. These regions may be a source region 23 and a drain region 5, if the semiconductor body 2 is to be configured as a MOSFET.
According to
Although only one first portion 21 is illustrated in context of
For example, a kinetic energy of electrons of the low-energy electron radiation E is at least 116 keV and at most 210 keV. As an option, a dose of the low-energy electron radiation E in the first portion 21 is at least 1012 cm−2 and at most 1017 cm−2.
For example, the irradiating with the radiation E is done in air or a nitrogen atmosphere. Thus, no vacuum may be required in the step of
In the method step of
For example, the electrical insulation layer 3 is of SiO2.
By means of the low-energy electron radiation E, carbon atoms are removed from a region next to the top side 20 in the first portion 21 so that in the first portion Si-rich SiC is present. Thus, electrical behavior can be improved as hampering the properly forming the oxide layer of the electrical insulation layer 3 by C clusters is suppressed.
Further, in
The finished power semiconductor device 1 is, for example, a power MOSFET or also an IGBT. In case of an IGBT, of course, there is no drain region but there may be a collector region as well as a drift region. Further electrodes beside the gate electrode 4, like a source electrode, a drain electrode or a collector electrode, are not illustrated in the figures.
For example, the finished power semiconductor device 1 is configured for currents of at least 10 A and/or of at most 10 kA. Alternatively or additionally, the power semiconductor device 1 is configured for a voltage of at least 0.6 kV and/or of at most 6 kV.
In
In this case, the finished power semiconductor device 1 will be configured as an IGBT. Thus, the semiconductor body 5 includes a source region 23 at the top side 20. As an option, the source region 23 is divided by the trench 5 in two sub-regions. The source region 23 is embedded in the well region 24. On a side of the well region 24 remote from the top side 20, there is a drift region 26. On a side of the drift region 26 remote from the drift region 26, there is a collector region 25. Again, electrodes for the various semiconductor regions 23, 24, 25 are not illustrate for simplifying the drawing.
For example, the trench 5 extends from the top side 20 into the drift region 26 and terminates within the drift region 26. Other than shown, the trench 5 does not need to have a planar bottom face but could have a rounded bottom face or even a V-shaped bottom region, seen in cross-section perpendicular with the top side 20.
Moreover, according to
Contrary to what is shown in
According to
Then, the remaining portion of the trench 5 is filled with the gate electrode 4.
Otherwise, the same as to
In
Otherwise, the same as to
The theoretical flat band voltage, VFB, is obtained by the difference between the gate metal work function and the semiconductor work function: VFB=□M−□S. This results in a value for VFB of 0.14 eV. From the measured U-C characteristic, a VFB of 0.38 eV for the pre-irradiated MOS device 1 and 1.80 eV for the reference device 9 can be extracted.
To prove the effects of electron irradiation, prior to oxidation, TCAD simulations were carried out on SiC MOSFETS. First, a SiC MOSFET with a typical concentration of interface traps of about 1012 eV−1 cm−2 was simulated. After that, a SiC MOSFET with the presence of traps that are present after oxidation have been considered, resulting in a Dit one order of magnitude lower:
EC − 0.19
ON1, ON2, OF1, OF2 may be regarded as labels only. Each electrically active level is located in the bandgap. For instance, OF1 is to be found at 0.19 eV below the conduction band edge. Electrically active levels give rise to a potential well, in which electrons fall. This well has a cross section. The larger, the easier to capture electrons. Also, each electrically active level is linked to a defect which, in turn, has a specified concentration.
The components shown in the figures follow, unless indicated otherwise, exemplarily in the specified sequence directly one on top of the other. Components which are not in contact in the figures are exemplarily spaced apart from one another. If lines are drawn parallel to one another, the corresponding surfaces may be oriented in parallel with one another. Likewise, unless indicated otherwise, the positions of the drawn components relative to one another are correctly reproduced in the figures.
The power semiconductor device and the method described herein is not restricted by the description on the basis of the exemplary embodiments. Rather, the power semiconductor device and the method encompass any new feature and also any combination of features, which includes in particular any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.
This patent application claims the priority of European patent application 22 162 144.4, the disclosure content of which is hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 22162144.4 | Mar 2022 | EP | regional |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2023/052132 | 1/30/2023 | WO |
