Manufacturing method of semiconductor device

Abstract

A gate electrode is formed on a first conductivity type substrate. A second conductivity type implantation region is formed in the first conductivity type substrate. A first conductivity type implantation region is formed by implanting the first conductivity type impurities into the first conductivity type substrate to a depth deeper than the second conductivity type implantation region. An ISSG oxide film whose thickness ranges from 60 nm to 100 nm is formed to cover the first conductivity type substrate and the gate electrode. A silicone nitride film is formed on the ISSG oxide film. A second silicone oxide film is formed on the silicon nitride film. A sidewall is formed to cover the gate electrode and the first conductivity type substrate. A source/drain diffusion layer is formed by implanting second conductivity type impurities into the first conductivity type substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

In the attached drawings:

FIG. 1 is a cross-sectional view schematically showing a semiconductor element according to the first embodiment of the present invention;

FIGS. 2A, 2B and 2C are cross-sectional views of the semiconductor element cut along a lengthwise direction of a gate, schematically showing a manufacturing process of the semiconductor element according to the first embodiment of the present invention;

FIGS. 3A, 3B and 3C are cross-sectional views schematically showing a manufacturing process following the manufacturing process shown in FIGS. 2A, 2B and 2C, and

FIG. 4 is a cross-sectional view schematically showing a semiconductor element according to the modification of the first embodiment of the present invention.

Claims

1. A manufacturing method of a semiconductor device, said manufacturing method comprising: forming a gate oxide film on a first conductivity type substrate;forming a polysilicon film on said gate oxide film;forming a tungsten silicide film on said polysilicon film;forming a first silicon oxide film on said tungsten silicide film;forming a resist mask having a pattern for forming a gate electrode on said first silicon oxide film;forming a gate electrode including a gate oxide layer, a polysilicon layer, tungsten silicide layer and a first silicon oxide layer layered on said first conductivity type substrate by patterning said gate oxide film, said polysilicon film, said tungsten silicide film and said first silicon oxide film using said resist mask as a mask;forming a second conductivity type implantation region by implanting second conductivity type impurities into said first conductivity type substrate exposed via said gate electrode using said gate electrode as a mask;forming a first conductivity type implantation region by implanting first conductivity type impurities into a region including an overlapping region overlapping with said second conductivity type implantation region in plane in such a manner that said first conductivity type impurities are implanted in the thickness direction of said first conductivity type substrate to a depth deeper than said second conductivity type implantation region;forming an ISSG oxide film having a thickness from 60 nm to 100 nm on an entire exposed surfaces including a surface of said first conductivity type substrate, a side surface and a top surface of said gate electrode;forming a silicone nitride film on said ISSG oxide film;forming a second silicone oxide film on said silicon nitride film;forming a sidewall including a layered body of an ISSG oxide layer, a silicon nitride layer and a second silicon oxide layer, by removing respective parts of said ISSG oxide film, said silicon nitride film and said second silicone oxide film, said sidewall covering said tungsten silicide layer, said polysilicon layer, said gate oxide layer and said first conductivity type substrate in such a manner that a top surface and a part of a side surface of said gate electrode are exposed, andforming a source/drain diffusion layer by implanting second conductivity type impurities into said first conductivity type substrate exposed via said gate electrode and said sidewall.

2. The manufacturing method according to claim 1, wherein said forming method of said ISSG film includes a heat treatment under the atmosphere of oxygen with the partial pressure ranging from 1066 Pa nm to 1200 Pa, at the temperature ranging from 900° C. to 1200° C., and the heating time ranging from 30 seconds to 60 seconds.

3. The manufacturing method according to claim 1, wherein said forming process of a second conductivity type implantation region is performed under the condition that the dose amount of said second conductivity type impurities ranges from 5×1012 ions/cm2 to 1.5×1013 ions/cm2, and the implantation energy ranges from 20 KeV to 40 KeV, and wherein said forming process of a first conductivity type implantation region is performed under the condition that the dose amount of said first conductivity type impurities ranges from 5×1012 ions/cm2 to 1.5×1013 ions/cm2, and the implantation energy ranges from 10 KeV to 30 KeV.

4. The manufacturing method according to claim 1, wherein said first conductivity type substrate is a P-type substrate, said second conductivity type impurities are N-type impurities, and said first conductivity type impurities are P-type impurities.

5. A manufacturing method of a semiconductor device, said manufacturing method comprising: forming a gate oxide film on a first conductivity type substrate;forming a polysilicon film on said gate oxide film;forming a tungsten silicide film on said polysilicon film;forming a first silicon oxide film on said tungsten silicide film;forming a resist mask having a pattern for forming a gate electrode on said first silicon oxide film;forming a gate electrode including a gate oxide layer, a polysilicon layer, tungsten silicide layer and a first silicon oxide layer layered on said first conductivity type substrate by patterning said gate oxide film, said polysilicon film, said tungsten silicide film and said first silicon oxide film using said resist mask as a mask;forming a first conductivity type implantation region by implanting first conductivity type impurities into said first conductivity type substrate exposed via said gate electrode using said gate electrode as a mask, under the condition that the dose amount of said first conductivity type impurities ranges from 5×1012 ions/cm2 to 1.0×1013 ions/cm2, and the implantation energy ranges from 10 KeV to 30 KeV.forming an ISSG oxide film on entire exposed surfaces of said first conductivity type substrate and said gate electrode;forming a silicone nitride film on said ISSG oxide film;forming a second silicone oxide film on said silicon nitride film;forming a sidewall including a layered body of an ISSG oxide layer, a silicon nitride layer and a second silicon oxide layer, by removing respective parts of said ISSG oxide film, said silicon nitride film and said second silicone oxide film, said sidewall covering said tungsten silicide layer, said polysilicon layer, said gate oxide layer and a part of said first conductivity type substrate in such a manner that a top surface and a part of a side surface of said gate electrode are exposed, andforming a source/drain diffusion layer by implanting second conductivity type impurities into said first conductivity type substrate exposed via said gate electrode and said sidewall.

6. The manufacturing method according to claim 5, wherein said first conductivity type substrate is a P-type substrate, said second conductivity type impurities are N-type impurities, and said first conductivity type impurities are P-type impurities.