Patent Grant
9866240
The disclosure relates to the technical field of communications, and in particular to a Maximum A Posteriori (MAP) algorithm-based Turbo decoding method and apparatus, and a computer storage medium.
In the international communication conference held at Geneva, Switzerland in 1993, C. Berrou, A. Glavieux and P. Thitimajshiwa from the British Communications University of France firstly proposed an encoding/decoding scheme referred to as a Turbo code. It is realized by combining two Recursive Systematic Convolutional (RSC) codes in a parallel cascading manner via an interleaver. This scheme adopts an iterative feedback decoding mode, truly explores a potential of cascaded codes, and breaks through a minimum distance short-code design idea in a random-like coding/decoding scheme, thereby making it more approach an ideal random code performance. Some existing communication systems such as a 3GPP LTE/LTE-A system, a WCDMA system and a TD-SCDMA system use Turbo codes for channel encoding.
The Turbo code has the characteristics of random-like codes, and also has sufficient structural information, which makes it possible to be decoded by using an efficient iterative decoding method. Due to these characteristics, the Turbo code has extremely beneficial performances under the conditions of a moderate bit error rate and a long packet length particularly. Actually, when any code rate and information packet length are greater than 104 bits, if a signal-to-noise ratio is within a Shannon limit 1 dB, the Turbo code using an iterative decoding algorithm can reach a bit error rate of 10-5, that is, an Eb/NO value under this code rate reaches a channel capacity.
The basic principle of Turbo decoding lies in iterative estimation of an information symbol based on an MAP algorithm, and inputting gradually updated prior information obtained by all pieces of statistically independent information after the previous decoding iteration. An iterative decoding concept is very similar to negative feedback, output external information is fed back to an input end to achieve an effect of amplifying the signal-to-noise ratio of the input end, thus stabilizing system output. By means of sufficient iterations, a final decoding decision may be obtained from a posterior probability Log Likelihood Ratio (LLR) value of any one decoder.
Most of the current MAP decoding schemes reduce the decoding delay and improve the throughput by using a decoding structure consisting of sub-blocks and sliding windows. In order to obtain more accurate boundary values, an existing method pre-calculates a part of overlap as a track back length. Under the restriction of the overlap length, this method is complicated in implementation and severe in performance degradation under high code rate, and the proportion of effective decoding time of each sub-block is low.
In view of this, the embodiment of the disclosure is intended to provide an MAP algorithm-based Turbo decoding method, an information symbol being sequentially divided into a plurality of sub-blocks, each sub-block including a plurality of sliding windows. The method may include: iteratively estimating an information symbol by using an MAP algorithm, acquiring α and β boundary values for each sliding window and each sub-block by means of window boundary value inheritance and block boundary value inheritance, and recursively calculating posterior probability Log Likelihood Ratio (LLR) values of a whole window and a whole block according to the α and β boundary values; and performing decoding decision according to the LLR values.
The acquiring an α boundary value for a sliding window by means of window boundary value inheritance and block boundary value inheritance may include: taking an α boundary value, acquired in a previous iteration, as an initial value of α in a present iteration, forwardly reading input data of the whole window of the sliding windows, and calculating an α value of the whole window.
Acquiring a β boundary value for a sliding window by means of window boundary value inheritance and block boundary value inheritance may include: taking a β boundary value, acquired in the previous iteration, as an initial value of β in the present iteration, reversely reading the input data of the whole window of the sliding windows, and calculating a β value of the whole window.
A Random Access Memory (RAM) array for storing the input data comprises two RAMs, configured to implement continuous calculation by means of a ping-pong operation.
In order to calculate β values, write and read addresses of the RAMs for storing the input data may range from 0 to K−1 and range from K−1 to 0 respectively, where K is a data length of a window.
The β values calculated for all the sliding windows may be stored in the RAMs, and the write and read addresses may range from K to 0 and range from 1 to K respectively, where K is a data length of a window.
For a first sliding window in a first sub-block, a first preset value is taken as the initial value of α, and for the first sliding window in a non-first sub-block, the α boundary value calculated for a last sliding window in a previous sub-block is inherited as the initial value of α to be updated in a present sub-block; and for the last sliding window in a last sub-block, a second preset value is taken as the initial value of β, and for the last sliding window in the non-last sub-block, the β boundary value calculated for the first sliding window in a subsequent sub-block is inherited as the initial value of β to be updated in the present sub-block.
The embodiment of the disclosure provides an MAP algorithm-based Turbo decoding apparatus. The apparatus may include: a first processing module and a second processing module. The first processing module is configured to iteratively estimate an information symbol by using an MAP algorithm, acquire α and β boundary values for each sliding window and each sub-block by means of window boundary value inheritance and block boundary value inheritance, and recursively calculate posterior probability Log Likelihood Ratio (LLR) values of α whole window and a whole block according to the α and β boundary values; and the second processing module is configured to perform decoding decision according to the LLR values.
The first processing module may be specifically configured to: take an α boundary value, acquired in a previous iteration, as an initial value of α in a present iteration, forwardly read input data of the whole window of the sliding windows, and calculate an α value of the whole window; and take a β boundary value, acquired in the previous iteration, as an initial value of β in the present iteration, reversely read the input data of the whole window of the sliding windows, and calculate a β value of the whole window.
The apparatus may further include a first storage module, configured to store the input data by means of a Random Access Memory (RAM) array comprising two RAMs, so as to implement continuous calculation by means of a ping-pong operation.
In order to calculate β values, write and read addresses of the RAMs for storing the input data may range from 0 to K−1 and range from K−1 to 0 respectively, where K is a data length of a window.
The apparatus may further include a second storage module, configured to store the β values calculated for all the sliding windows, the write and read addresses ranging from K to 0 and ranging from 1 to K respectively, where K is a data length of a window, and the β window boundary value acquired after calculation for a whole window is stored at a zero position.
The first processing module is configured to: for a first sliding window in a first sub-block, take a first preset value as an initial value of α, and for the first sliding window in a non-first sub-block, inherit an α boundary value calculated for the last sliding window in the previous sub-block as an initial value of α to be updated in the present sub-block; and for the last sliding window in a last sub-block, take a second preset value as an initial value of β, and for the last sliding window in the non-last sub-block, inherit a β boundary value calculated for the first sliding window in a subsequent sub-block as the initial value of β to be updated in the present sub-block.
The embodiment of the disclosure also provides a computer storage medium. Computer executable instructions may be stored therein. The computer executable instructions may be configured to execute the above method.
The embodiment of the disclosure provides an MAP algorithm-based Turbo decoding method and apparatus, and a computer storage medium. An information symbol is iteratively estimated by using an MAP algorithm, an α boundary value and β boundary value for each sliding window and an α boundary value and β boundary value for each sub-block are acquired by means of window boundary value inheritance and block boundary value inheritance, and LLR values of α whole window and a whole block are recursively calculated according to the α boundary values and the β boundary values; and decoding decision is performed according to the LLR values. According to the technical solutions of the embodiment of the disclosure, it is unnecessary to pre-calculate initial α and β states of each sub-block by using overlap, and it is also unnecessary to pre-calculate initial α and β states by using overlap of each sliding window, thereby resulting in a simple implementation structure, and prolonging effective decoding time of each sub-block.
In various embodiments of the disclosure, an α boundary value and β boundary value of each sliding window are acquired by means of window boundary value inheritance.
In order to deal with performance degradation of an MAP algorithm with overlap at a high code rate and complicated structure for implementing the algorithm, an embodiment of the disclosure provides an MAP algorithm-based Turbo decoding method. As shown in
Step 101: An information symbol is iteratively estimated by using an MAP algorithm, an α boundary value and β boundary value of each sliding window and an α boundary value and β boundary value of each sub-block are acquired by means of window boundary value inheritance, and LLR values of a whole window and a whole block are recursively calculated according to the α boundary values and the β boundary values.
In the embodiment of the disclosure, the information symbol is sequentially divided into a plurality of sub-blocks, each sub-block including a plurality of sliding windows.
Step 102: Decoding decision is performed according to the LLR values.
Optionally, acquiring the α boundary values of the sliding windows by means of the window boundary value inheritance includes: taking an α boundary value, acquired in a previous iteration, as an initial value of α in a present iteration, forwardly reading input data of the whole window of the sliding windows, and calculating an α value of the whole window.
Acquiring the β boundary values of the sliding windows by means of the window boundary value inheritance includes: taking a β boundary value, acquired in the previous iteration, as an initial value of β in the present iteration, reversely reading the input data of the whole window of the sliding windows, and calculating a β value of the whole window.
It is to be noted that the step of inheriting the α boundary values of the sliding windows is intended to ensure that an initial state for calculation of each recursive update of boundary values α0-α7, of each sliding window, along with increase of number of iterations, fully approaches a values α0-α7 corresponding to an original MAP decoding structure without sub-blocks and sliding windows, and the step of inheriting the β boundary values of the sliding windows is intended to ensure that an initial state for calculation of each recursive update of boundary values β0-β7 of each sliding window, along with increase of the number of iterations, fully approaches corresponding β values (ensuring that relative relationships of β0-β7 are consistent) in the original MAP decoding structure without the sub-blocks and the sliding windows.
Here, the boundary values β0-β7 of each sliding window β are stored in an RAM as initial values of the corresponding sliding windows β in a subsequent iteration. Based on a recursive β calculation process, it is necessary to store input data (system bits, check bits, and prior information) of a whole window of each sliding window in the RAMs, and then to calculate a β value of the whole window by reverse reading. Write and read addresses of the RAMs for storing the input data range from 0 to K−1 and range from K−1 to 0 respectively, where K is a data length of a window.
Optionally, an RAM array storing the input data includes two RAMs, so as to implement continuous calculation by means of a ping-pong operation. Here, in order to facilitate pipelined storage of the input data (system bits, check bits, and prior information) and continuous calculation of α and LLR, it requires two RAMs to execute an access operation (ping-pong operation).
Optionally, in order to calculate β values, write and read addresses of the RAMs storing the input data may range from 0 to K−1 and range from K−1 to 0 respectively, where K is a data length of a window.
Optionally, the β values calculated for all the sliding windows may be stored in the RAMs, the write and read addresses may range from K to 0 and range from 1 to K respectively, where K is a data length of a window, and a β window boundary value acquired by calculating a window is stored at a zero position.
Optionally, for the first sliding window in the first sub-block, an initial value of α is a first preset value, and for the first sliding window in the non-first sub-block, an α boundary value calculated for the last sliding window in the previous sub-block is inherited as an initial value of α to be updated in the present sub-block; and for the last sliding window in the last sub-block, an initial value of β is a second preset value, and for the last sliding window in the non-last sub-block, a β boundary value calculated for the first sliding window in the subsequent sub-block is inherited as an initial value of β to be updated in the present sub-block.
It is to be noted that the step of inheriting inter-block α and β boundary values is intended to ensure that regarding an initial state for calculating α and β of each sub-block through each recursive update, along with increase of the number of iterations, it fully approaches a relative relationship of eight states of corresponding α values α0-α7 and a relative relationship of eight states of corresponding β values β0-β7 in the original MAP decoding structure without the sub-blocks and the sliding windows. After calculation of the sliding windows is ended, boundary values of sub-blocks are stored, and inherited to a subsequent iteration as an initial value corresponding to each sub-block.
For example, the step of implementing inter-block α inheritance may include: inheriting α boundary values α0-α7 calculated for the last sliding window in the previous sub-block as an initial state of α to be updated in the present sub-block. For the initial value of α for the first sub-block, each iteration is [0, INF, INF, INF, INF, INF, INF, INF], where INF represents minus infinity.
For example, the step of implementing inter-block β inheritance may include: inheriting β boundary values β0-17 calculated for the first sliding window in the subsequent sub-block as an initial state of α to be updated in the present sub-block. For the initial value of β for the last sub-block, each iteration is [0, INF, INF, INF, INF, INF, INF, INF], where INF represents minus infinity.
In the embodiment of the disclosure, the initial value of α for each sub-block is obtained by inter-block inheritance. Since a is sequentially calculated, during calculation of α for each sliding window, it may be acquired just from the boundary value of the previous sliding window, without the need of inheriting a state value of the previous iteration. During calculation of β for each sliding window, it is necessary to inherit the window boundary value of the previous iteration.
Correspondingly, the embodiment of the disclosure also provides an MAP algorithm-based Turbo decoding apparatus. As shown in
The first processing module 21 is configured to iteratively estimate an information symbol by using an MAP algorithm, acquire an α boundary value and β boundary value for each sliding window by means of window boundary value inheritance, acquire an α boundary value and β boundary value for each sub-block by means of block boundary value inheritance, and recursively calculate LLR values of a whole window and a whole block according to the α boundary values and the β boundary values.
The second processing module 22 is configured to perform decoding decision according to the LLR values.
Optionally, the first processing module 21 is specifically configured to: take an α boundary value, acquired in a previous iteration, as an initial value of α in a present iteration, forwardly read input data of the whole window of the sliding windows, and calculate an α value of the whole window; and take a β boundary value, acquired in the previous iteration, as an initial value of β in the present iteration, reversely read the input data of the whole window of the sliding windows, and calculate a β value of the whole window.
Optionally, as shown in
Optionally, in order to calculate β values, write and read addresses of the RAMs storing the input data may range from 0 to K−1 and range from K−1 to 0 respectively, where K is a data length of a window.
Optionally, as shown in
Optionally, the first processing module 21 is specifically configured to: for the first sliding window in the first sub-block, take a first preset value as an initial value of α, and inherit an α boundary value calculated at the last sliding window in the previous sub-block as an initial value of α to be updated in the present sub-block for the first sliding window in the non-first sub-block; and acquire a second preset value serving as an initial value of β for the last sliding window in the last sub-block, and inherit a β boundary value calculated for the first sliding window in the subsequent sub-block as an initial value of β to be updated in the present sub-block for the last sliding window in the non-last sub-block.
The embodiment of the disclosure also provides a computer storage medium. Computer executable instructions are stored therein. The computer executable instructions are configured to execute the above method.
The technical solutions of the disclosure will be further elaborated below by means of specific embodiments.
In a first time window, input data (information bit Ys, check bit Yp and prior information La) of a window length LEN of a sliding window is stored in an RAM array; in a second time window, Ys, Yp and La are read from the RAM array, and β1 is calculated and stored in the RAM, where β1 represents a β value of a whole window of a first sliding window; and in a third time window, Ys, Yp and La are read from the RAM array, α1 and β2 are calculated and stored in the RAM array, and so on until α and β of the last sliding window of this sub-block are calculated.
Here, the RAM array storing the input data (information bit Ys, check bit Yp and prior information La) includes two RAMs of which the sizes are equal to the window length LEN, namely RAM(0) and RAM(1).
In an input data RAM address generation module, write address of RAM(0) and RAM(1) are addr(i)=0, 1, 2, . . . , LEN, a read address of α is addr(j)=0, 1, 2, . . . , LEN, and a read address of β is addr(k), k=LEN, LEN−1, LEN−2, . . . , 3, 2, 1.
Compared with a traditional pipelined calculation flow of a sliding window with a window boundary value calculated by means of overlap shown in
[0, INF, INF, INF, INF, INF, INF, INF]; and as for a sub-block n, an initial value of β is also a constant:
[0, INF, INF, INF, INF, INF, INF, INF]. An initial value of each window boundary value is used for the first iteration, eight states α0-α7 and β0-β7 of α and β are equally probable in default. Specifically,
αinitial=[0,0,0,0,0,0,0,0],βinitial=[0,0,0,0,0,0,0,0]
In an ith (i>1) iteration, a window boundary value of β is read by the RAM array storing β, and block boundary values of α and β are obtained by reading corresponding registers.
The RAM array storing β includes two RAMs of which the sizes are equal to the window length LEN, namely RAMβ(0) and RAMβ(1).
In an RAM address generation hardware module storing β, write addresses of RAMβ(0) and RAMβ(1) are addr(i), i=LEN, LEN−1, LEN−2, . . . , 1, 0, and read addresses of RAMβ(0) and RAMβ(1) are addr(j)=0 1 2 . . . , LEN.
As shown in
As shown in
According to the above description, the solutions of the embodiments of the disclosure have the following beneficial effects.
(1) α and β of sub-blocks and sliding windows may be directly calculated, and there is no need to pre-calculate initial states of α and β of each sub-block by using overlap or pre-calculate initial states of α and β by using overlap of each sliding window, thereby resulting in a simple implementation structure.
(2) An RAM prepared for storing input data (system bits, check bits and prior information) for calculation of overlap is not needed (as shown in
(3) As for each sub-block, calculation of two windows of overlap needed for calculation of a block boundary value is eliminated, thereby prolonging the effective decoding time of each sub-block (as shown in
(4) Conventionally, in order to deal with decoding performance degradation at a high perforation rate, overlap is lengthened, but this will accordingly increase the occupied storage space of an RAM and will cause the proportion of the effective decoding time of each sub-block to the total decoding time to be smaller. Along with increase of number of iterations, the method of the disclosure makes a relative relationship of eight states α0-α7 and β0-β7 of each window boundary value fully approach an original MAP situation without sub-blocks and sliding windows, and the overhead of an additional RAM is not increased.
Each of the above units may be implemented by a Central Processing Unit (CPU), a Digital Signal Processor (DSP) or a Field-Programmable Gate Array (FPGA) in an electronic device.
Those skilled in the art shall understand that the embodiments of the disclosure may be provided as a method, a system or a computer program product. Thus, forms of hardware embodiments, software embodiments or embodiments integrating software and hardware may be adopted in the disclosure. Moreover, a form of the computer program product implemented on one or more computer available storage media (including, but are not limited to, a disk memory, an optical memory and the like) containing computer available program codes may be adopted in the disclosure.
The disclosure is described with reference to flow charts and/or block diagrams of the method, the device (system) and the computer program product according to the embodiments of the disclosure. It will be appreciated that each flow and/or block in the flow charts and/or the block diagrams and a combination of the flows and/or the blocks in the flow charts and/or the block diagrams may be implemented by computer program instructions. These computer program instructions may be provided for a general computer, a dedicated computer, an embedded processor or processors of other programmable data processing devices to generate a machine, such that an apparatus for implementing functions designated in one or more flows of the flow charts and/or one or more blocks of the block diagrams is generated via instructions executed by the computers or the processors of the other programmable data processing devices.
These computer program instructions may also be stored in a computer readable memory capable of guiding the computers or the other programmable data processing devices to work in a specific mode, such that a manufactured product including an instruction apparatus is generated via the instructions stored in the computer readable memory, and the instruction apparatus implements the functions designated in one or more flows of the flow charts and/or one or more blocks of the block diagrams.
These computer program instructions may also be loaded to the computers or the other programmable data processing devices, such that processing implemented by the computers is generated by executing a series of operation steps on the computers or the other programmable devices, and therefore the instructions executed on the computers or the other programmable devices provide a step of implementing the functions designated in one or more flows of the flow charts and/or one or more blocks of the block diagrams.
The above is only the preferred embodiments of the disclosure and not intended to limit the scope of protection of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014 1 0307603 | Jun 2014 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2014/086524 | 9/15/2014 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2016/000321 | 1/7/2016 | WO | A |
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