Claims
- 1. A processing system comprising:
- an engine including,
- a chip having a plurality of functional circuits for performing a plurality of functions,
- a plurality of Input/Output pins,
- a plurality of selectable connectors internal to said chip and configured to connect selected ones of the functional circuits provided on said chip to selected ones of the Input/Output pins, and
- a selection device configured to select said selectable connectors, and in a first mode, connecting a first set of said functional circuits to a first set of said Input/Output pins, and in a second mode, connecting a second set of said functional circuits to a second set of said Input/Output pins, so that different functional circuits are functionally accessible at said Input/Output pins via said connectors as selected by said selection device in said second mode; and
- a controller configured to control the connectors in relation to the connections selected by means of the selection device.
- 2. A distributed system for performing a plurality of system functions comprising:
- a plurality of interconnected engines, each including,
- a plurality of functional circuits for performing a plurality of respective engine functions,
- a plurality of Input/Output pins, and
- a plurality of selectable connectors internal to each said engine and configured to connect selected ones of the functional circuits to selected ones of the Input/Output pins;
- connections which interconnect said Input/Output pins of said engines; and
- a controller configured to control said selectable internal connectors of said plurality of interconnected engines such that a selected functional circuit of one engine receives as an input, via the Input/Output pins of said one engine, said connections and the Input/Output pins of an other engine, an output of a selected functional circuit of said other engine.
- 3. The distributed system of claim 2, wherein each said engine comprises a chip having said selectable connectors internal to said chip, and the chip of each engine is identical.
- 4. A distributed system comprising:
- a plurality of interconnected engines, each capable of performing a common system function and each including,
- a plurality of functional circuits for performing a plurality of respective engine functions,
- a plurality of Input/Output pins, and
- a plurality of selectable internal connectors internal to each said engine and configured to connect selected ones of the functional circuits to selected ones of the Input/Output pins;
- connections which interconnect at least one Input/Output pin of at least one engine with at least one Input/Output pin of an other engine, and
- a controller configured to control said selectable connectors of said plurality of engines such that a selected functional circuit of said at least one engine receives as an input an output of a selected functional circuit of said other engine and portions of said common system function are distributed for performance by functional circuits of different of said interconnected engines.
- 5. The distributed system of claim 4, wherein each said engine comprises a chip having said selectable connectors internal to said chip, and the chip of each engine is identical.
Parent Case Info
This application is a continuation of application Ser. No. 08/478,313, filed Jun. 7, 1995 now U.S. Pat. No. 5,671,433, which is a continuation of application Ser. No. 07/947,471, filed Sep. 18, 1992, now abandoned.
US Referenced Citations (8)
Continuations (2)
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Number |
Date |
Country |
Parent |
478313 |
Jun 1995 |
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Parent |
947471 |
Sep 1992 |
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