1. Field of the Invention
The invention relates to a look-up table, and more particularly, to a look-up table architecture.
2. Description of the Prior Art
Look-up tables (LUTs) are a circuit component frequently used in many kinds of electronic devices. Using a look-up table as an auxiliary tool in a mapping apparatus, an output value of a complex mathematical function corresponding to an input value could be easily determined according to the data stored in the look-up table. Hence, a complicated computing process and delay caused by the complicated computing process could be avoided.
A look-up table is always implemented through using a memory (such as a SRAM or other kinds of memory). The memory size determines the price of a memory. Some conventional methods for improving memory usage of look-up table mapping are developed. For example, U.S. Pat. No. 5,937,088 is related to “An apparatus and a method for improving memory usage of look-up table mapping”, and U.S. Pub. No. 2003/0123304 is related to “Look-up table methods for reducing the use of memory volume and system thereof”.
It is one of many objectives of the claimed invention to provide a mapping apparatus and a method thereof to reduce used memory size.
It is another one of many objectives of the claimed invention to provide a mapping apparatus and a method thereof to enhance the utilization efficiency of the look-up table.
According to the claimed invention, a mapping method is disclosed. The mapping method includes utilizing the look-up table to store a plurality of basic values and a plurality of delta value sets, wherein a basic value corresponds to a delta value set; determining a first basic value and a first delta value set according to an input value and generating an output value according to the first basic value and the first delta value set.
According to the claimed invention, a mapping apparatus is disclosed. The apparatus includes a look-up table for storing a plurality of basic values and a plurality of delta value sets, and determining a first basic value and a first delta value set according to an input value; and the arithmetic circuit coupled to the look-up table for generating an output value according to the first basic value and the first delta value set.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In a second embodiment of the present invention, a memory is utilized to store a plurality of basic values and a plurality of delta value sets (each delta value set includes a single delta value or more than one delta values). In the memory, a basic value corresponds to a delta value set, and the delta value set represents a difference between the basic value and another basic value adjacent to the basic value in the memory.
The arithmetic circuit 220 includes a multiplier 222 and an adder 224. The multiplier 220 multiplies a delta value DV outputted by the LUT 210 with a multiplicand M to generate an increment value IV, where M is determined according to the input value I (ex. M=(I mod 4)/4). The adder 224 adds a basic value BV outputted by the LUT 210 with the increment value IV to generate the output value O.
Please take a look at some specific examples. When I7 is used as the input value I, the LUT 210 outputs O4 and Δ8,4 as the basic value BV and the delta value DV respectively. The multiplicand M is set as ¾ (since (7 mod 4)/4=¾). Hence, the output value O is O=O4+(¾)×Δ8,4. Similarly, when I12 is used as the input value I, the LUT 210 outputs O12 and Δ16,12 as the basic value BV and the delta value DV respectively. The multiplicand M is set as 0 (since (12 mod 4)/4=0). Hence, the output value O is O=O12+0×Δ16,12=O12.
The arithmetic circuit 320 includes a first adder 322, a first multiplexer 324, a second multiplexer 326, a multiplier 328, and a second adder 330. The first adder 322 combines a basic value BV with a first delta value DV1 outputted by the LUT 310 to generate a combined value CV. The first multiplexer 324 receives the basic value BV or the combined value CV, and selectively chooses one of these two values as an output. The second multiplexer 326 receives the first delta value DV1 and a second delta value DV2 outputted by the LUT 310, and selectively chooses one of these two values as an output. Both the first multiplexer 324 and the second multiplexer 326 could be controlled according to the input value I. For example, if (I mod 8)<=4, than the first multiplexer 324 is controlled to output the basic value BV, and the second multiplexer 326 is controlled to output the first delta value DV1; if (I mod 8)>4, than the first multiplexer 324 is controlled to output the combined value CV, and the second multiplexer 326 is controlled to output the second delta value DV2. The multiplier 328 multiplies the output of the second multiplexer 326 (DV1 or DV2) with a multiplicand M to generate an increment value IV, where the multiplicand M is determined according to the input value I (ex. when (I mod 8)=4, M is determined to be 1; when (I mod 8)≠4, M is determined according to: M=(I mod 4)/4). The adder 330 adds the output of the first multiplexer 324 (BV or BV+DV1) with the increment value IV to generate the output value O.
Please take a look at some specific examples, when I10 is used as the input value I, the LUT 310 outputs O8, Δ12,8 and Δl6,12 as the basic value BV, the first delta value DV1, and the second delta value DV2 respectively. Since (10 mod 8)=2<4, the first multiplexer 324 is controlled to output the basic value BV (i.e. O8), and the second multiplexer 326 is controlled to output the first delta value DV1 (i.e. Δ12,8). Since (10 mod 4)/4= 2/4, M is determined as 2/4. Hence, the output value generated by the arithmetic circuit 320 is O=O8+( 2/4)×Δ12,8. Similarly, when I15 is used as the input value I, the LUT 310 outputs O8, Δ12,8 and Δ16,12 as the basic value BV, the first delta value DV1, and the second delta value DV2 respectively. Since (15 mod 8)=7>4, the first multiplexer 324 is controlled to output BV+DV1 (i.e. O8+Δ12,8), and the second multiplexer 326 is controlled to output the second delta value DV2 (i.e. Δ16,12). Since (15 mod 4)/4=¾, M is determined as ¾. Hence, the output value generated by the arithmetic circuit 320 is O=O8+Δ12,8+(¾)×Δ16,12.
According to the present invention, the required memory space in these three embodiments is smaller than that is required in the prior art. Taking a mathematical function having 1024 input values (from I0˜I1023) and 1024 corresponding output values (from O0˜O1023) as an example. Assume that each one of the basic values (such as an OL, an OH, or a BV) occupies ten bits, the mapping apparatus 100 shown in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
4538299 | DeForest | Aug 1985 | A |
5471411 | Adams et al. | Nov 1995 | A |
5781903 | Rusterholz | Jul 1998 | A |
5937088 | Hsu | Aug 1999 | A |
6122640 | Pereira | Sep 2000 | A |
6446259 | Brett | Sep 2002 | B1 |
20030123304 | Wei et al. | Jul 2003 | A1 |