In a shingled magnetic recording (SMR) drive, data tracks are written in a partially overlapped manner to increase data density and overall drive capacity. An SMR drive may be divided into multiple shingle zones according to one approach of formatting an SMR drive. In such a case, each shingle zone has a user data area and a guardband area. Due to the overlapping nature of the written tracks, a guardband may be necessary to separate two adjacent shingle zones to prevent data corruption.
The features and advantages of the implementations of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. The drawings and the associated descriptions are provided to illustrate implementations of the disclosure and not to limit the scope of what is claimed.
In the following detailed description, numerous specific details are set forth to provide a full understanding of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the various implementations disclosed may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail to avoid unnecessarily obscuring the various implementations.
The host 110 communicates to the DSD 100 through the host interface 120. The host interface 120 communicates with the controller 122, which further communicates with the solid state memory 124 and the VCM 130. The VCM 130 operates in conjunction with the actuator arm 132 to position the head 140 over a desired track 155 of the platter 150. Although not shown in
To operate (i.e. read, write, etc.) on a desired location or sector of the platter 150, the VCM moves the head 140 to the desired sector.
In
Defects may be present on the platters 150. In other words, certain sectors 170 may not be usable. However, ABA addressing includes all blocks, good or bad. To prevent the bad blocks from being used, another addressing scheme may be used to skip over the bad blocks.
Returning to
Shingled magnetic recording (SMR) can improve the density of magnetic disk storage, such as the platters 150. Writing data to a magnetic medium generally requires a stronger magnetic field than reading data. As such, the head 140 writes a wide track, but reads a narrow track. SMR takes advantage of the discrepancy between the width of the written track and the width of the read track. The tracks can be placed closer to improve density. Because only a narrow track is read, the rest of the wide written track can be overwritten while maintaining the integrity of the narrow track for reading. As long as the narrow track is not overwritten, adjacent tracks may overlap.
To ensure the guardbands and other restricted areas are not used, they must be mapped out during the drive formatting process. To use conventional mapping schemes, the restricted areas may be treated as defects. However, due to the large number of shingle zones (e.g. 20,000 shingle zones), many sectors are designated as defective in such conventional mapping schemes. As a result, conventional mapping schemes would require larger tables and more processing time. For example, the guardband, or other restricted areas such as write logs can be treated as defects and added to the PDList. A write log of a track contains metadata of the written user data on that track. There may be two write logs per track for redundancy purposes. For example, one write log near the middle of a track may refer to the first half of the track, and a second write log near the end of the track may refer to the second half of the track. The host LBA would not have addresses for the restricted areas, similar to actual defects. Before the DSD 100 is used, it must build the PDList. However, because entire tracks or significant portions of tracks may be restricted, the iterative process of building the PDList becomes a time-consuming process, as each sector is essentially checked as good or bad/restricted.
The positions labeled with A demark the starting ABA of each shingle zone 471-473. The positions labeled with B demark the starting SBA of the shingle zones 471-473. The positions labeled C demark the starting ABA of the guardbands 481-483. Although in certain implementations MLBA or CHS are used rather than ABA, for the sake of simplicity, ABA is described in
Mapping out the SBAs avoids the time-intensive process of building the PDList with restricted areas mapped as defects. The SBAs can be mapped out in a separate process. In addition, because the restricted areas are not random or nondeterministic sectors, such as defects, the process can take advantage of being able to calculate the restricted areas rather than having to iteratively inspect each sector. In other words, because SBA mapping follows a predictable pattern and defect mapping does not, separating the two mapping processes enhances the efficiency of the overall process. The mapping could also be done in the field rather than at the factory. For instance, the PDList may be rebuilt on the fly to account for new defects. The SBAs would be remapped afterwards.
At 530, the restricted areas are calculated. By knowing or setting various parameters, the restricted areas can be calculated. For example, if the number of good sectors, percent of sectors to use as guardbands, number of shingle zones, and number of tracks per shingle zone are known, the average shingle zone size can be calculated, and further used to calculate the guardband sizes and locations. With the parameters kept static, the guardband locations will be consistent for subsequent calculations. Taking advantage of the calculable nature of the restricted areas yields significant reductions in time over conventional mapping schemes. In other implementations, the restricted areas may be calculated by other algorithms.
At 540, the locations of the restricted areas are mapped out. For example, SBAs are mapped to good blocks, but not assigned to restricted areas. The mapping may also take advantage of the calculable nature of the restricted areas. In other implementations, 530 and 540 may be combined or performed simultaneously.
Having the restricted areas calculated for an SBA layer provides for a quicker mapping of restricted areas and does not overburden the defect detection process. In this regard, the PDList may be unsuitable for storing the guardbands and other restricted areas as defects. For example, the PDList may only hold about 30,000 entries. A DSD may have 10,000 shingle zones, each requiring two guardbands or restricted areas for a total of at least 20,000 entries as defects. Building the PDList with the guardbands as defects may take hours. In contrast, the SBA calculation may take less than a minute.
Those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, and processes described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Furthermore, the foregoing processes can be embodied on a computer readable medium which causes a processor or computer to perform or execute certain functions.
To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, and modules have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of ordinary skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, units, modules, and controllers described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The activities of a method or process described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The steps of the method or algorithm may also be performed in an alternate order from those provided in the examples. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable media, an optical media, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC).
The foregoing description of the disclosed example implementations is provided to enable any person of ordinary skill in the art to make or use the implementations in the present disclosure. Various modifications to these examples will be readily apparent to those of ordinary skill in the art, and the principles disclosed herein may be applied to other examples without departing from the spirit or scope of the present disclosure. The described implementations are to be considered in all respects only as illustrative and not restrictive and the scope of the disclosure is, therefore, indicated by the following claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
This application claims the benefit of U.S. Provisional Application No. 61/823,241, filed on May 14, 2013, which is hereby incorporated by reference in its entirety, and hereby incorporates by reference in their entirety U.S. application Ser. No. 13/316,039, filed on Dec. 9, 2011, U.S. application Ser. No. 13/709,470, filed on Dec. 10, 2012, and U.S. application Ser. No. 12/729,159, filed on Mar. 22, 2010.
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