Patent Application
20230222277
This application claims the benefit of priority to Taiwan Patent Application No. 111100661, filed on Jan. 7, 2022. The entire content of the above identified application is incorporated herein by reference.
Some references, which may include patents, patent applications and various publications, may be cited and discussed in the description of this disclosure. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to the disclosure described herein. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference.
The present disclosure relates to a calibration method and a calibration system, and more particularly to a margin calibration method and a margin calibration system for static timing analysis.
The importance of static timing analysis (STA) in integrated circuit (IC) mass production is generally demonstrated through the following two aspects:
(1) Operating speed of a chip: when an assessment of the actual operating speed is accurate, it can determined whether a chip complies with its product specification.
(2) Yield of a chip: since in general the yield of the chip may decrease as the operating speed increases, accurate static timing analysis results can be used to monitor an actual yield when the chip speed is increased, so as to confirm whether the chip functions and is ready for mass production. However, when the static timing analysis results are inaccurate, it cannot be relied on as to whether the chip can, after the chip speed is increased, function and ready for mass production. During manufacturing, this can lead to the chip speed being lowered for conservative purpose. However, such a reduction in chip speed results in worse chip performance and power consumption and area (i.e., PPA) than what can actually be achieved by the chip, thus resulting in increased costs.
In a margin estimation that uses the existing STA method, a fab end provides, according to physical disturbance characteristics and empirical rules for mass production of transistors, a margin to a design end, which can be used in the STA for circuit design. The aim is to obtain more accurate results when analyzing the circuit.
Since the margin is obtained based on the transistor level, when the margin is applied to the design logic level, there will be errors due to different analysis and application conditions, which may cause the analysis results to either be more optimistic or more pessimistic. When the analysis results are too optimistic, a drop in yield may be foreseen. Conversely, when the analysis results are too pessimistic, the PPA can be expected to be worse than what can realistically be achieved, thus resulting in increased costs.
In response to the above-referenced inadequacies, the present disclosure provides a margin correction method and a margin correction system for static timing analysis that are capable of obtaining an accurate margin.
In one aspect, the present disclosure provides a margin calibration method for static timing analysis, and the margin calibration method includes: measuring performance on a plurality of dies on a to-be-tested chip with a target circuit to obtain a plurality of performance data records of critical paths of the plurality of dies; obtaining a plurality of simulation data records for simulating performances of the plurality of dies, respectively; executing a static timing analysis (STA) tool to perform static timing analysis on the target circuit according to the simulation data records, for obtaining a plurality of timing analysis results corresponding to the critical paths of the plurality of dies; statistically calculating a simulation process corner based on the plurality of timing analysis results; obtaining a measurement process corner based on the plurality of performance data records; establishing a statistical model that defines a margin based on a difference between the measurement process corner and the simulation process corner; substituting the plurality of timing analysis results and the measurement process corner into the statistical model and executing a model fitting algorithm for fitting the statistical model to a target model for obtaining the margin, wherein the target model defines a first function and a second function that are equal, the first function being a function of the measurement process corner, and the second function being a function of the timing analysis result; and executing the STA tool to perform static timing analysis on the target circuit according to the plurality of simulation data records and the margin, so as to obtain a plurality of calibrated timing analysis results corresponding to the plurality of dies.
In another aspect, the present disclosure provides a margin calibration system for static timing analysis, and the margin calibration system includes a memory and a processor. The memory is configured to store a plurality of computer-executable instructions. The processor is electrically coupled to the memory, and configured to retrieve and execute the computer-executable instructions to perform: measuring performance on a plurality of dies on a to-be-tested chip with a target circuit to obtain a plurality of performance data records of critical paths of the plurality of dies; obtaining a plurality of simulation data records for simulating performances of the plurality of dies, respectively; executing a static timing analysis (STA) tool to perform static timing analysis on the target circuit according to the simulation data records, for obtaining a plurality of timing analysis results corresponding to the critical paths of the plurality of dies; statistically calculating a simulation process corner based on the plurality of timing analysis results; obtaining a measurement process corner based on the plurality of performance data records; establishing a statistical model that defines a margin based on a difference between the measurement process corner and the simulation process corner; substituting the plurality of timing analysis results and the measurement process corner into the statistical model and executing a model fitting algorithm, for fitting the statistical model to a target model for obtaining the margin, in which the target model defines a first function and a second function that are equal, the first function being a function of the measurement process corner, and the second function being a function of the timing analysis result; and executing the STA tool to perform static timing analysis on the target circuit according to the plurality of simulation data records and the margin, so as to obtain a plurality of calibrated timing analysis results corresponding to the plurality of dies.
Therefore, in the margin calibration method and the margin calibration system for static timing analysis provided by the present disclosure, an optimal margin can be estimated by numerical optimization for STA, thereby saving computing and measurement resources, improving yield, and shortening development times.
These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure.
The described embodiments may be better understood by reference to the following description and the accompanying drawings, in which:
The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Like numbers in the drawings indicate like components throughout the views. As used in the description herein and throughout the claims that follow, unless the context clearly dictates otherwise, the meaning of “a”, “an”, and “the” includes plural reference, and the meaning of “in” includes “in” and “on”. Titles or subtitles can be used herein for the convenience of a reader, which shall have no influence on the scope of the present disclosure.
The terms used herein generally have their ordinary meanings in the art. In the case of conflict, the present document, including any definitions given herein, will prevail. The same thing can be expressed in more than one way. Alternative language and synonyms can be used for any term(s) discussed herein, and no special significance is to be placed upon whether a term is elaborated or discussed herein. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms is illustrative only, and in no way limits the scope and meaning of the present disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given herein. Numbering terms such as “first”, “second” or “third” can be used to describe various components, signals or the like, which are for distinguishing one component/signal from another one only, and are not intended to, nor should be construed to impose any substantive limitations on the components, signals or the like.
The memory 10 is any storage device that can be configured to store data, such as, but not limited to, a random access memory (RAM), a read only memory (ROM), a flash memory, a hard disk or other storage device that can be configured to store data. The memory 10 is configured to store at least a plurality of computer readable instructions 100. In one embodiment, the memory 10 can also be configured to store temporary data that are generated when operations are performed by the processor 11.
The processor 11 is electrically coupled to the memory 10, and is configured to access computer-readable instructions 100 from the memory 10, so as to control components in the optimizing device 1 to perform functions of the optimizing device 1.
The network unit 12 is configured to perform network access under a control of the processor 11. The storage unit 13 can be, for example, but not limited to, a magnetic disk or an optical disk, to store data or instructions under the control of the processor 11. The input/output (I/O) interface 14 can be operated by a user to communicate with the processor 11 in order to input and output data.
Referring to
Step S20: measuring performance on a plurality of dies on a to-be-tested chip that includes a target circuit to obtain a plurality of performance data records of critical paths of the plurality of dies.
For example, signal sources with different frequencies can be input to the to-be-tested chip through a network analyzer to measure operating frequencies of the plurality of dies, and then a plurality of measured minimum passing frequencies of the dies can be obtained as the plurality of performance data records. Reference can be made to
Step S21: obtaining a plurality of simulation data records for simulating performances of the plurality of dies, respectively.
The simulation data records 101 represent relevant data of the target circuit that are predetermined to be applied with the static timing analysis, the simulation data records 101 can be provided by the fab end, and can be, for example, model parameters of a transistor, including parameters such as a length, a width, an oxide layer thickness, and an electrical conductivity of the transistor.
Step S22: executing a static timing analysis (STA) tool to perform static timing analysis on the target circuit according to the simulation data records, so as to obtain a plurality of timing analysis results corresponding to the critical paths of the plurality of dies.
The static timing analysis is known to those skilled in the art and used for calculating and predicting timings of digital circuits in an integrated circuit design, so as to measure delays of a circuit in different operation stages, and to test performance of the circuit at a specified operating speed.
For example, in one embodiment of the present disclosure, an integrated circuit design of the target circuit can include a plurality of signal transmission paths, and after the static timing analysis is performed (for example, the static timing analysis tool 102 is executed by the processor 11, and the target circuit is analyzed according to the simulation data record 101), the path that causes the largest signal transmission delay among these signal transmission paths is regarded as a critical path. In this step, relevant information of the critical path is obtained by simulation and regarded as a timing analysis result 103, which can be stored in the memory 10.
Step S23: statistically calculating a simulation process corner based on the timing analysis results.
In this step, the static timing analysis can be performed on the target circuit to obtain a plurality of setup times for multiple ones of the critical paths of the plurality of dies.
The setup time represents the minimum amount of time a data signal should be held stable before a rising edge of an input clock signal occurs, and the setup time is determined by a clock period of the clock signal, an uncertainty of the clock signal, and slack.
Slack is a difference between actual time used and time required for an integrated circuit design, and is a term that indicates whether the integrated circuit design meets a timing condition. A positive slack represents that the timing condition is met (slack of timing), and a negative timing slack means that the timing condition is not met (a lack of timing).
After the setup times are obtained, these setup times can be converted into a plurality of simulation minimum passing frequencies according to the following equation (1).
Simulation minimum passing frequency=[1/(clock period of clock signal−uncertainty of clock signal−slack)] Equation (1);
A statistical algorithm 104 can then be executed by the processor 11 to perform statistics on the simulated process corners and the measured process corners. In this case, the statistics include global statistics and local statistics. Reference is made to
Therefore, the global statistics can be represented, for example, by the following equation (2):
Global corner=μ(diei) Equation (2);
where global corner represents the global process corner, μ(diei) represents an average of the process corners of i dies in the same chip, and the process corners can be obtained by making measurements (such as step S20) or can be obtained by performing a simulation (such as step S21 to S23).
Therefore, when the simulation process corners need to be extracted from the timing analysis results, these simulation minimum passing frequencies can be averaged according to the above-mentioned global statistics, so as to obtain a simulation global process corner.
Reference is made to
Therefore, the local statistics can be represented, for example, by the following equation (3):
Local corner=σ(diei)=σ(Die1_i−Die2_i)/20.5 Equation (3);
where local corner represents the local process corner, σ(diei) represents the variation of the process parameters of i dies in the same wafer, and the process parameters can be obtained by measurement (such as step S20) or simulation (such as steps S21 to S23).
A statistical derivation of equation (3) is as follows.
Let N(μ, σ) be a normal distribution function with mean μ and variance σ.
Let X1_i be a first process corner in an i-th die and satisfy the following equation (4):
X
1_i
=N
1_i(μglobal_1,μglobal,1)+N1_i(μlocal_1,σlocal_1) Equation (4);
Let X2_i be a second process corner in the i-th die and satisfy the following equation (5):
X
2 _i
=N
1_i(μglobal_2,σglobal_2)+N2_i(μlocal_2,σlocal_2) Equation (5);
Random first and second process corners are subtracted, and a variance σ is taken as shown in the following equation (6):
σ2(X1_i−X2_i)=σ2{[N1_i(μglobal_1,μglobal_1)+N1_i(μlocal_1,σlocal_1)]−[N1_i(μglobal_2,σglobal_2)+N2_i(μlocal_2,σ1ocal_2)]} Equation (6);
Since global characteristics are the same in the same die, N1_i (μglobal_1,σglobal_1)=N1_i (μglobal_2, σglobal_2).
Next, the equation (6) can be expressed as the following equation (7):
σ2(X1_i−X2_i)=σ2local_1+σ2local_2−2Cov(local_1,local_2) Equation (7);
where the local variations are always the same: σ2local_1=σ2local_2=σ2local,
and 2Cov(local_1, local_2)=0;
Therefore, it can be obtained that σ2local=σ2(X1_i−X2_i)/2, and σlocal=σ(X1_i−X2_i)/20.5.
Therefore, taking a conversion of the minimum simulation process corner as an example, when the simulation process corner need to be extracted from the timing analysis results, based on the above-mentioned local statistics, simulation minimum passing frequencies corresponding to the dies with the relationship of paired design can be extracted and subtracted two by two to calculate a variance, which is then divided by a statistical coefficient (that is, 20.5 obtained by the above derivation) to obtain a local simulation process corner.
Step S24: obtaining a measurement process corner based on the plurality of performance data records.
In this step, the aforementioned global statistics and local statistics can be used to average these performance data records to obtain a global measurement process corner (global corner), and the performance data records corresponding to the dies with the relationship of paired design are extracted and subtracted two by two to calculate a variance, which is then divided by the statistical coefficient to obtain a local measurement process corner.
In one embodiment of the present disclosure, the performance data records for performing the global statistics and the local statistics are the minimum passing frequencies obtained in step S20.
Step S25: establishing a statistical model that defines a margin as a difference between the measurement process corner and the simulation process corner.
In this step, the statistical model can include a global statistical model and a local statistical model.
The global statistical model is defined as follows:
Global margin=|measurement global process corner−simulation global process corner|;
The local statistical model is defined as follows:
Local margin=|measurement local process corner−simulation global process corner|.
Step S26: substituting the plurality of timing analysis results and the measurement process corner into the statistical model and executing a model fitting algorithm, so as to fit the statistical model to a target model to obtain the margin. For example, the processor 11 can be configured to execute a model fitting algorithm 105, and the target model is defined as shown in the following equation (8):
fMeasure=fSimulation Equation (8);
where fMeasure is a function of measurement process corner, and fSimulation is a function of timing analysis result.
Therefore, the target model can be further obtained as fMeasure−fSimulation=0.
Therefore, the global statistical model and the local statistical model can be respectively fitted with the target model to obtain the global margin and the local margin, respectively.
For example, the measurement global process corner and the simulation global process corner can be substituted into the global statistical model to fit the global statistical model to the target model (fMeasure_global=fSimulation_global), so as to obtain the global margin.
fMeasure_global is a function of the measurement global process corner, and fSimulation_global is a function of the simulation global process corner.
Alternatively, the measurement local process corner and the simulation local process corner can be substituted into the local statistical model, so as to fit the local statistical model to the target model (fMeasure_local=fSimulation_local) to obtain the local margin.
fMeasure_local is a function of the measurement local process corner, and fSimulation_local is a function of simulation local process corner.
For example, the model fitting algorithm can utilize a bisection method, for example. Reference is made to
As shown in
Step S60: randomly generating a first value and a second value between 0 and 1.
Step S61: taking the first value, the second value and an intermediate value between the first value and the second value as the margin, and substituting the margin into the statistical model, the first value being greater than the second value.
For example, the aforementioned statistical model is simplified to a function f(margin) of the margin, the first value, the second value and the intermediate value are respectively denoted as STAp_h, STAp_l and STAp_m, and STAp is a to-be-obtained margin that satisfies f(STAp)=0.
At this time, STAp_h and STAp_l between 0 and 1 are randomly generated and substituted into f(STAp_h), f(STAp_l) and f(STAp_m) to calculate values of f(STAp_h), f(STAp_l) and f(STAp_m), respectively.
Step S62: determining whether a fitting condition is met, and using the first value and the second value in response to the fitting condition being met to calculate the margin.
For example, whether f(STAp_h)*f(STAp_m) is less than 0 or not can be firstly determined. If so, STAp_l is replaced with STAp_m, if not, STAp_h is replaced with STAp_m, determining whether f(STAp_h)−f(STAp_l) is less than or equal to 95% confidence interval as the fitting condition.
If f(STAp_h)−f(STAp_l) is greater than the 95% confidence interval, the bisection method returns to step S60.
If f(STAp_h)−f(STAp_l) is less than or equal to the 95% confidence interval, the margin is calculated according to STAp_h and STAp_l at this time.
Step S27: executing the STA tool to perform static timing analysis on the target circuit according to the plurality of simulation data records and the margin, so as to obtain a plurality of calibrated timing analysis results corresponding to the plurality of dies.
Advantages of using the margin calibration method and the margin calibration system for static timing analysis provided by the present disclosure can include those set forth in the following list:
(1) High applicability: the margin calibration method of the present disclosure can perform margin calibration according to different types of circuits and components. For example, the margin correction method can be applied to the design of CPUs with ultra-high-speed requirements or automotive chips with ultra-high yield requirements, or can be applied to transistors with high, medium, and low threshold voltages.
(2) Saving computing resources: the optimal STA parameters estimated by the numerical optimization method can reduce verification time using the existing simulation programs (such as SPICE, Monte Carlo, etc.) having huge computational loads.
(3) Saving measurement resources: the use of statistical derivation and regression analysis can reduce the number of hardware measurements to save a lot of time and human resources.
(4) High yield can be achieved, so as to afford high reliability.
(5) Shortened development schedule: before a mass production of the circuit, the calibrated margin can be obtained first, which can effectively shorten the development schedule and prevent repeated consumption of various resources from repeated modification of the circuit.
In conclusion, in the margin calibration method and the margin calibration system for static timing analysis provided by the present disclosure, an optimal margin can be estimated by numerical optimization for STA, thereby saving computing and measurement resources, improving yield, and shortening development times.
The aforementioned description for the composite nanometer material structure 2 of the first embodiment is merely an example, and is not meant to limit the scope of the present disclosure.
The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.
The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.
| Number | Date | Country | Kind |
|---|---|---|---|
| 111100661 | Jan 2022 | TW | national |
