The invention will hereafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements, and:
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
One or more specific embodiments of the present invention will be described below. It is specifically intended that the present invention not be limited to the embodiments and illustrations contained herein, but include modified forms of those embodiments including portions of the embodiments and combinations of elements of different embodiments as come within the scope of the following claims. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. Nothing in this application is considered critical or essential to the present invention unless explicitly indicated as being “critical” or “essential.”
The present invention will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Referring now to the drawings wherein like reference numbers correspond to similar components throughout the several views and, specifically, referring to
Turning now to
The PMOS transistor 305 is diode-connected and the gates of the PMOS transistors 305, 310 are coupled to one another to form the current source 300. The gate-source voltage, VGS, of the PMOS transistor 305 equals its drain-source voltage, VDS, and the VGS of the PMOS transistors 305, 310 are equal. The gate of the PMOS transistor 315 is coupled to the drain of the PMOS transistor 310, so that the PMOS transistor 315 may operate as a feedback device that forces the VDS of the PMOS transistors 305, 310 to be equal to eliminate current imbalance and cancel the effects of the Early voltage, VA.
The NMOS transistors 320, 325 form a voltage loop with the PNP transistors 335, 340 to generate the reference current, IREF. In the illustrated embodiment the reference currents are equal in both legs of the master bias current generator 215 due to the transistors 305, 310 in the current source 300 having the same aspect ratios (W/L). The current in the reference legs 350, 355 may be scaled with respect to one another by varying the aspect ratios of the transistors 305, 310. The NMOS transistor 330 biases the gate voltage of the transistors with a voltage equal to the emitter-base voltage, VEB, of the PNP transistor 345 plus the VGS of the NMOS transistor 330.
The emitter area of the transistor 340 is a multiple (M×A) of the emitter area (A) of the transistor 335. The aspect ratios of the NMOS transistors 320, 325 are also multiples of one another. For example, if the aspect ratio of the transistor 325 is represented as W/L1, the aspect ratio of the transistor 320 is K×(W/L1). The transistors 330, 345 in the bias leg 360 are sized to match the corresponding pair in one of the reference legs 350, 355 (e.g., W/L1 and M×A or K×(W/L1) and A).
Generally, the master bias current generator 215 generates different emitter-base voltages, VEB, for the PNP transistors 335, 340 due to the different emitter areas and causes that voltage difference to drop across the VGS of the NMOS transistors 320, 325 having different aspect ratios. In the following equations, the NMOS transistors 320, 325 are referred to as M1 and M2, respectively, and the PNP transistors 335, 340 are referred to as Q1 and Q2, respectively. To examine how the reference current, IREF, is set by the master bias current generator 215, consider the voltage loop equation arising from Kirchoff's Voltage Law (KVL) as follows:
V
GS(M2)+VEB(Q2)=VGS(M1)+VEB(Q1) (2)
In Equation (2), the emitter-base voltage of the PNP transistors 35, 340 and gate-source voltage of the NMOS transistors 320, 325 may be defined as follows:
where
VEB=Emitter-Base voltage of PNP Bipolar Transistor (Volt)
VT=Thermal Voltage=kT/q=0.0259 V at room Temperature (Volt)
IE=Emitter current flowing into PNP emitter (A)
JS=Emitter Current Density (A/m2)
M=Number of unit emitters in PNP
A=Area of one unit emitter in PNP (m2)
where
VGS=Gate-source voltage of NMOS Transistor (Volt)
VTH=Threshold voltage of the NMOS transistor (Volt)
ID=Drain (or Source) current of NMOS (A)
μN=Electron mobility in the channel of an NMOS transistor
COX=Gate oxide per unit area (F/m2)
W/L=Width/Length which is the aspect ratio of an MOS transistor
Expanding the KVL voltage loop equation (2) results in:
where VTH is the threshold voltage of the NMOS transistors 320, 325 (M1 and M2), and VT is the thermal voltage.
To find a closed form solution, Equation (5) may be solved for reference current, IREF:
where μN is the electron mobility, COX is oxide capacitance per unit area; and W/L is the width/length ratio of the NMOS transistors 320, 325.
The factors M and K are integer multiples of the NMOS aspect ratio and the PNP emitter area, respectively. In the illustrated embodiment, M is 8 and K is 2; however both may vary depending on the particular implantation. For instance, M may be between 4 and 100. Generally, a larger value for M increases the accuracy of IREF at the expense of increased chip real estate area. The values of M and K determine the amount of reference current. A larger current provides enhanced matching, but requires higher power consumption.
Both the M and K ratios may be defined precisely and their variations are typically very small in any semiconductor process. Also, in typical CMOS analog processes, the tolerance variation on oxide thickness COX, mobility μN, channel width W, and channel length L are usually well-controlled. Hence, the variability of the parameters in Equation (6) that define the value of the reference current is significantly less than the variability in the resistance parameter that defines the reference current in Equation (1) for the prior art circuit 100 of
Turning now to
The master bias current generator circuits 215, 400 described herein exhibit increased performance and reduced variability relative to the prior art circuit 100 of
One aspect of the present invention is seen in a master bias current generating circuit including a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size parameter coupled to the current source and a first diode having a second size parameter coupled to the first transistor. The second reference leg includes a second transistor having a third size parameter less than the first size parameter coupled to the current source and a second diode having a fourth size parameter greater than the second size parameter coupled to the second transistor.
Another aspect of the present invention is seen where the first reference leg includes a first field effect transistor having a first aspect ratio coupled to the current source and a first diode-connected bipolar transistor having a first emitter area coupled to the first field effect transistor. The second reference leg includes a second field effect transistor having a second aspect ratio less than the first aspect ratio coupled to the current source and a second diode-connected bipolar transistor having a second emitter area greater than the first emitter area coupled to the second field effect transistor.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.