Master latch circuit with signal level displacement for a dynamic flip flop
The invention relates to a master latch circuit with signal level displacement for a dynamic flip flop which has a minimal signal switching delay.
U.S. Pat. No. 6,507,228 B2 describes a clock edge triggered latch circuit suitable for a high-frequency clock signal. The latch circuit contains a signal delay circuit, which delays the clock signal present by a specific time. A circuit node connected downstream is charged depending on a data signal present during a time window that is adjustable by means of the delay time.
In digital systems, the computing power is limited on account of the heating of the digital system as a result of the power loss that occurs. Furthermore, the power loss of the components limits the operating duration particularly in the case of mobile digital systems.
It has been proposed, therefore, to use a plurality of operating voltages within a digital logic block, a high operating voltage being made available for the components in the case of the critical signal paths, while the components are supplied with a low supply voltage in the case of the noncritical signal paths. The dynamic losses, in particular, which depend quadratically on the operating voltage, are reduced as a result of the low supply voltage. However, the use of a plurality of operating voltages gives rise to the problem area that there are signal transitions between different voltage domains on account of the logical structure of the circuit. What is critical in this case is, in particular, the signal transition from a region with a low supply voltage to a region with a high supply voltage.
Therefore, in order to avoid the shunt currents, use is made of a signal level displacement circuit according to the prior art such as is illustrated in
The signal level displacement circuit as illustrated in
However, the signal level displacement circuit according to the prior art such as is illustrated in
A further disadvantage consists in the fact that the signal level displacement circuit of
A further disadvantage consists in the fact that the signal level displacement circuit in accordance with
In order to minimize the disadvantages mentioned, it is proposed, therefore, to integrate the signal level displacement function into an edge triggered flip flop.
In order to avoid the disadvantages associated with a conventional signal level displacement circuit such as is illustrated in
By virtue of the integration of the signal level displacement into the conventional static flip flop, as illustrated in
Since the flip flop with signal displacement according to the prior art as illustrated in
Therefore, the object of the present invention is to provide a master latch circuit with signal level displacement for a dynamic flip flop which has a minimal signal delay.
This object is achieved according to the invention by means of a master latch circuit having the features specified in patent claim 1.
The invention provides a master latch circuit with signal level displacement for a flip flop which is clocked by a clock signal (Clk), the master latch circuit having:
a signal delay circuit, which delays and inverts the clock signal (Clk) present with a specific time delay (ΔT); and
a circuit node which, in a charging phase, in which the clock signal (Clk) present is logically low, is charged to an operating voltage (VB) and which, in an evaluation phase, if the clock signal (Clk) present and the delayed inverted clock signal (ClkDELAY) are logically high, can be discharged depending on a data signal (D) present.
The input signal from the low voltage domain Va drives only transistors of one type in this case (either only P-channel or only N-channel).
The master latch circuit with signal level displacement for a dynamic flip flop according to the invention has the advantage that the dynamic flip flop only has to be supplied with one operating voltage.
As a result of this, the components of the dynamic flip flop can be arranged at a very small distance from one another on the chip. This has the effect that the master latch circuit according to the invention or the dynamic flip flop can be integrated with a minimal area requirement on the chip.
Moreover, signal propagation times within the master latch circuit according to the invention or the dynamic flip flop according to the invention are minimized on account of the components being spaced apart minimally.
A further advantage of the master latch circuit according to the invention consists in the fact that a minimal number of circuitry components are integrated therein, so that the power loss of the master latch circuit according to the invention is likewise minimized.
In one preferred embodiment of the master latch circuit according to the invention, the circuit node (LDN) is discharged in the evaluation phase if the data signal (D) present is logically high, and the circuit node (LDN) is not discharged in the evaluation phase if the data signal (D) present is logically low.
In one preferred embodiment, the circuit node (LDN) is connected to a reference potential (GND) via a capacitance (C).
In a first embodiment, said capacitance (C) is a parasitic capacitance.
In an alternative embodiment, the capacitance (C) is formed by a capacitor provided.
In one preferred embodiment of the master latch circuit according to the invention, the circuit node (LND) is connected to an input of a first isolating circuit clocked by the clock signal (Clk).
The first isolating circuit preferably has an output connected to a slave latch circuit, which buffer-stores the output signal of the master latch circuit.
An inverter is preferably connected downstream of the slave latch circuit.
In one preferred embodiment, the output of the first isolating circuit is fed back to the input of the first isolating circuit via a second clocked isolating circuit, the second isolating circuit being clocked with the delayed clock signal (ClkDELAY).
The provision of the second clocked isolating circuit has the advantage that, after the evaluation phase, the charge at the circuit node (LDN) is held actively at a specific signal level by means of the feedback.
A decrease in the signal level at the circuit node (LDN) for example on account of leakage currents or noise can thereby be prevented.
In a further embodiment of the master latch circuit according to the invention, the master latch circuit has a first controllable switch, which is driven by the inverted clock signal ({overscore (Clk)}) and which switches the operating voltage (VB) present to the circuit node (LDN) if the clock signal (Clk) is logically low.
The first controllable switch is preferably a PMOS transistor.
In one preferred embodiment of the master latch circuit according to the invention, the master latch circuit has a second controllable switch, a third controllable switch, and a fourth controllable switch, which are connected in series with one another between the circuit node (LDN) and the reference potential (GND).
In this case, the second controllable switch is preferably driven by the delayed inverted clock signal ({overscore (CLKDELAY)})
The third controllable switch is preferably driven by the data signal (D) present.
The fourth controllable switch is preferably driven by the clock signal (Clk).
The second, third and fourth controllable switches are preferably NMOS transistors.
The second, third and fourth controllable switches are preferably connected in parallel with the capacitance.
In one particularly preferred embodiment of the master latch circuit according to the invention, the time delay (ΔT) of the signal delay circuit is adjustable.
In this case, the time constant (τ) with which the capacitance (C) is discharged via the series-connected switches during the evaluation phase if the data signal (D) present is logically high is less than the time delay (ΔT) of the signal delay circuit (τ<<ΔT).
The time delay (ΔT) of the signal delay circuit is preferably substantially less than the time period of the clock signal (Clk) (ΔT<<Tclk).
In one preferred embodiment, the signal delay circuit is formed by a plurality of inverter stages connected in series.
The invention furthermore provides an edge triggered flip flop with a master latch circuit according to claim 1, with a slave latch circuit for buffer-storing the output signal of the master latch circuit and with a clocked isolating circuit for isolating the master latch circuit from the slave latch circuit.
The invention provides a dynamic flip flop with signal level displacement, which has:
a master latch circuit having a signal delay circuit, which delays and inverts the clock signal present with a specific time delay (ΔT);
a circuit node which, in a charging phase, in which the clock signal (Clk) present is logically low, is charged to an operating voltage and which, in an evaluation phase, if the clock signal (Clk) present and the delayed inverted clock signal (ClkDELAY) are logically high, can be discharged depending on a data signal (D) present; a slave latch circuit for buffer-storing the output signal of the master latch circuit; and having a clocked isolating circuit for isolating the master latch circuit from the slave latch circuit.
In this case, the input signal D drives only transistors of a single type (either only N-channel or only P-channel).
Preferred embodiments of the master latch circuit with signal level displacement for a dynamic flip flop according to the invention are described below with reference to the accompanying figures for elucidating features that are essential to the invention.
In the figures:
The master latch circuit 10 comprises a signal delay circuit 13, which delays and inverts the clock signal Clk present at the clock signal input with a specific time delay ΔT. In this case, the signal delay circuit 13 preferably comprises a series of series-connected inverter stages 13a, which brings about a specific time delay ΔT, and an inverter 13 being connected downstream. The master latch circuit 10 contains a dynamic circuit node 14 which, in a charging phase, if the clock signal (Clk) present is logically low, is charged to an operating voltage VB present at the terminal 7 and which, in an evaluation phase, if the clock signal (Clk) present and the delayed inverted clock signal that is output by the signal delay circuit 13 are logically high, can be discharged depending on the data signal (D) present at the terminal 3. The circuit node 14 is discharged in the evaluation phase if the data signal (D) present is logically high, and conversely the circuit node 14 is not discharged during the evaluation phase if the data signal (D) present is logically low.
In an alternative embodiment, the master latch circuit 10 may be constructed complementarily with respect to the circuit illustrated in
The circuit node 14 is connected to a reference potential via a capacitance 15. The reference potential is preferably ground (GND). In a first embodiment of the master latch circuit 10 according to the invention, the capacitance 15 is formed by a parasitic capacitance C.
In an alternative embodiment, the capacitance C is formed by at least one capacitor provided.
As an alternative, the capacitance C may be formed by a programmable capacitor network, which permits programming of the time constant T for the charging and discharging of the circuit node 14.
The circuit node 14 is connected via a line 16 to an input of the first isolating circuit 12, which is clocked by the clock signal Clk for driving the transmission gate contained therein. The output of the first isolating circuit 12 is connected via a line 17 to an input of the slave latch circuit 11, which buffer-stores the output signal QM of the master latch circuit 10. An inverter 18 is preferably connected downstream of the slave latch circuit 11, which inverter inverts the output signal QS of the slave latch circuit 11 and outputs the output signal Q of the dynamic flip flop 1 at the output 5 of the flip flop 1.
The master latch circuit 10 has a first controllable switch 19, which is driven by the inverted clock signal ({overscore (Clk)}). The clock signal input 2 of the flip flop 1 is connected via a line 20 to an inverter 21 for inverting the clock signal Clk. However, the inverter may be omitted if a corresponding type of transistor (here P-channel) is used for the switch 19. The output of the inverter 21 is connected to the control input of the switch 19 via a line 22. The controllable switch 19 is preferably a PMOS transistor. If the clock signal Clk is logically low, the PMOS transistor 19 turns on and connects the operating voltage terminal 7 to the dynamic node 14, so that the latter is charged to the operating voltage VB during the charging phase.
The signal delay circuit 13 is connected, on the output side, via a line 23 to a second controllable switch 24, which is preferably an NMOS transistor.
The data signal D present at the data signal input 3 is applied via a line 25 directly to the control input of a further controllable switch 26, which is likewise preferably an NMOS transistor. The clock signal Clk present at the clock signal input 2 controls a third controllable switch 28, which is preferably likewise implemented as an NMOS transistor, via an internal line 27. The NMOS transistors 24, 26, 28 are connected in series with one another. In this case, they are connected up in series between the dynamic circuit node 14 and the reference potential GND.
The series circuit of the three NMOS transistors 24, 26, 28 is connected up in parallel with the capacitance 15 present.
In the charging phase, the capacitance 15 is via the PMOS transistor 19 with a specific time constant τcharging resulting from the product of the capacitance of the capacitor 15 and the switch-over resistance Rs1 of the PMOS transistor:
τcharging=R19·C15 (1)
In the evaluation phase, the dynamic circuit node 14, in a specific time window if the clock signal Clk present and the delayed inverted clock signal ({overscore (ClkDELAY)}) are logically high, depending on the data signal D present, is discharged if the data signal D is logically high and is not discharged if the data signal D is logically low. The time window is determined by the time delay ΔT of the signal delay circuit 13. In this case, the delay time AT is preferably adjustable.
The discharging of the dynamic node 14 for the case where the data signal present is logically high within the time window is effected with a discharge time constant τdischarge determined by the product of the on resistances of the series-connected NMOS transistors 24, 26, 28 and the capacitance of the capacitor 15:
τdischarge=(R24+R26+R28)·C15 (2)
The signal delay time ΔT of the signal delay circuit 13 is chosen such that it is considerably greater than the discharge time constant τdischarge
ΔT>>τdischarge (3)
Furthermore, it must be ensured that the signal delay time ΔT of the signal delay circuit 13 is considerably less than the clock period Tclk of the clock signal Clk present.
ΔT<<<TClk (4)
The data signal QM present at the dynamic circuit node 14 is buffer-stored in the slave latch circuit 11 connected downstream. The slave latch circuit 11 contains an inverter 11a, the output of which is fed back via an isolating circuit 11b via the input of the inverter 11a. The isolating circuit 11b contains an inverter with an integrated transmission gate which is driven by the inverted clock signal {overscore (Clk)}.
a-12f show signal sequences for elucidating the functioning of the flip flop 1 according to the invention with integrated signal level displacement.
a shows the signal profile at the clock signal input 2 of the dynamic flip flop 1.
b shows the clock signal {overscore (Clk)} inverted at the inverter.
c shows the inverted clock signal {overscore (ClkDELAY)} that is signal-delayed by the signal delay circuit 13 and drives the NMOS transistor 24.
d shows by way of example a data signal D present at the data signal input 3.
e shows the associated signal profile at the dynamic circuit node LDN (Logic Decision Node).
f shows the signal profile at the signal output 5 of the dynamic flip flop 1 according to the invention.
At the instant t1, the clock signal Clk has a rising signal edge, so that the NMOS transistor 28 turns on. The NMOS transistor 24 is also still turned on within a time window determined by the signal delay time AT of the signal delay circuit 13.
During the time window ΔT, the data signal D is logically high, so that the NMOS transistor 26 concurrently connected in series is also turned on. The logic decision mode (LDN) 14 is discharged via the series-connected NMOS transistors 24, 26, 28 with the discharge time constant τdischarge. It can be seen in
At the instant t2, the clock signal Clk has a falling signal edge, so that the NMOS transistor 28 is turned off. At the same time, the PMOS transistor 19 turns on, so that the dynamic circuit node 14 is charged to the operating voltage VB with a charging time constant τcharging. The circuit node 14 remains charged until the next time window at the instant t3. At the instant t3, a time window is opened again in order to close the two NMOS transistors 24, 28. In the example illustrated, the data signal D is logically low at this instant, so that the NMOS transistor 26 remains open and, consequently, the capacitor 15 is not discharged. At the instant t5, a time window AT is opened again, the circuit node 14 being correspondingly discharged on account of the logically high data signal D.
As can be discerned from
A further advantage of the first embodiment of the flip flop 1 according to the invention or the master latch circuit 10 according to the invention as illustrated in
In an alternative embodiment of the master latch circuit 10, the controllable switch 24 is a PMOS transistor and the controllable switches 26, 28 are formed by NMOS transistors. The advantage of this embodiment consists in the fact that an inversion of the delayed clock signal ClkDELAY is not necessary, so that the inverter 13b is omitted.
The dynamic flip flop 1 according to the invention generally carries out a signal level boosting of the data signal present.
As an alternative, the flip flop according to the invention may also bring about a signal level lowering of the data signal present for data systems connected downstream. The logic decision node 14 stores the supplied data information during half a clock phase TClk/2. As a result of this, the dynamic flip flop 1 according to the invention becomes particularly fast and takes up only a small area in this case.
In the case of the embodiment illustrated in
The dynamic flip flops 1 according to the invention such as have been illustrated in
The dynamic flip flop 1 according to the invention makes it possible also for time-noncritical signal paths whose signal propagation time is only insignificantly below the signal propagation time of the critical signal path likewise to be provided with a flip flop 1 according to the invention for signal level boosting since the flip flop 1 according to the invention has only a very low signal propagation time and thus increases the signal propagation time of the noncritical signal path only very slightly, so that it still lies below the total signal propagation time of the critical signal path. One advantage of the dynamic flip flop 1 according to the invention for signal level boosting therefore consists in the fact that the number of noncritical signal paths which can be supplied with a low supply voltage VA can be considerably increased.
The dynamic flip flop 1 according to the invention functions for a wide range of input voltages and thereby differs from conventional signal level displacement circuits, which often only permit a narrow voltage range.
The dynamic flip flop 1 according to the invention is distinguished by a low signal delay, a small chip area requirement and a very low power loss.
Number | Date | Country | Kind |
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103 43 565.4 | Sep 2003 | DE | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/EP04/09853 | 9/3/2004 | WO | 7/17/2006 |