Claims
- 1. A communications system comprising:
one or more communication buses implemented on a backplane having one or more interface slots; one or more controller cards communicating with the communication buses through said one or more interface slots, each controller card comprising:
a controller; and at least two independent communication channels provided for connecting a host with said one or more communication buses, wherein the controller determines and designates the status of said one or more controller cards such that a first controller card is designated to have primary status if the first controller card is inserted in a first interface slot while remaining interface slots are empty.
- 2. The communication system of claim 1, wherein the controller further determines and designates the status of one or more controller cards inserted in said one or more slots such that the first controller card in said first slot retains primary status while one or more controller cards are added or removed from said remaining slots.
- 3. The communication system of claim 2, wherein the controller further determines and designates the status of one or more controller cards inserted in said one or more slots such that a second controller card having a non-primary status inserted in a second interface slot assumes primary status after a power interruption, if the second interface slot is designated as the slot to assume primary status after a power interruption.
- 4. The communication system of claim 3, wherein the controller further determines and designates the status of one or more controller cards inserted in said one or more slots such that a second controller card having a non-primary status inserted in a second interface slot assumes primary status if the first controller card is removed from the first interface slot.
- 5. The communication system of claim 4, wherein the controller included in the first controller card comprises:
a primary card identifier for detecting the presence of the second controller card in the second interface slot; and a tristate buffer for assigning or maintaining primary status of the first controller card.
- 6. The communication system of claim 5, wherein the primary card identifier determines the presence of the second controller in the second interface slot based on one or more signals driven through the backplane.
- 7. The communication system of claim 6, wherein the signals driven through the backplane are changed by insertion of the second controller in the second interface slot.
- 8. The communication system of claim 7, wherein the signals are driven high by the backplane before the insertion of the second controller in the second interface slot.
- 9. The communication system of claim 8, wherein the signals are grounded and driven low after the insertions of the second controller in the second interface slot.
- 10. The communication system of claim 5, wherein the primary card identifier after detecting the presence of the second controller card in the second interface slot activates the tristate buffer.
- 11. The communication system of claim 10, wherein the tristate buffer if activated generates a primary signal forwarded to the second interface slot indicating that an interface slot includes a controller card with primary status.
- 12. The communication system of claim 11, wherein the primary signal generated by the tristate buffer drives a primary input signal to the primary card identifier, the primary input signal for detecting a change in the primary status.
- 13. The communication system of claim 12, wherein a change in the value of the primary input signal indicates the removal of a controller card from an interface slot.
- 14. The communication system of claim 13, wherein when the tristate buffer is activated then the primary input signal is driven low.
- 15. The communication system of claim 14, wherein when the second controller card is removed from the second interface slot, the primary card identifier detects that the second interface slot is empty and deactivates the tristate buffer.
- 16. The communication system of claim 15, wherein the primary input signal is driven high by the backplane when the second controller card is removed from the second interface slot.
- 17. The communication system of claim 16, wherein when primary input signal is driven from low to high, the primary card identifier determines that the first controller card is the only card in the system and causes the first controller card to assume primary status.
- 18. The communication system of claim 17, wherein no signals are generated by the tristate buffer when the tristate buffer is inactive.
- 19. A communications system with a plurality of interface slots, said system including control logic that determines and designates the status of one or more controller cards inserted in said one or more slots such that:
a first controller card is designated to have primary status if the first controller card is inserted in a first interface slot while the other interface slots are empty; the first controller card in said first slot retains primary status while one or more controller cards are added or removed from said remaining slots; and a second controller card having non-primary status inserted in a second interface slot assumes primary status after a power interruption, if the second interface slot is designated as the slot to assume primary status after a power interruption.
- 20. The communication system of claim 19, wherein the control logic determines and designates the status of one or more controller cards inserted in said one or more slots such that the second controller card having non-primary status inserted in a second interface slot assumes primary status if the first controller card is removed from the first interface slot.
CROSS-REFERENCES
[0001] The present invention is related to subject matter disclosed in the following co-pending patent applications, the contents of which are incorporated by reference herein in their entirety:
[0002] 1. U.S. patent application entitled, “Redundant, High-Availability Storage System” (HP Docket No. 10003435- 1), naming Anthony J. Benson and James J. deBlanc as inventors and filed on even date within.
[0003] 2. U.S. patent application entitled, “System and Method for Data Corruption Avoidance” (HP Docket No. 10003436-1), naming Anthony J.
[0004] Benson and Patrick McGoey as inventors and filed on even date within.
[0005] 3. U.S. patent application entitled, “Multiple-Path Interface Card for Interfacing Multiple Isolated Interfaces to a Storage System” (HP Docket No. 10003437-1), naming Anthony J. Benson and James J. deBlanc as inventors and filed on even date within.
[0006] 4. U.S. patent application entitled, “DIP Switch Configuration for Increased Usability with Multiple Cards” (HP Docket No.10003438-1), naming Anthony J. Benson, Chadi Theodossy, and Joanna Baisden as inventors and filed on even date within.
[0007] 5. U.S. patent application entitled, “Circuit for Switching One or More HVD Transceivers” (HP Docket No. 10003439-1), naming Anthony J. Benson as inventor and filed on even date within.
[0008] 6. U.S. patent application entitled, “Management of Communication Bus Resets” (HP Docket No. 10005621-1), naming Anthony J. Benson, James L. White and Dovard K. Howard as inventors and filed on even date within.
[0009] 7. U.S. patent application entitled, “Management of Resets For Interdependent Dual Small Computer Standard Interface (SCSI) Bus Controllers” (HP Docket No. 10992797-1, PTO Ser. No.: 09/605,161), Anthony J. Benson, et al., filed on Jun. 27, 2000.