Claims
- 1. A match circuit for implementation in a general purpose performance counter (“GPPC”) connected to a bus carrying debug data, the match circuit comprising logic for activating a match signal when a selected N-bit portion of the debug data matches an N-bit threshold for all bits selected by an N-bit match mask (“mmask”).
- 2. The match circuit of claim 1 wherein N is equal to sixteen.
- 3. The match circuit of claim 1 wherein the N-bit threshold is provided from a control status register (“CSR”).
- 4. The match circuit of claim 1 wherein the N-bit mmask is provided from a control status register (“CSR”).
- 5. The match circuit of claim 1 wherein the debug data comprises 80 bits.
- 6. The match circuit of claim 5 wherein the debug data comprises eight 16-bit portions aligned on 10-bit blocks.
- 7. The match circuit of claim 6 wherein the selected portion comprises one of the eight 16-bit portions.
- 8. The match circuit of claim 1 wherein the logic for activating a match signal comprises logic for comparing a binary bit of the selected debug data portion with a corresponding bit of the threshold and outputting a binary bit indicative of whether the compared bits match.
- 9. Circuitry for implementation in a general purpose performance counter (“GPPC”) connected to a bus carrying debug data, the circuitry for analyzing a selected portion of the debug data, comprising:
logic means for activating a match signal when the selected portion of the debug data includes a specified bit pattern; logic means for activating a threshold signal based on a comparison between at least a subset of the selected debug data portion and a threshold value; and logic means for outputting one of the match signal and the threshold signal in response to a selection control signal.
- 10. The circuitry of claim 9 wherein the logic means for activating a match signal further comprises:
an exclusive NOR (“XNOR”) circuit operating to perform a bit-wise XNOR operation between the selected debug data portion and a threshold register that is as wide as the selected debug data portion; an OR circuit for ORing an inverted mask (“mmask”) with the output of the XNOR circuit; and an AND circuit operating to AND the OR circuit's output to generate the match signal.
- 11. The circuitry of claim 10 wherein the mmask is provided from a control status register (“CSR”).
- 12. The circuitry of claim 10 wherein the threshold register is provided as a control status register (“CSR”).
- 13. The circuitry of claim 10 wherein the debug data comprises 80 bits.
- 14. The circuitry of claim 10 wherein the debug data comprises eight 16-bit portions aligned on 10-bit blocks.
- 15. The circuitry of claim 14 wherein the selected portion comprises one of the eight 16-bit portions.
- 16. The circuitry of claim 9 wherein the logic means for activating a threshold signal comprises a compare circuit that outputs a logic one when the subset of the selected debug data portion is greater than or equal to the threshold value.
- 17. The circuitry of claim 9 wherein the logic means for outputting one of the match signal and the threshold signal comprises a 2:1 multiplexer circuit.
- 18. A method operable in a general purpose performance counter (“GPPC”) connected to a bus carrying debug data for of analyzing a selected portion of the debug data, the method comprising:
activating a match signal when the selected portion of the debug data includes a specified bit pattern; activating a threshold signal based on a comparison between at least a subset of the selected debug data portion and a threshold value; and outputting one of the match signal and the threshold signal in response to a selection control signal.
- 19. The method of claim 18 wherein the activating of a match signal comprises:
performing a bit-wise exclusive NOR operation between the selected debug data portion and a threshold register that is as wide as the selected debug data portion to create a first intermediary output; performing an OR operation between the first intermediary output and an inverted mask (“mmask”) to create a second intermediary output; and performing an AND operation on the second intermediary output to generate the match signal.
- 20. The method of claim 19 wherein the mmask is provided from a control status register (“CSR”).
- 21. The method of claim 19 wherein the threshold value is provided from a control status register (“CSR”) operating as the threshold register.
- 22. The method of claim 19 wherein the selected portion of the debug data comprises 16 bits.
- 23. The method of claim 19 wherein the debug data comprises eight 16-bit portions aligned on 10-bit blocks.
- 24. The method of claim 23 wherein the selected portion comprises one of the eight 16-bit portions.
- 25. The method of claim 18 wherein the activating of a threshold signal comprises outputting a logic one when the subset of the selected debug data portion is greater than or equal to the threshold value.
PRIORITY UNDER 35 U.S.C. §119(e) & 37 C.F.R. §1.78
[0001] This nonprovisional application claims priority based upon the following prior United States provisional patent application entitled: “General Purpose Counters for Performance, Debug and Coverage,” Application No.: 60/469,180, filed May 9, 2003, in the name(s) of Richard W. Adkisson and Tyler J. Johnson, which is hereby incorporated by reference.
[0002] This application is related to U.S. patent application Ser, No. ______, filed ______ entitled COVERAGE CIRCUIT FOR PERFORMANCE COUNTER (Docket No. 200208996-1); U.S. patent application Ser. No. ______, filed ______ entitled COVERAGE DECODER CIRCUIT FOR PERFORMANCE COUNTER (Docket No. 200208997-1); U.S. patent application Ser. No. ______, filed ______ entitled DATA SELECTION CIRCUIT FOR PERFORMANCE COUNTER (Docket No. 200209000-1); U.S. patent application Ser. No. ______, filed ______ entitled ZEROING CIRCUIT FOR PERFORMANCE COUNTER (Docket No. 200209001-1); U.S. patent application Ser. No. ______, filed ______ entitled GENERAL PURPOSE PERFORMANCE COUNTER (Docket No. 200208999-2); and U.S. patent application Ser. No. ______, filed entitled INCREMENT/DECREMENT CIRCUIT FOR PERFORMANCE COUNTER (Docket No. 200208998-1), all of which are hereby incorporated by reference in their entirety.
[0003] Related subject matter disclosed in the following commonly owned co-pending U.S. patent applications: (i) A BUS INTERFACE MODULE, filed Mar. 28, 2003; application Ser. No. 10/402,092; and (ii) AN INTEGRATED CIRCUIT, filed Mar. 28, 2003; application Ser. No. 10/402,034, is hereby incorporated by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60469180 |
May 2003 |
US |