Materials for forming a nucleation-inhibiting coating and devices incorporating same

Abstract

An opto-electronic device includes a nucleating inhibiting coating (NIC) disposed on a first layer surface of the device in a first portion of a lateral aspect thereof; and a conductive coating disposed on a second layer surface of the device in a second portion of the lateral aspect thereof; wherein an initial sticking probability for forming the conductive coating onto a surface of the NIC in the first portion, is substantially less than the initial sticking probability for forming the conductive coating onto the surface in the second portion, such that the surface of the NIC in the first portion is substantially devoid of the conductive coating.

Description

RELATED APPLICATIONS

The present application is a 371 National Stage Entry of International Application No. PCT/US2020/054359, filed May 7, 2020, which in turn claims the benefit of priority to U.S. Provisional Patent Application No. 62/845,273, filed May 8, 2019, and U.S. Provisional Patent Application 62/886,896, filed Aug. 14, 2019, the contents of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present disclosure relates to opto-electronic devices and in particular to an opto-electronic device having first and second electrodes separated by a semiconductor layer and having a conductive coating deposited thereon patterned using a nucleation-inhibiting coating (NIC).

BACKGROUND

In an opto-electronic device such as an organic light emitting diode (OLED), at least one semiconducting layer is disposed between a pair of electrodes, such as an anode and a cathode. The anode and cathode are electrically coupled to a power source and respectively generate holes and electrons that migrate toward each other through the at least one semiconducting layer. When a pair of holes and electrons combine, a photon may be emitted.

OLED display panels may comprise a plurality of (sub-)pixels, each of which has an associated pair of electrodes. Various layers and coatings of such panels are typically formed by vacuum-based deposition techniques.

In some applications, it may be desirable to provide a conductive coating in a pattern for each (sub-)pixel of the panel across either or both of a lateral and a cross-sectional aspect thereof, by selective deposition of the conductive coating to form a device feature, such as, without limitation, an electrode and/or a conductive element electrically coupled thereto, during the OLED manufacturing process.

One method for doing so, in some non-limiting applications, involves the interposition of a fine metal mask (FMM) during deposition of an electrode material and/or a conductive element electrically coupled thereto. However, materials typically used as electrodes have relatively high evaporation temperatures, which impacts the ability to re-use the FMM and/or the accuracy of the pattern that may be achieved, with attendant increases in cost, effort and complexity.

One method for doing so, in some non-limiting examples, involves depositing the electrode material and thereafter removing, including by a laser drilling process, unwanted regions thereof to form the pattern. However, the removal process often involves the creation and/or presence of debris, which may affect the yield of the manufacturing process.

Further, such methods may not be suitable for use in some applications and/or with some devices with certain topographical features.

It would be beneficial to provide an improved mechanism for providing selective deposition of a conductive coating.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples of the present disclosure will now be described by reference to the following FIGURES, in which identical reference numerals in different FIGURES indicate identical and/or in some non-limiting examples, analogous and/or corresponding elements and in which:

FIG. 1 is a block diagram from a cross-sectional aspect, of an example electro-luminescent device according to an example in the present disclosure;

FIG. 2 is a cross-sectional view of an example backplane layer of the substrate of the device of FIG. 1, showing a thin film transistor (TFT) embodied therein;

FIG. 3 is a circuit diagram for an example circuit such as may be provided by one or more of the TFTs shown in the backplane layer of FIG. 2;

FIG. 4 is a cross-sectional view of the device of FIG. 1;

FIG. 5 is a cross-sectional view of an example version of the device of FIG. 1, showing at least one example pixel definition layer (PDL) supporting deposition of at least one second electrode of the device;

FIG. 6 is an example energy profile illustrating relative energy states of an adatom absorbed onto a surface according to an example in the present disclosure;

FIG. 7 is a schematic diagram showing an example process for depositing a selective coating in a pattern on an exposed layer surface of an underlying material in an example version of the device of FIG. 1, according to an example in the present disclosure;

FIG. 8 is a schematic diagram showing an example process for depositing a conductive coating in the first pattern on an exposed layer surface that comprises the deposited pattern of the selective coating of FIG. 7 where the selective coating is a nucleation-inhibiting coating (NIC);

FIGS. 9A-D are a schematic diagrams showing example open masks, suitable for use with the process of FIG. 7, having an aperture therewithin according to an example in the present disclosure;

FIG. 10 is an example version of the device of FIG. 1, with additional example deposition steps according to an example in the present disclosure;

FIG. 11A is a schematic diagram showing an example process for depositing a selective coating that is a nucleation-promoting coating (NPC) in a pattern on an exposed layer surface that comprises the deposited pattern of the selective coating of FIG. 9;

FIG. 11B is a schematic diagram showing an example process for depositing a conductive coating in a pattern on an exposed layer surface that comprises the deposited pattern of the NPC of FIG. 11A;

FIG. 12A is a schematic diagram showing an example process for depositing an NPC in a pattern on an exposed layer surface of an underlying material in an example version of the device of FIG. 1, according to an example in the present disclosure;

FIG. 12B is a schematic diagram showing an example process of depositing an NIC in a pattern on an exposed layer surface that comprises the deposited pattern of the NPC of FIG. 12A;

FIG. 12C is a schematic diagram showing an example process for depositing a conductive coating in a pattern on an exposed layer surface that comprises the deposited pattern of the NIC of FIG. 12B;

FIGS. 13A-13C are schematic diagrams that show example stages of an example printing process for depositing a selective coating in a pattern on an exposed layer surface in an example version of the device of FIG. 1, according to an example in the present disclosure;

FIG. 14 is a schematic diagram illustrating, in plan view, an example patterned electrode suitable for use in a version of the device of FIG. 1, according to an example in the present disclosure;

FIG. 15 is a schematic diagram illustrating an example cross-sectional view of the device of FIG. 14 taken along line 15-15;

FIG. 16A is a schematic diagram illustrating, in plan view, a plurality of example patterns of electrodes suitable for use in an example version of the device of FIG. 1, according to an example in the present disclosure;

FIG. 16B is a schematic diagram illustrating an example cross-sectional view, at an intermediate stage, of the device of FIG. 16A taken along line 16B-16B;

FIG. 16C is a schematic diagram illustrating an example cross-sectional view of the device of FIG. 16A taken along line 16C-16C;

FIG. 17 is a schematic diagram illustrating a cross-sectional view of an example version of the device of FIG. 1, having an example patterned auxiliary electrode according to an example in the present disclosure;

FIG. 18A is a schematic diagram illustrating, in plan view, an example arrangement of emissive region(s) and/or non-emissive region(s) in an example version of the device of FIG. 1, according to an example in the present disclosure;

FIGS. 18B-18D are schematic diagrams each illustrating a segment of a part of FIG. 18A, showing an example auxiliary electrode overlaying a non-emissive region according to an example in the present disclosure;

FIG. 19 is a schematic diagram illustrating, in plan view an example pattern of an auxiliary electrode overlaying at least one emissive region and at least one non-emissive region according to an example in the present disclosure;

FIG. 20A is a schematic diagram illustrating, in plan view, an example pattern of an example version of the device of FIG. 1, having a plurality of groups of emissive regions in a diamond configuration according to an example in the present disclosure;

FIG. 20B is a schematic diagram illustrating an example cross-sectional view of the device of FIG. 20A taken along line 20B-20B;

FIG. 20C is a schematic diagram illustrating an, example cross-sectional view of the device of FIG. 20A taken along line 20C-20C;

FIG. 21 is a schematic diagram illustrating an example cross-sectional view of an example version of the device of FIG. 4 with additional example deposition steps according to an example in the present disclosure;

FIG. 22 is a schematic diagram illustrating an example cross-sectional view of an example version of the device of FIG. 4 with additional example deposition steps according to an example in the present disclosure;

FIG. 23 is a schematic diagram illustrating an example cross-sectional view of an example version of the device of FIG. 4 with additional example deposition steps according to an example in the present disclosure;

FIG. 24 is a schematic diagram illustrating an example cross-sectional view of an example version of the device of FIG. 4 with additional example deposition steps according to an example in the present disclosure;

FIGS. 25A-25C are schematic diagrams that show example stages of an example process for depositing a conductive coating in a pattern on an exposed layer surface of an example version of the device of FIG. 1, by selective deposition and subsequent removal process, according to an example in the present disclosure;

FIG. 26A is a schematic diagram illustrating, in plan view, an example of a transparent version of the device of FIG. 1 comprising at least one example pixel region and at least one example light-transmissive region, with at least one auxiliary electrode according to an example in the present disclosure;

FIG. 26B is a schematic diagram illustrating an example cross-sectional view of the device of FIG. 26A taken along line 26B-26B;

FIG. 27A is a schematic diagram illustrating, in plan view, an example of a transparent version of the device of FIG. 1 comprising at least one example pixel region and at least one example light-transmissive region according to an example in the present disclosure;

FIGS. 27B and 27C are schematic diagrams illustrating an example cross-sectional view of the device of FIG. 27A taken along line 27B-27B;

FIGS. 28A-28D are schematic diagrams that show example stages of an example process for manufacturing an example version of the device of FIG. 1 to provide emissive region having a second electrode of different thickness according to an example in the present disclosure;

FIGS. 29A-29D are schematic diagrams that show example stages of an example process for manufacturing an example version of the device of FIG. 1 having sub-pixel regions having a second electrode of different thickness according to an example in the present disclosure;

FIG. 30 is a schematic diagram illustrating an example cross-sectional view of an example version of the device of FIG. 1 in which a second electrode is coupled to an auxiliary electrode according to an example in the present disclosure;

FIGS. 31A-31I are schematic diagrams that show various potential behaviours of an NIC at a deposition interface with a conductive coating in an example version of the device of FIG. 1, according to various examples in the present disclosure;

FIG. 32 is a schematic diagram illustrating an example cross-sectional view of an example version of the device of FIG. 1 having a partition and a sheltered region, such as a recess, in a non-emissive region thereof according to an example in the present disclosure;

FIG. 33A is a schematic diagram that shows an example cross-sectional view of an example version of the device of FIG. 1 having a partition and a sheltered region, such as a recess, in a non-emissive region prior to deposition of a semiconducting layer thereon, according to an example in the present disclosure;

FIGS. 33B-33P are schematic diagrams that show various examples of interactions between the partition of FIG. 33A after deposition of a semiconducting layer, a second electrode and an NIC with a conductive coating deposited thereon, according to various examples in the present disclosure;

FIGS. 34A-34G are schematic diagrams that show various examples of an auxiliary electrode within the device of FIG. 33A, according to various examples in the present disclosure;

FIGS. 35A-35B are schematic diagrams that show example cross-sectional views of an example version of the device of FIG. 1 having a partition and a sheltered region, such as an aperture, in a non-emissive region, according to various examples in the present disclosure; and

FIG. 36 is a schematic diagram illustrating the formation of a film nucleus according to an example in the present disclosure.

In the present disclosure, for purposes of explanation and not limitation, specific details are set forth in order to provide a thorough understanding of the present disclosure, including, without limitation, particular architectures, interfaces and/or techniques. In some instances, detailed descriptions of well-known systems, technologies, components, devices, circuits, methods and applications are omitted so as not to obscure the description of the present disclosure with unnecessary detail.

Further, it will be appreciated that block diagrams reproduced herein can represent conceptual views of illustrative components embodying the principles of the technology.

Accordingly, the system and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the examples of the present disclosure, so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

Any drawings provided herein may not be drawn to scale and may not be considered to limit the present disclosure in any way.

Any feature or action shown in dashed outline may in some examples be considered as optional.

SUMMARY

It is an object of the present disclosure to obviate or mitigate at least one disadvantage of the prior art.

The present disclosure discloses an opto-electronic device having a plurality of layers, comprising, in a lateral aspect, a first portion and a second portion. In the first portion, the device comprises a nucleation-inhibiting coating (NIC) is disposed on a first layer surface.

In the second portion, a conductive coating is disposed on a second layer surface.

An initial sticking probability for forming the conductive coating onto a surface of the NIC in the first portion is substantially less than the initial sticking probability for forming the conductive coating onto the second layer surface in the second portion. Accordingly, in some embodiments, the first portion is substantially devoid of the conductive coating.

According to a broad aspect of the present disclosure, there is disclosed an opto-electronic device having a plurality of layers, comprising: a nucleation-inhibiting coating (NIC) disposed on a first layer surface in a first portion in a lateral aspect thereof; and a conductive coating disposed on a second layer surface in a second portion of the lateral aspect thereof; wherein the surface of the NIC in the first portion is substantially devoid of the conductive coating; and wherein the NIC comprises a compound of Formula (I), (II), (III), (IV), (V), (VI), (VII), (VIII), (IX), (X), (XI), (XII), (XIII), (XIV), (XV), (XVI), (XVII), (XVIII), (XIX), and/or (XX):

• • wherein:
  • L¹ independently represents C, CR², CR²R³, N, NR³, S, O, substituted or unsubstituted cycloalkylene having 3-6 carbon atoms, substituted or unsubstituted arylene group having 5-60 carbon atoms, or a substituted or unsubstituted heteroarylene group having 4-60 carbon atoms;
  • Ar¹ independently represents a substituted or unsubstituted aryl group having 5 to 60 carbon atoms, a substituted or unsubstituted haloaryl group having 5 to 60 carbon atoms, or a substituted or unsubstituted heteroaryl group having 4 to 60 carbon atoms;
  • R¹, R², and R³ independently represents H, D (deutero), F, Cl, alkyl including C1-C6 alkyl, cycloaklyl including C3-C6 cycloalkyl, alkoxy including C1-C6 alkoxy, fluoroalkyl, haloaryl, heteroaryl, haloalkoxy, fluoroaryl, fluoroalkoxy, fluoroalkylsulfanyl, fluoromethyl, difluoromethyl, trifluoromethyl, difluoromethoxy, trifluoromethoxy, fluoroethyl, polyfluoroethyl, 4-fluorophenyl, 3,4,5-trifluorophenyl, polyfluoroaryl, 4-(trifluoromethoxy)phenyl, SF₄Cl, SF₅, (CF₂)_aSF₅, (O(CF₂)_b)_dCF₃, (CF₂)_e(O(CF₂)_b)_d)CF₃, or trifluoromethylsulfanyl;
  • Z independently represents F or Cl;
  • s represents an integer of 0 to 4, wherein the sum of r and s is 5;
  • r represents an integer of 1 to 3;
  • p represents an integer of 0 to 6;
  • q represents an integer of 1 to 8;
  • represents an integer of 2 to 4;
  • j represents an integer of 1 to 3;
  • k represents an integer of 1 to 4;
  • t represents an integer of 2 to 6;
  • u represents an integer of 0 to 2, wherein the sum of r and u is 3;
  • h represents an integer of 0 to 4, wherein the sum of r and h is 4;
  • i represents an integer of 1 to 4;
  • a represents an integer of 2 to 6;
  • b represents an integer of 1 to 4;
  • d represents an integer of 1 to 3; and
  • e represents an integer of 1 to 4.

Examples have been described above in conjunctions with aspects of the present disclosure upon which they can be implemented. Those skilled in the art will appreciate that examples may be implemented in conjunction with the aspect with which they are described, but may also be implemented with other examples of that or another aspect. When examples are mutually exclusive, or are otherwise incompatible with each other, it will be apparent to those having ordinary skill in the relevant art. Some examples may be described in relation to one aspect, but may also be applicable to other aspects, as will be apparent to those having ordinary skill in the relevant art.

Some aspects or examples of the present disclosure may provide an opto-electronic device having a first portion of a lateral aspect thereof, comprising a nucleation-inhibiting coating (NIC) on a first layer surface thereof and a second portion having a conductive coating on a second layer surface thereof, wherein an initial sticking probability for forming the conductive coating onto a surface of the NIC in the first portion is substantially less than the initial sticking probability for forming the conductive coating onto the second layer surface in the second portion, such that the first portion is substantially devoid of the conductive coating.

DESCRIPTION

Opto-Electronic Device

The present disclosure relates generally to electronic devices, and more specifically, to opto-electronic devices. An opto-electronic device generally encompasses any device that converts electrical signals into photons and vice versa.

In the present disclosure, the terms “photon” and “light” may be used interchangeably to refer to similar concepts. In the present disclosure, photons may have a wavelength that lies in the visible light spectrum, in the infrared (IR) and/or ultraviolet (UV) region thereof.

An organic opto-electronic device can encompass any opto-electronic device where one or more active layers and/or strata thereof are formed primarily of an organic (carbon-containing) material, and more specifically, an organic semiconductor material.

In the present disclosure, it will be appreciated by those having ordinary skill in the relevant art that an organic material, may comprise, without limitation, a wide variety of organic molecules, and/or organic polymers. Further, it will be appreciated by those having ordinary skill in the relevant art that organic materials that are doped with various inorganic substances, including without limitation, elements and/or inorganic compounds, may still be considered to be organic materials. Still further, it will be appreciated by those having ordinary skill in the relevant art that various organic materials may be used, and that the processes described herein are generally applicable to an entire range of such organic materials.

In the present disclosure, an inorganic substance may refer to a substance that primarily includes an inorganic material. In the present disclosure, an inorganic material may comprise any material that is not considered to be an organic material, including without limitation, metals, glasses and/or minerals.

Where the opto-electronic device emits photons through a luminescent process, the device may be considered an electro-luminescent device. In some non-limiting examples, the electro-luminescent device may be an organic light-emitting diode (OLED) device. In some non-limiting examples, the electro-luminescent device may be part of an electronic device. By way of non-limiting example, the electro-luminescent device may be an OLED lighting panel or module, and/or an OLED display or module of a computing device, such as a smartphone, a tablet, a laptop, an e-reader, and/or of some other electronic device such as a monitor and/or a television set.

In some non-limiting examples, the opto-electronic device may be an organic photo-voltaic (OPV) device that converts photons into electricity. In some non-limiting examples, the opto-electronic device may be an electro-luminescent quantum dot device. In the present disclosure, unless specifically indicated to the contrary, reference will be made to OLED devices, with the understanding that such disclosure could, in some examples, equally be made applicable to other opto-electronic devices, including without limitation, an OPV and/or quantum dot device in a manner apparent to those having ordinary skill in the relevant art.

The structure of such devices will be described from each of two aspects, namely from a cross-sectional aspect and/or from a lateral (plan view) aspect.

In the present disclosure, the terms “layer” and “strata” may be used interchangeably to refer to similar concepts.

In the context of introducing the cross-sectional aspect below, the components of such devices are shown in substantially planar lateral strata. Those having ordinary skill in the relevant art will appreciate that such substantially planar representation is for purposes of illustration only, and that across a lateral extent of such a device, there may be localized substantially planar strata of different thicknesses and dimension, including, in some non-limiting examples, the substantially complete absence of a layer, and/or layer(s) separated by non-planar transition regions (including lateral gaps and even discontinuities). Thus, while for illustrative purposes, the device is shown below in its cross-sectional aspect as a substantially stratified structure, in the plan view aspect discussed below, such device may illustrate a diverse topography to define features, each of which may substantially exhibit the stratified profile discussed in the cross-sectional aspect.

Cross-Sectional Aspect

FIG. 1 is a simplified block diagram from a cross-sectional aspect, of an example electro-luminescent device according to the present disclosure. The electro-luminescent device, shown generally at 100 comprises, a substrate 110, upon which a frontplane 10, comprising a plurality of layers, respectively, a first electrode 120, at least one semiconducting layer 130, and a second electrode 140, are disposed. In some non-limiting examples, the frontplane 10 may provide mechanisms for photon emission and/or manipulation of emitted photons. In some non-limiting examples, a barrier coating 1650 (FIG. 16C) may be provided to surround and/or encapsulate the layers 120, 130, 140 and/or the substrate 110 disposed thereon.

For purposes of illustration, an exposed layer surface of underlying material is referred to as 111. In FIG. 1, the exposed layer surface 111 is shown as being of the second electrode 140. Those having ordinary skill in the relevant art will appreciate that, at the time of deposition of, by way of non-limiting example, the first electrode 120, the exposed layer surface 111 would have been shown as 111a, of the substrate 110.

Those having ordinary skill in the relevant art will appreciate that when a component, a layer, a region and/or portion thereof is referred to as being “formed”, “disposed” and/or “deposited” on another underlying material, component, layer, region and/or portion, such formation, disposition and/or deposition may be directly and/or indirectly on an exposed layer surface 111 (at the time of such formation, disposition and/or deposition) of such underlying material, component, layer, region and/or portion, with the potential of intervening material(s), component(s), layer(s), region(s) and/or portion(s) therebetween.

In the present disclosure, a directional convention is followed, extending substantially normally relative to the lateral aspect described above, in which the substrate 110 is considered to be the “bottom” of the device 100, and the layers 120, 130, 140 are disposed on “top” of the substrate 11. Following such convention, the second electrode 140 is at the top of the device 100 shown, even if (as may be the case in some examples, including without limitation, during a manufacturing process, in which one or more layers 120, 130, 140 may be introduced by means of a vapor deposition process), the substrate 110 is physically inverted such that the top surface, on which one of the layers 120, 130, 140, such as, without limitation, the first electrode 120, is to be disposed, is physically below the substrate 110, so as to allow the deposition material (not shown) to move upward and be deposited upon the top surface thereof as a thin film.

In some non-limiting examples, the device 100 may be electrically coupled to a power source 15. When so coupled, the device 100 may emit photons as described herein.

In some non-limiting examples, the device 100 may be classified according to a direction of emission of photons generated therefrom. In some non-limiting examples, the device 100 may be considered to be a bottom-emission device if the photons generated are emitted in a direction toward and through the substrate 100 at the bottom of the device 100 and away from the layers 120, 130, 140 disposed on top of the substrate 110. In some non-limiting examples, the device 100 may be considered to be a top-emission device if the photons are emitted in a direction away from the substrate 110 at the bottom of the device 100 and toward and/or through the top layer 140 disposed, with intermediate layers 120, 130, on top of the substrate 110. In some non-limiting examples, the device 100 may be considered to be a double-sided emission device if it is configured to emit photons in both the bottom (toward and through the substrate 110) and top (toward and through the top layer 140).

Thin Film Formation

The frontplane 10 layers 120, 130, 140 may be disposed in turn on a target exposed layer surface 111 (and/or, in some non-limiting examples, including without limitation, in the case of selective deposition disclosed herein, at least one target region and/or portion of such surface) of an underlying material, which in some non-limiting examples, may be, from time to time, the substrate 110 and intervening lower layers 120, 130, 140, as a thin film. In some non-limiting examples, an electrode 120, 140, 1750, 4150 may be formed of at least one thin conductive film layer of a conductive coating 830 (FIG. 8).

The thickness of each layer, including without limitation, layers 120, 130, 140, and of the substrate 110, shown in FIG. 1, and throughout the FIGURES, is illustrative only and not necessarily representative of a thickness relative to another layer 120, 130, 140 (and/or of the substrate 110).

The formation of thin films during vapor deposition on an exposed layer surface 111 of an underlying material involves processes of nucleation and growth. During initial stages of film formation, a sufficient number of vapor monomers (which in some non-limiting examples may be molecules and/or atoms) typically condense from a vapor phase to form initial nuclei on the surface 111 presented, whether of the substrate 110 (or of an intervening lower layer 120, 130, 140). As vapor monomers continue to impinge on such surface, a size and density of these initial nuclei increase to form small clusters or islands. After reaching a saturation island density, adjacent islands typically will start to coalesce, increasing an average island size, while decreasing an island density. Coalescence of adjacent islands may continue until a substantially closed film is formed.

There may be at least three basic growth modes for the formation of thin films: 1) island (Volmer-Weber), 2) layer-by-layer (Frank-van der Merwe), and 3) Stranski-Krastanov. Island growth typically occurs when stale clusters of monomers nucleate on a surface and grow to form discrete islands. This growth mode occurs when the interactions between the monomers is stronger than that between the monomers and the surface.

The nucleation rate describes how many nuclei of a given size (where the free energy does not push a cluster of such nuclei to either grow or shrink) (“critical nuclei”) form on a surface per unit time. During initial stages of film formation, it is unlikely that nuclei will grow from direct impingement of monomers on the surface, since the density of nuclei is low, and thus the nuclei cover a relatively small fraction of the surface (e.g. there are large gaps/spaces between neighboring nuclei). Therefore, the rate at which critical nuclei grow typically depends on the rate at which adatoms (e.g. adsorbed monomers) on the surface migrate and attach to nearby nuclei.

After adsorption of an adatom on a surface, the adatom may either desorb from the surface, or may migrate some distance on the surface before either desorbing, interacting with other adatoms to form a small cluster, or attaching to a growing nucleus. An average amount of time that an adatom remains on the surface after initial adsorption is given by:

${\tau }_s=\frac{1}{v}\exp \left(\frac{E_{des}}{\mathrm{kT}}\right)$

In the above equation, v is a vibrational frequency of the adatom on the surface, k is the Botzmann constant, T is temperature, and E_des 631 (FIG. 6) is an energy involved to desorb the adatom from the surface. From this equation it is noted that the lower the value of E_des 631 the easier it is for the adatom to desorb from the surface, and hence the shorter the time the adatom will remain on the surface. A mean distance an adatom can diffuse is given by,

$X=a_0\exp \left(\frac{E_{des}-E_s}{2kT}\right)$ where a₀ is a lattice constant and E_s 621 (FIG. 6) is an activation energy for surface diffusion. For low values of E_des 631 and/or high values of E_s 621, the adatom will diffuse a shorter distance before desorbing, and hence is less likely to attach to growing nuclei or interact with another adatom or cluster of adatoms.

During initial stages of film formation, adsorbed adatoms may interact to form clusters, with a critical concentration of clusters per unit area being given by,

$\frac{N_i}{n_0}={\frac{N_1}{n_0}}^i\exp \left(\frac{E_i}{kT}\right)$ where E_i is an energy involved to dissociate a critical cluster containing i adatoms into separate adatoms, n₀ is a total density of adsorption sites, and N₁ is a monomer density given by:

$N_1=\stackrel{.}{R}{\tau }_s$ where {dot over (R)} is a vapor impingement rate. Typically i will depend on a crystal structure of a material being deposited and will determine the critical cluster size to form a stable nucleus.

A critical monomer supply rate for growing clusters is given by the rate of vapor impingement and an average area over which an adatom can diffuse before desorbing:

$\stackrel{.}{R}{X}^2={\alpha }_0^2\exp \left(\frac{E_{des}-E_s}{kT}\right)$

The critical nucleation rate is thus given by the combination of the above equations:

${\stackrel{.}{N}}_i=\stackrel{.}{R}{\alpha }_0^2{n_0\left(\frac{\stackrel{.}{R}}{v{n}_0}\right)}^i\exp \left(\frac{\left(i+1\right)E_{des}-E_s+E_i}{kT}\right)$

From the above equation it is noted that the critical nucleation rate will be suppressed for surfaces that have a low desorption energy for adsorbed adatoms, a high activation energy for diffusion of an adatom, are at high temperatures, and/or are subjected to vapor impingement rates.

Sites of substrate heterogeneities, such as defects, ledges or step edges, may increase E_des 631, leading to a higher density of nuclei observed at such sites. Also, impurities or contamination on a surface may also increase E_des 631, leading to a higher density of nuclei. For vapor deposition processes, conducted under high vacuum conditions, the type and density of contaminates on a surface is affected by a vacuum pressure and a composition of residual gases that make up that pressure.

Under high vacuum conditions, a flux of molecules that impinge on a surface (per cm²-sec) is given by:

$\varphi =3.513\times 10^{22}\frac{P}{MT}$ where P is pressure, and M is molecular weight. Therefore, a higher partial pressure of a reactive gas, such as H₂O, can lead to a higher density of contamination on a surface during vapor deposition, leading to an increase in E_des 631 and hence a higher density of nuclei.

While the present disclosure discusses thin film formation, in reference to at least one layer or coating, in terms of vapor deposition, those having ordinary skill in the relevant art will appreciate that, in some non-limiting examples, various components of the electro-luminescent device 100 may be selectively deposited using a wide variety of techniques, including without limitation, evaporation (including without limitation, thermal evaporation and/or electron beam evaporation), photolithography, printing (including without limitation, ink jet and/or vapor jet printing, reel-to-reel printing and/or micro-contact transfer printing), physical vapor deposition (PVD) (including without limitation, sputtering), chemical vapor deposition (CVD) (including without limitation, plasma-enhanced CVD (PECVD) and/or organic vapor phase deposition (OVPD)), laser annealing, laser-induced thermal imaging (LITI) patterning, atomic-layer deposition (ALD), coating (including without limitation, spin coating, dip coating, line coating and/or spray coating), and/or combinations of any two or more thereof. Some processes may be used in combination with a shadow mask, which may, in some non-limiting examples, be an open mask and/or fine metal mask (FMM), during deposition of any of various layers and/or coatings to achieve various patterns by masking and/or precluding deposition of a deposited material on certain portions of a surface of an underlying material exposed thereto.

In the present disclosure, the terms “evaporation” and/or “sublimation” may be used interchangeably to refer generally to deposition processes in which a source material is converted into a vapor, including without limitation by heating, to be deposited onto a target surface in, without limitation, a solid state. As will be understood, an evaporation process is a type of PVD process where one or more source materials are evaporated and/or sublimed under a low pressure (including without limitation, a vacuum) environment and deposited on a target surface through de-sublimation of the one or more evaporated source materials. A variety of different evaporation sources may be used for heating a source material, and, as such, it will be appreciated by those having ordinary skill in the relevant art, that the source material may be heated in various ways. By way of non-limiting example, the source material may be heated by an electric filament, electron beam, inductive heating, and/or by resistive heating. In some non-limiting examples, the source material may be loaded into a heated crucible, a heated boat, a Knudsen cell (which may be an effusion evaporator source) and/or any other type of evaporation source.

In some non-limiting examples, a deposition source material may be a mixture. In some non-limiting examples, at least one component of a mixture of a deposition source material may not be deposited during the deposition process (or, in some non-limiting examples, be deposited in a relatively small amount compared to other components of such mixture).

In the present disclosure, a reference to a layer thickness of a material, irrespective of the mechanism of deposition thereof, refers to an amount of the material deposited on a target exposed layer surface 111, which corresponds to an amount of the material to cover the target surface with a uniformly thick layer of the material having the referenced layer thickness. By way of non-limiting example, depositing a layer thickness of 10 nanometers (nm) of material indicates that an amount of the material deposited on the surface corresponds to an amount of the material to form a uniformly thick layer of the material that is 10 nm thick. It will be appreciated that, having regard to the mechanism by which thin films are formed discussed above, by way of non-limiting example, due to possible stacking or clustering of monomers, an actual thickness of the deposited material may be non-uniform. By way of non-limiting example, depositing a layer thickness of 10 nm may yield some parts of the deposited material having an actual thickness greater than 10 nm, or other parts of the deposited material having an actual thickness less than 10 nm. A certain layer thickness of a material deposited on a surface may thus correspond, in some non-limiting examples, to an average thickness of the deposited material across the target surface.

In the present disclosure, a reference to a reference layer thickness refers to a layer thickness of magnesium (Mg) that is deposited on a reference surface exhibiting a high initial sticking probability S₀ (that is, a surface having an initial sticking probability S₀ that is about and/or close to 1). The reference layer thickness does not indicate an actual thickness of Mg deposited on a target surface (such as, without limitation, a surface of a nucleation-inhibiting coating (NIC) 810 (FIG. 8)). Rather, the reference layer thickness refers to a layer thickness of Mg that would be deposited on a reference surface, in some non-limiting examples, a surface of a quartz crystal positioned inside a deposition chamber for monitoring a deposition rate and the reference layer thickness, upon subjecting the target surface and the reference surface to identical Mg vapor flux for the same deposition period. Those having ordinary skill in the relevant art will appreciate that in the event that the target surface and the reference surface are not subjected to identical vapor flux simultaneously during deposition, an appropriate tooling factor may be used to determine and/or to monitor the reference layer thickness.

In the present disclosure, a reference to depositing a number X of monolayers of material refers to depositing an amount of the material to cover a desired area of an exposed layer surface 111 with X single layer(s) of constituent monomers of the material. In the present disclosure, a reference to depositing a fraction 0.X monolayer of a material refers to depositing an amount of the material to cover a fraction 0.X of a desired area of a surface with a single layer of constituent monomers of the material. Those having ordinary skill in the relevant art will appreciate that due to, by way of non-limiting example, possible stacking and/or clustering of monomers, an actual local thickness of a deposited material across a desired area of a surface may be non-uniform. By way of non-limiting example, depositing 1 monolayer of a material may result in some local regions of the desired area of the surface being uncovered by the material, while other local regions of the desired area of the surface may have multiple atomic and/or molecular layers deposited thereon.

In the present disclosure, a target surface (and/or target region(s) thereof) may be considered to be “substantially devoid of”, “substantially free of” and/or “substantially uncovered by” a material if there is a substantial absence of the material on the target surface as determined by any suitable determination mechanism.

In some non-limiting examples, one measure of an amount of a material on a surface is a percentage coverage of the surface by such material. In some non-limiting examples surface coverage may be assessed using a variety of imaging techniques, including without limitation, transmission electron microscopy (TEM), atomic force microscopy (AFM) and/or scanning electron microscopy (SEM).

In some non-limiting examples, one measure of an amount of an electrically conductive material on a surface is a (light) transmittance, since in some non-limiting examples, electrically conductive materials, including without limitation, metals, including without limitation Mg, attenuate and/or absorb photons.

Thus, in some non-limiting examples, a surface of a material may be considered to be substantially devoid of an electrically conductive material if the transmittance therethrough is greater than 90%, greater than 92%, greater than 95%, and/or greater than 98% of the transmittance of a reference material of similar composition and dimension of such material, in some non-limiting examples, in the visible part of the electromagnetic spectrum.

In the present disclosure, for purposes of simplicity of illustration, details of deposited materials, including without limitation, thickness profiles and/or edge profiles of layer(s) have been omitted. Various possible edge profiles at an interface between NICs 810 and conductive coatings 830 are discussed herein.

Substrate

In some examples, the substrate 110 may comprise a base substrate 112. In some examples, the base substrate 112 may be formed of material suitable for use thereof, including without limitation, an inorganic material, including without limitation, silicon (Si), glass, metal (including without limitation, a metal foil), sapphire, and/or other inorganic material, and/or an organic material, including without limitation, a polymer, including without limitation, a polyimide and/or a silicon-based polymer. In some examples, the base substrate 112 may be rigid or flexible. In some examples, the substrate 112 may be defined by at least one planar surface. The substrate 110 has at least one surface that supports the remaining front plane 10 components of the device 100, including without limitation, the first electrode 120, the at least one semiconducting layer 130 and/or the second electrode 140.

In some non-limiting examples, such surface may be an organic surface and/or an inorganic surface.

In some examples, the substrate 110 may comprise, in addition to the base substrate 112, one or more additional organic and/or inorganic layers (not shown nor specifically described herein) supported on an exposed layer surface 111 of the base substrate 112.

In some non-limiting examples, such additional layers may comprise and/or form one or more organic layers, which may comprise, replace and/or supplement one or more of the at least one semiconducting layers 130.

In some non-limiting examples, such additional layers may comprise one or more inorganic layers, which may comprise and/or form one or more electrodes, which in some non-limiting examples, may comprise, replace and/or supplement the first electrode 120 and/or the second electrode 140.

In some non-limiting examples, such additional layers may comprise and/or be formed of and/or as a backplane layer 20 (FIG. 2) of a semiconductor material. In some non-limiting examples, the backplane layer 20 contains power circuitry and/or switching elements for driving the device 100, including without limitation, electronic TFT structure(s) and/or component(s) 200 (FIG. 2) thereof that may be formed by a photolithography process, which may not be provided under, and/or may precede the introduction of low pressure (including without limitation, a vacuum) environment.

In the present disclosure, a semiconductor material may be described as a material that generally exhibits a band gap. In some non-limiting examples, the band gap may be formed between a highest occupied molecular orbital (HOMO) and a lowest unoccupied molecular orbital (LUMO) of the semiconductor material. Semiconductor materials thus generally exhibit electrical conductivity that is less than that of a conductive material (including without limitation, a metal), but that is greater than that of an insulating material (including without limitation, a glass). In some non-limiting examples, the semiconductor material may comprise an organic semiconductor material. In some non-limiting examples, the semiconductor material may comprise an inorganic semiconductor material.

Backplane and TFT Structure(s) Embodied Therein

FIG. 2 is a simplified cross-sectional view of an example of the substrate 110 of the device 100, including a backplane layer 20 thereof. In some non-limiting examples, the backplane 20 of the substrate 110 may comprise one or more electronic and/or opto-electronic components, including without limitation, transistors, resistors and/or capacitors, such as which may support the device 100 acting as an active-matrix and/or a passive matrix device. In some non-limiting examples, such structures may be a thin-film transistor (TFT) structure, such as is shown at 200. In some non-limiting examples, the TFT structure 200 may be fabricated using organic and/or inorganic materials to form various layers 210, 220, 230, 240, 250, 270, 270, 280 and/or parts of the backplane layer 20 of the substrate 110 above the base substrate 112. In FIG. 2, the TFT structure 200 shown is a top-gate TFT. In some non-limiting examples, TFT technology and/or structures, including without limitation, one or more of the layers 210, 220, 230, 240, 250, 270, 270, 280, may be employed to implement non-transistor components, including without limitation, resistors and/or capacitors.

In some non-limiting examples, the backplane 20 may comprise a buffer layer 210 deposited on an exposed layer surface 111 of the base substrate 112 to support the components of the TFT structure 200. In some non-limiting examples, the TFT structure 200 may comprise a semiconductor active area 220, a gate insulating layer 230, a TFT gate electrode 240, an interlayer insulating layer 250, a TFT source electrode 260, a TFT drain electrode 270 and/or a TFT insulating layer 280. In some non-limiting examples, the semiconductor active area 220 is formed over a part of the buffer layer 210, and the gate insulating layer 230 is deposited on substantially cover the semiconductor active area 220. In some non-limiting examples, the gate electrode 240 is formed on top of the gate insulating layer 230 and the interlayer insulating layer 250 is deposited thereon. The TFT source electrode 270 and the TFT drain electrode 270 are formed such that they extend through openings formed through both the interlayer insulating layer 250 and the gate insulating layer 230 such that they are electrically coupled to the semiconductor active area 220. The TFT insulating layer 280 is then formed over the TFT structure 200.

In some non-limiting examples, one or more of the layers 210, 220, 230, 240, 250, 270, 270, 280 of the backplane 20 may be patterned using photolithography, which uses a photomask to expose selective parts of a photoresist covering an underlying device layer to UV light. Depending upon a type of photoresist used, exposed or unexposed parts of the photomask may then be removed to reveal desired parts of the underlying device layer. In some examples, the photoresist is a positive photoresist, in which the selective parts thereof exposed to UV light are not substantially removable thereafter, while the remaining parts not so exposed are substantially removable thereafter. In some non-limiting examples, the photoresist is a negative photoresist, in which the selective parts thereof exposed to UV light are substantially removable thereafter, while the remaining parts not so exposed are not substantially removable thereafter. A patterned surface may thus be etched, including without limitation, chemically and/or physically, and/or washed off and/or away, to effectively remove an exposed part of such layer 210, 220, 230, 240, 250, 260, 270, 280.

Further, while a top-gate TFT structure 200 is shown in FIG. 2, those having ordinary skill in the relevant art will appreciate that other TFT structures, including without limitation a bottom-gate TFT structure, may be formed in the backplane 20 without departing from the scope of the present disclosure.

In some non-limiting examples, the TFT structure 200 may be an n-type TFT and/or a p-type TFT. In some non-limiting examples, the TFT structure 200 may incorporate any one or more of amorphous Si (a-Si), indium gallium zinc (Zn) oxide (IGZO) and/or low-temperature polycrystalline Si (LTPS).

First Electrode

The first electrode 120 is deposited over the substrate 110. In some non-limiting examples, the first electrode 120 is electrically coupled to a terminal of the power source 15 and/or to ground. In some non-limiting examples, the first electrode 120 is so coupled through at least one driving circuit 300 (FIG. 3), which in some non-limiting examples, may incorporate at least one TFT structure 200 in the backplane 20 of the substrate 110.

In some non-limiting examples, the first electrode 120 may comprise an anode 341 (FIG. 3) and/or a cathode 342 (FIG. 3). In some non-limiting examples, the first electrode 120 is an anode 341.

In some non-limiting examples, the first electrode 120 may be formed by depositing at least one thin conductive film, over (a portion of) the substrate 110. In some non-limiting examples, there may be a plurality of first electrodes 120, disposed in a spatial arrangement over a lateral aspect of the substrate 110. In some non-limiting examples, one or more of such at least one first electrodes 120 may be deposited over (a portion of) the TFT insulating layer 280 disposed in a lateral aspect in a spatial arrangement. If so, in some non-limiting examples, at least one of such at least one first electrodes 120 may extend through an opening of the corresponding TFT insulating layer 280, as shown in FIG. 4, to be electrically coupled to an electrode 240, 260, 270 of the TFT structure 200 in the backplane 20. In FIG. 4, a part of the at least one first electrode 120 is shown coupled to the TFT drain electrode 270.

In some non-limiting examples, the at least one first electrode 120 and/or at least one thin film thereof, may comprise various materials, including without limitation, one or more metallic materials, including without limitation, Mg, aluminum (Al), calcium (Ca), Zn, silver (Ag), cadmium (Cd), barium (Ba) and/or ytterbium (Yb), and/or combinations of any two or more thereof, including without limitation, alloys containing any of such materials, one or more metal oxides, including without limitation, a transparent conducting oxide (TCO), including without limitation, ternary compositions such as, without limitation, fluorine tin oxide (FTO), indium zinc oxide (IZO), and/or indium tin oxide (ITO), and/or combinations of any two or more thereof and/or in varying proportions, and/or combinations of any two or more thereof in at least one layer, any one or more of which may be, without limitation, a thin film.

In some non-limiting examples, a thin conductive film comprising the first electrode 120 may be selectively deposited, deposited and/or processed using a variety of techniques, including without limitation, evaporation (including without limitation, thermal evaporation and/or electron beam evaporation), photolithography, printing (including without limitation, ink jet and/or vapor jet printing, reel-to-reel printing and/or micro-contact transfer printing), PVD (including without limitation, sputtering), CVD (including without limitation, PECVD and/or OVPD), laser annealing, LITI patterning, ALD, coating (including without limitation, spin coating, dip coating, line coating and/or spray coating), and/or combinations of any two or more thereof.

Second Electrode

The second electrode 140 is deposited over the at least one semiconducting layer 130. In some non-limiting examples, the second electrode 140 is electrically coupled to a terminal of the power source 15 and/or to ground. In some non-limiting examples, the second electrode 140 is so coupled through at least one driving circuit 300, which in some non-limiting examples, may incorporate at least one TFT structure 200 in the backplane 20 of the substrate 110.

In some non-limiting examples, the second electrode 140 may comprise an anode 341 and/or a cathode 342. In some non-limiting examples, the second electrode 130 is a cathode 342.

In some non-limiting examples, the second electrode 140 may be formed by depositing a conductive coating 830, in some non-limiting examples, as at least one thin film, over (a part of) the at least one semiconducting layer 130. In some non-limiting examples, there may be a plurality of second electrodes 140, disposed in a spatial arrangement over a lateral aspect of the at least one semiconducting layer 130.

In some non-limiting examples, the at least one second electrode 140 may comprise various materials, including without limitation, one or more metallic materials, including without limitation, Mg, Al, Ca, Zn, Ag, Cd, Ba and/or Yb, and/or combinations of any two or more thereof, including without limitation, alloys containing any of such materials, one or more metal oxides, including without limitation, a TCO, including without limitation, ternary compositions such as, without limitation, FTO, IZO, and/or ITO, and/or combinations of any two or more thereof and/or in varying proportions, and/or zinc oxide (ZnO) and/or other oxides containing indium (In) and/or Zn, and/or combinations of any two or more thereof in at least one layer, and/or one or more non-metallic materials, any one or more of which may be, without limitation, a thin conductive film. In some non-limiting examples, for a Mg:Ag alloy, such alloy composition may range from about 1:9 to about 9:1 by volume.

In some non-limiting examples, a thin conductive film comprising the second electrode 140 may be selectively applied, deposited and/or processed using a variety of techniques, including without limitation, evaporation (including without limitation, thermal evaporation and/or electron beam evaporation), photolithography, printing (including without limitation, ink jet and/or vapor jet printing, reel-to-reel printing and/or micro-contact transfer printing), PVD (including without limitation, sputtering), CVD (including without limitation, PECVD and/or OVPD), laser annealing, LITI patterning, ALD, coating (including without limitation, spin coating, dip coating, line coating and/or spray coating), and/or combinations of any two or more thereof.

In some non-limiting examples, the deposition of the second electrode 140 may be performed using an open-mask and/or a mask-free deposition process.

In some non-limiting examples, the second electrode 140 may comprise a plurality of such layers and/or coatings. In some non-limiting examples, such layers and/or coatings may be distinct layers and/or coatings disposed on top of one another.

In some non-limiting examples, the second electrode 140 may comprise a Yb/Ag bi-layer coating. By way of non-limiting examples, such bi-layer coating may be formed by depositing a Yb coating, followed by an Ag coating. A thickness of such Ag coating may be greater than a thickness of the Yb coating.

In some non-limiting examples, the second electrode 140 may be a multi-layer electrode 140 comprising at least one metallic layer and/or at least one oxide layer.

In some non-limiting examples, the second electrode 140 may comprise a fullerene and Mg.

In the present disclosure, the term “fullerene” may refer generally to a material including carbon molecules. Non-limiting examples of fullerene molecules include carbon cage molecules, including without limitation, a three-dimensional skeleton that includes multiple carbon atoms that form a closed shell and which may be, without limitation, spherical and/or semi-spherical in shape. In some non-limiting examples, a fullerene molecule can be designated as C_n, where n is an integer corresponding to a number of carbon atoms included in a carbon skeleton of the fullerene molecule. Non-limiting examples of fullerene molecules include C_n, where n is in the range of 50 to 250, such as, without limitation, C_n, C₇₀, C₇₂, C₇₄n C₇₆n C₇₈n C₈₀, C₈₂, and C₈₄. Additional non-limiting examples of fullerene molecules include carbon molecules in a tube and/or a cylindrical shape, including without limitation, single-walled carbon nanotubes and/or multi-walled carbon nanotubes.

By way of non-limiting examples, such coating may be formed by depositing a fullerene coating followed by an Mg coating. In some non-limiting examples, a fullerene may be dispersed within the Mg coating to form a fullerene-containing Mg alloy coating. Non-limiting examples of such coatings are described in United States Patent Application Publication No. 2015/0287846 published 8 Oct. 2015 and/or in PCT International Application No. PCT/IB2017/054970 filed 15 Aug. 2017 and published as WO2018/033860 on 22 Feb. 2018.

Driving Circuit

In the present disclosure, the concept of a sub-pixel 2641-2643 (FIG. 26) may be referenced herein, for simplicity of description only, as a sub-pixel 264x. Likewise, in the present disclosure, the concept of a pixel 340 (FIG. 3) may be discussed in conjunction with the concept of at least one sub-pixel 264x thereof. For simplicity of description only, such composite concept is referenced herein as a “(sub-)pixel 340/264x” and such term is understood to suggest either or both of a pixel 340 and/or at least one sub-pixel 264x thereof, unless the context dictates otherwise.

FIG. 3 is a circuit diagram for an example driving circuit such as may be provided by one or more of the TFT structures 200 shown in the backplane 20. In the example shown, the circuit, shown generally at 300 is for an example driving circuit for an active-matrix OLED (AMOLED) device 100 (and/or a (sub-)pixel 340/264x thereof) for supplying current to the first electrode 120 and the second electrode 140, and that controls emission of photons from the device 100 (and/or a (sub-)pixel 340/264x). The circuit 300 shown incorporates a plurality of p-type top-gate thin film TFT structures 200, although the circuit 300 could equally incorporate one or more p-type bottom-gate TFT structures 200, one or more n-type top-gate TFT structures 200, one or more n-type bottom-gate TFT structures 200, one or more other TFT structure(s) 200, and/or any combination thereof, whether or not formed as one or a plurality of thin film layers. The circuit 300 comprises, in some non-limiting examples, a switching TFT 310, a driving TFT 320 and a storage capacitor 330.

A (sub-)pixel 340/264x of the OLED display 100 is represented by a diode 340. The source 311 of the switching TFT 310 is coupled to a data (or, in some non-limiting examples, a column selection) line 30. The gate 312 of the switching TFT 310 is coupled to a gate (or, in some non-limiting examples, a row selection) line 31. The drain 313 of the switching TFT 310 is coupled to the gate 322 of the driving TFT 320.

The source 321 of the driving TFT 320 is coupled to a positive (or negative) terminal of the power source 15. The (positive) terminal of the power source 15 is represented by a power supply line (VDD) 32.

The drain 323 of the driving TFT 320 is coupled to the anode 341 (which may be, in some non-limiting examples, the first electrode 120) of the diode 340 (representing a (sub-)pixel 340/264x of the OLED display 100) so that the driving TFT 320 and the diode 340 (and/or a (sub-)pixel 340/264x of the OLED display 100) are coupled in series between the power supply line (VDD) 32 and ground.

The cathode 342 (which may be, in some non-limiting examples, the second electrode 140) of the diode 340 (representing a (sub-)pixel 340/264x of the OLED display 100) is represented as a resistor 350 in the circuit 300.

The storage capacitor 330 is coupled at its respective ends to the source 321 and gate 322 of the driving TFT 320. The driving TFT 320 regulates a current passed through the diode 340 (representing a (sub-)pixel 340/264x of the OLED display 100) in accordance with a voltage of a charge stored in the storage capacitor 330, such that the diode 340 outputs a desired luminance. The voltage of the storage capacitor 330 is set by the switching TFT 310, coupling it to the data line 30.

In some non-limiting examples, a compensation circuit 370 is provided to compensate for any deviation in transistor properties from variances during the manufacturing process and/or degradation of the switching TFT 310 and/or driving TFT 320 over time.

Semiconducting Layer

In some non-limiting examples, the at least one semiconducting layer 130 may comprise a plurality of layers 131, 133, 135, 137, 139, any of which may be disposed, in some non-limiting examples, in a thin film, in a stacked configuration, which may include, without limitation, any one or more of a hole injection layer (HIL) 131, a hole transport layer (HTL) 133, an emissive layer (EL) 135, an electron transport layer (ETL) 137 and/or an electron injection layer (EIL) 139. In the present disclosure, the term “semiconducting layer(s)” may be used interchangeably with “organic layer(s)” since the layers 131, 133, 135, 137, 139 in an OLED device 100 may in some non-limiting examples, may comprise organic semiconducting materials.

In some non-limiting examples, the at least one semiconducting layer 130 may form a “tandem” structure comprising a plurality of ELs 135. In some non-limiting examples, such tandem structure may also comprise at least one charge generation layer (CGL).

In some non-limiting examples, a thin film comprising a layer 131, 133, 135, 137, 139 in the stack making up the at least one semiconducting layer 130, may be selectively applied, deposited and/or processed using a variety of techniques, including without limitation, evaporation (including without limitation, thermal evaporation and/or electron beam evaporation), photolithography, printing (including without limitation, ink jet and/or vapor jet printing, reel-to-reel printing and/or micro-contact transfer printing), PVD (including without limitation, sputtering), CVD (including without limitation, PECVD and/or OVPD), laser annealing, LITI patterning, ALD, coating (including without limitation, spin coating, dip coating, line coating and/or spray coating), and/or combinations of any two or more thereof.

Those having ordinary skill in the relevant art will readily appreciate that the structure of the device 100 may be varied by omitting and/or combining one or more of the semiconductor layers 131, 133, 135, 137, 139.

Further, any of the layers 131, 133, 135, 137, 139 of the at least one semiconducting layer 130 may comprise any number of sub-layers. Still further, any of such layers 131, 133, 135, 137, 139 and/or sub-layer(s) thereof may comprise various mixture(s) and/or composition gradient(s). In addition, those having ordinary skill in the relevant art will appreciate that the device 100 may comprise one or more layers containing inorganic and/or organometallic materials and is not necessarily limited to devices composed solely of organic materials. By way of non-limiting example, the device 100 may comprise one or more quantum dots.

In some non-limiting examples, the HIL 131 may be formed using a hole injection material, which may facilitate injection of holes by the anode 341.

In some non-limiting examples, the HTL 133 may be formed using a hole transport material, which may, in some non-limiting examples, exhibit high hole mobility.

In some non-limiting examples, the ETL 137 may be formed using an electron transport material, which may, in some non-limiting examples, exhibit high electron mobility.

In some non-limiting examples, the EIL 139 may be formed using an electron injection material, which may facilitate injection of electrons by the cathode 342.

In some non-limiting examples, the EL 135 may be formed, by way of non-limiting example, by doping a host material with at least one emitter material. In some non-limiting examples, the emitter material may be a fluorescent emitter, a phosphorescent emitter, a thermally activated delayed fluorescence (TADF) emitter and/or a plurality of any combination of these.

In some non-limiting examples, the device 100 may be an OLED in which the at least one semiconducting layer 130 comprises at least an EL 135 interposed between conductive thin film electrodes 120, 140, whereby, when a potential difference is applied across them, holes are injected into the at least one semiconducting layer 130 through the anode 341 and electrons are injected into the at least one semiconducting layer 130 through the cathode 342.

The injected holes and electrons tend to migrate through the various layers 131, 133, 135, 137, 139 until they reach and meet each other. When a hole and an electron are in close proximity, they tend to be attracted to one another due to a Coulomb force and in some examples, may combine to form a bound state electron-hole pair referred to as an exciton. Especially if the exciton is formed in the EL 135, the exciton may decay through a radiative recombination process, in which a photon is emitted. The type of radiative recombination process may depend upon a spin state of an exciton. In some examples, the exciton may be characterized as having a singlet or a triplet spin state. In some non-limiting examples, radiative decay of a singlet exciton may result in fluorescence. In some non-limiting examples, radiative decay of a triplet exciton may result in phosphorescence.

More recently, other photon emission mechanisms for OLEDs have been proposed and investigated, including without limitation, TADF. In some non-limiting examples, TADF emission occurs through a conversion of triplet excitons into single excitons via a reverse inter-system crossing process with the aid of thermal energy, followed by radiative decay of the singlet excitons.

In some non-limiting examples, an exciton may decay through a non-radiative process, in which no photon is released, especially if the exciton is not formed in the EL 135.

In the present disclosure, the term “internal quantum efficiency” (IQE) of an OLED device 100 refers to a proportion of all electron-hole pairs generated in the device 100 that decay through a radiative recombination process and emit a photon.

In the present disclosure, the term “external quantum efficiency” (EQE) of an OLED device 100 refers to a proportion of charge carriers delivered to the device 100 relative to a number of photons emitted by the device 100. In some non-limiting examples, an EQE of 100% indicates that one photon is emitted for each electron that is injected into the device 100.

Those having ordinary skill in the relevant art will appreciate that the EQE of a device 100 may, in some non-limiting examples, be substantially lower than the IQE of the same device 100. A difference between the EQE and the IQE of a given device 100 may in some non-limiting examples be attributable to a number of factors, including without limitation, adsorption and reflection of photons caused by various components of the device 100.

In some non-limiting examples, the device 100 may be an electro-luminescent quantum dot device in which the at least one semiconducting layer 130 comprises an active layer comprising at least one quantum dot. When current is provided by the power source 15 to the first electrode 120 and second electrode 140, photons are emitted from the active layer comprising the at least one semiconducting layer 130 between them.

Those having ordinary skill in the relevant art will readily appreciate that the structure of the device 100 may be varied by the introduction of one or more additional layers (not shown) at appropriate position(s) within the at least one semiconducting layer 130 stack, including without limitation, a hole blocking layer (not shown), an electron blocking layer (not shown), an additional charge transport layer (not shown) and/or an additional charge injection layer (not shown).

Barrier Coating

In some non-limiting examples, a barrier coating 1650 may be provided to surround and/or encapsulate the first electrode 120, second electrode 140, and the various layers of the at least one semiconducting layer 130 and/or the substrate 110 disposed thereon of the device 100.

In some non-limiting examples, the barrier coating 1650 may be provided to inhibit the various layers 120, 130, 140 of the device 100, including the at least one semiconducting layer 130 and/or the cathode 342 from being exposed to moisture and/or ambient air, since these layers 120, 130, 140 may be prone to oxidation.

In some non-limiting examples, application of the barrier coating 1650 to a highly non-uniform surface may increase a likelihood of poor adhesion of the barrier coating 1650 to such surface.

In some non-limiting examples, the absence of a barrier coating 1650 and/or a poorly-applied barrier coating 1650 may cause and/or contribute to defects in and/or partial and/or total failure of the device 100. In some non-limiting examples, a poorly-applied barrier coating 1650 may reduce adhesion of the barrier coating 1650 to the device 100. In some non-limiting examples, poor adhesion of the barrier coating 1650 may increase a likelihood of the barrier coating 1650 peeling off the device 100 in whole or in part, especially if the device 100 is bent and/or flexed. In some non-limiting examples, a poorly-applied barrier coating 1650 may allow air pockets to be trapped, during application of the barrier coating 1650, between the barrier coating 1650 and an underlying surface of the device 100 to which the barrier coating 1650 was applied.

In some non-limiting examples, the barrier coating 1650 may be a thin film encapsulation (TFE) layer 2050 (FIG. 20B) and may be selectively applied, deposited and/or processed using a variety of techniques, including without limitation, evaporation (including without limitation, thermal evaporation and/or electron beam evaporation), photolithography, printing (including without limitation, ink jet and/or vapor jet printing, reel-to-reel printing and/or micro-contact transfer printing), PVD (including without limitation, sputtering), CVD (including without limitation, PECVD and/or OVPD), laser annealing, LITI patterning, ALD, coating (including without limitation, spin coating, dip coating, line coating and/or spray coating), and/or combinations of any two or more thereof.

In some non-limiting examples, the barrier coating 1650 may be provided by laminating a pre-formed barrier film onto the device 100. In some non-limiting examples, the barrier coating 1650 may comprise a multi-layer coating comprising at least one of an organic material, an inorganic material and/or any combination thereof. In some non-limiting examples, the barrier coating 1550 may further comprise a getter material and/or a desiccant.

Lateral Aspect

In some non-limiting examples, including where the OLED device 100 comprises a lighting panel, an entire lateral aspect of the device 100 may correspond to a single lighting element. As such, the substantially planar cross-sectional profile shown in FIG. 1 may extend substantially along the entire lateral aspect of the device 100, such that photons are emitted from the device 100 substantially along the entirety of the lateral extent thereof. In some non-limiting examples, such single lighting element may be driven by a single driving circuit 300 of the device 100.

In some non-limiting examples, including where the OLED device 100 comprises a display module, the lateral aspect of the device 100 may be sub-divided into a plurality of emissive regions 1910 of the device 100, in which the cross-sectional aspect of the device structure 100, within each of the emissive region(s) 1910 shown, without limitation, in FIG. 1 causes photons to be emitted therefrom when energized.

Emissive Regions

In some non-limiting examples, individual emissive regions 1910 of the device 100 may be laid out in a lateral pattern. In some non-limiting examples, the pattern may extend along a first lateral direction. In some non-limiting examples, the pattern may also extend along a second lateral direction, which in some non-limiting examples, may be substantially normal to the first lateral direction. In some non-limiting examples, the pattern may have a number of elements in such pattern, each element being characterized by one or more features thereof, including without limitation, a wavelength of light emitted by the emissive region 1910 thereof, a shape of such emissive region 1910, a dimension (along either or both of the first and/or second lateral direction(s)), an orientation (relative to either and/or both of the first and/or second lateral direction(s)) and/or a spacing (relative to either or both of the first and/or second lateral direction(s)) from a previous element in the pattern. In some non-limiting examples, the pattern may repeat in either or both of the first and/or second lateral direction(s).

In some non-limiting examples, each individual emissive region 1910 of the device 100 is associated with, and driven by, a corresponding driving circuit 300 within the backplane 20 of the device 100, in which the diode 340 corresponds to the OLED structure for the associated emissive region 1910. In some non-limiting examples, including without limitation, where the emissive regions 1910 are laid out in a regular pattern extending in both the first (row) lateral direction and the second (column) lateral direction, there may be a signal line 30, 31 in the backplane 20, which may be the gate line (or row selection) line 31, corresponding to each row of emissive regions 1910 extending in the first lateral direction and a signal line 30, 31, which may in some non-limiting examples be the data (or column selection) line 30, corresponding to each column of emissive regions 1910 extending in the second lateral direction. In such a non-limiting configuration, a signal on the row selection line 31 may energize the respective gates 312 of the switching TFT(s) 310 electrically coupled thereto and a signal on the data line 30 may energize the respective sources of the switching TFT(s) 310 electrically coupled thereto, such that a signal on a row selection line 31/data line 30 pair will electrically couple and energise, by the positive terminal (represented by the power supply line VDD 32) of the power source 15, the anode 341 of the OLED structure of the emissive region 1910 associated with such pair, causing the emission of a photon therefrom, the cathode 342 thereof being electrically coupled to the negative terminal of the power source 15.

In some non-limiting examples, each emissive region 1910 of the device 100 corresponds to a single display pixel 340. In some non-limiting examples, each pixel 340 emits light at a given wavelength spectrum. In some non-limiting examples, the wavelength spectrum corresponds to a colour in, without limitation, the visible light spectrum.

In some non-limiting examples, each emissive region 1910 of the device 100 corresponds to a sub-pixel 264x of a display pixel 340. In some non-limiting examples, a plurality of sub-pixels 264x may combine to form, or to represent, a single display pixel 340.

In some non-limiting examples, a single display pixel 340 may be represented by three sub-pixels 2641-2643. In some non-limiting examples, the three sub-pixels 2641-2643 may be denoted as, respectively, R(ed) sub-pixels 2641, G(reen) sub-pixels 2642 and/or B(lue) sub-pixels 2643. In some non-limiting examples, a single display pixel 340 may be represented by four sub-pixels 264x, in which three of such sub-pixels 264x may be denoted as R, G and B sub-pixels 2641-2643 and the fourth sub-pixel 264x may be denoted as a W(hite) sub-pixel 264x. In some non-limiting examples, the emission spectrum of the light emitted by a given sub-pixel 264x corresponds to the colour by which the sub-pixel 264x is denoted. In some non-limiting examples, the wavelength of the light does not correspond to such colour but further processing is performed, in a manner apparent to those having ordinary skill in the relevant art, to transform the wavelength to one that does so correspond.

Since the wavelength of sub-pixels 264x of different colours may be different, the optical characteristics of such sub-pixels 264x may differ, especially if a common electrode 120, 140 having a substantially uniform thickness profile is employed for sub-pixels 264x of different colours.

When a common electrode 120, 140 having a substantially uniform thickness is provided as the second electrode 140 in a device 100, the optical performance of the device 100 may not be readily be fine-tuned according to an emission spectrum associated with each (sub-)pixel 340/264x. The second electrode 140 used in such OLED devices 100 may in some non-limiting examples, be a common electrode 120, 140 coating a plurality of (sub-)pixels 340/264x. By way of non-limiting example, such common electrode 120, 140 may be a relatively thin conductive film having a substantially uniform thickness across the device 100. While efforts have been made in some non-limiting examples, to tune the optical microcavity effects associated with each (sub-)pixel 340/264x color by varying a thickness of organic layers disposed within different (sub-)pixel(s) 340/264x, such approach may, in some non-limiting examples, provide a significant degree of tuning of the optical microcavity effects in at least some cases. In addition, in some non-limiting examples, such approach may be difficult to implement in an OLED display production environment.

As a result, the presence of optical interfaces created by numerous thin-film layers and coatings with different refractive indices, such as may in some non-limiting examples be used to construct opto-electronic devices including without limitation OLED devices 100, may create different optical microcavity effects for sub-pixels 264x of different colours.

Some factors that may impact an observed microcavity effect in a device 100 includes, without limitation, the total path length (which in some non-limiting examples may correspond to the total thickness of the device 100 through which photons emitted therefrom will travel before being out-coupled) and the refractive indices of various layers and coatings.

In some non-limiting examples, modulating the thickness of an electrode 120, 140 in and across a lateral aspect 410 of emissive region(s) 1910 of a (sub-)pixel 340/264x may impact the microcavity effect observable. In some non-limiting examples, such impact may be attributable to a change in the total optical path length.

In some non-limiting examples, a change in a thickness of the electrode 120, 140 may also change the refractive index of light passing therethrough, in some non-limiting examples, in addition to a change in the total optical path length. In some non-limiting examples, this may be particularly the case where the electrode 120, 140 is formed of at least one conductive coating 830.

In some non-limiting examples, the optical properties of the device 100, and/or in some non-limiting examples, across the lateral aspect 410 of emissive region(s) 1910 of a (sub-)pixel 340/264x that may be varied by modulating at least one optical microcavity effect, include, without limitation, the emission spectrum, the intensity (including without limitation, luminous intensity) and/or angular distribution of emitted light, including without limitation, an angular dependence of a brightness and/or color shift of the emitted light.

In some non-limiting examples, a sub-pixel 264x is associated with a first set of other sub-pixels 264x to represent a first display pixel 340 and also with a second set of other sub-pixels 264x to represent a second display pixel 340, so that the first and second display pixels 340 may have associated therewith, the same sub-pixel(s) 264x.

The pattern and/or organization of sub-pixels 264x into display pixels 340 continues to develop. All present and future patterns and/or organizations are considered to fall within the scope of the present disclosure.

Non-Emissive Regions

In some non-limiting examples, the various emissive regions 1910 of the device 100 are substantially surrounded and separated by, in at least one lateral direction, one or more non-emissive regions 1920, in which the structure and/or configuration along the cross-sectional aspect, of the device structure 100 shown, without limitation, in FIG. 1, is varied, so as to substantially inhibit photons to be emitted therefrom. In some non-limiting examples, the non-emissive regions 1920 comprise those regions in the lateral aspect, that are substantially devoid of an emissive region 1910.

Thus, as shown in the cross-sectional view of FIG. 4, the lateral topology of the various layers of the at least one semiconducting layer 130 may be varied to define at least one emissive region 1910, surrounded (at least in one lateral direction) by at least one non-emissive region 1920.

In some non-limiting examples, the emissive region 1910 corresponding to a single display (sub-)pixel 340/264x may be understood to have a lateral aspect 410, surrounded in at least one lateral direction by at least one non-emissive region 1920 having a lateral aspect 420.

A non-limiting example of an implementation of the cross-sectional aspect of the device 100 as applied to an emissive region 1910 corresponding to a single display (sub-)pixel 340/264x of an OLED display 100 will now be described. While features of such implementation are shown to be specific to the emissive region 1910, those having ordinary skill in the relevant art will appreciate that in some non-limiting examples, more than one emissive region 1910 may encompass common features.

In some non-limiting examples, the first electrode 120 may be disposed over an exposed layer surface 111 of the device 100, in some non-limiting examples, within at least a part of the lateral aspect 410 of the emissive region 1910. In some non-limiting examples, at least within the lateral aspect 410 of the emissive region 1910 of the (sub-)pixel(s) 340/264x, the exposed layer surface 111, may, at the time of deposition of the first electrode 120, comprise the TFT insulating layer 280 of the various TFT structures 200 that make up the driving circuit 300 for the emissive region 1910 corresponding to a single display (sub-) pixel 340/264x.

In some non-limiting examples, the TFT insulating layer 280 may be formed with an opening 430 extending therethrough to permit the first electrode 120 to be electrically coupled to one of the TFT electrodes 240, 260, 270, including, without limitation, as shown in FIG. 4, the TFT drain electrode 270.

Those having ordinary skill in the relevant art will appreciate that the driving circuit 300 comprises a plurality of TFT structures 200, including without limitation, the switching TFT 310, the driving TFT 320 and/or the storage capacitor 330. In FIG. 4, for purposes of simplicity of illustration, only one TFT structure 200 is shown, but it will be appreciated by those having ordinary skill in the relevant art, that such TFT structure 200 is representative of such plurality thereof that comprise the driving circuit 300.

In a cross-sectional aspect, the configuration of each emissive region 1910 may, in some non-limiting examples, be defined by the introduction of at least one pixel definition layer (PDL) 440 substantially throughout the lateral aspects 420 of the surrounding non-emissive region(s) 1920. In some non-limiting examples, the PDLs 440 may comprise an insulating organic and/or inorganic material.

In some non-limiting examples, the PDLs 440 are deposited substantially over the TFT insulating layer 280, although, as shown, in some non-limiting examples, the PDLs 440 may also extend over at least a part of the deposited first electrode 120 and/or its outer edges.

In some non-limiting examples, as shown in FIG. 4, the cross-sectional thickness and/or profile of the PDLs 440 may impart a substantially valley-shaped configuration to the emissive region 1910 of each (sub-)pixel 340/264x by a region of increased thickness along a boundary of the lateral aspect 420 of the surrounding non-emissive region 1920 with the lateral aspect 410 of the surrounded emissive region 1910, corresponding to a (sub-)pixel 340/264x.

In some non-limiting examples, the profile of the PDLs 440 may have a reduced thickness beyond such valley-shaped configuration, including without limitation, away from the boundary between the lateral aspect 420 of the surrounding non-emissive region 1920 and the lateral aspect 410 of the surrounded emissive region 1910, in some non-limiting examples, substantially well within the lateral aspect 420 of such non-emissive region 1920.

While the PDL(s) 440 have been generally illustrated as having a linearly-sloped surface to form a valley-shaped configuration that define the emissive region(s) 1910 surrounded thereby, those having ordinary skill in the relevant art will appreciate that in some non-limiting examples, at least one of the shape, aspect ratio, thickness, width and/or configuration of such PDL(s) 440 may be varied. By way of non-limiting example, a PDL 440 may be formed with a steeper or more gradually-sloped part. In some non-limiting examples, such PDL(s) 440 may be configured to extend substantially normally away from a surface on which it is deposited, that covers one or more edges of the first electrode 120. In some non-limiting examples, such PDL(s) 440 may be configured to have deposited thereon at least one semiconducting layer 130 by a solution-processing technology, including without limitation, by printing, including without limitation, ink-jet printing.

In some non-limiting examples, the at least one semiconducting layer 130 may be deposited over the exposed layer surface 111 of the device 100, including at least a part of the lateral aspect 410 of such emissive region 1910 of the (sub-)pixel(s) 340/264x. In some non-limiting examples, at least within the lateral aspect 410 of the emissive region 1910 of the (sub-)pixel(s) 340/264x, such exposed layer surface 111, may, at the time of deposition of the at least one semiconducting layer 130 (and/or layers 131, 133, 135, 137, 139 thereof), comprise the first electrode 120.

In some non-limiting examples, the at least one semiconducting layer 130 may also extend beyond the lateral aspect 410 of the emissive region 1910 of the (sub-)pixel(s) 340/264x and at least partially within the lateral aspects 420 of the surrounding non-emissive region(s) 1920. In some non-limiting examples, such exposed layer surface 111 of such surrounding non-emissive region(s) 1920 may, at the time of deposition of the at least one semiconducting layer 130, comprise the PDL(s) 440.

In some non-limiting examples, the second electrode 140 may be disposed over an exposed layer surface 111 of the device 100, including at least a part of the lateral aspect 410 of the emissive region 1910 of the (sub-)pixel(s) 340/264x. In some non-limiting examples, at least within the lateral aspect 410 of the emissive region 1910 of the (sub-)pixel(s) 340/264x, such exposed layer surface 111, may, at the time of deposition of the second electrode 130, comprise the at least one semiconducting layer 130.

In some non-limiting examples, the second electrode 140 may also extend beyond the lateral aspect 410 of the emissive region 1910 of the (sub-) pixel(s) 340/264x and at least partially within the lateral aspects 420 of the surrounding non-emissive region(s) 1920. In some non-limiting examples, such exposed layer surface 111 of such surrounding non-emissive region(s) 1920 may, at the time of deposition of the second electrode 140, comprise the PDL(s) 440.

In some non-limiting examples, the second electrode 140 may extend throughout substantially all or a substantial part of the lateral aspects 420 of the surrounding non-emissive region(s) 1920.

Transmissivity

Because the OLED device 100 emits photons through either or both of the first electrode 120 (in the case of a bottom-emission and/or a double-sided emission device), as well as the substrate 110 and/or the second electrode 140 (in the case of a top-emission and/or double-sided emission device), it may be desirable to make either or both of the first electrode 120 and/or the second electrode 140 substantially photon— (or light)-transmissive (“transmissive”), in some non-limiting examples, at least across a substantial part of the lateral aspect 410 of the emissive region(s) 1910 of the device 100. In the present disclosure, such a transmissive element, including without limitation, an electrode 120, 140, a material from which such element is formed, and/or property thereof, may comprise an element, material and/or property thereof that is substantially transmissive (“transparent”), and/or, in some non-limiting examples, partially transmissive (“semi-transparent”), in some non-limiting examples, in at least one wavelength range.

A variety of mechanisms have been adopted to impart transmissive properties to the device 100, at least across a substantial part of the lateral aspect 410 of the emissive region(s) 1910 thereof.

In some non-limiting examples, including without limitation, where the device 100 is a bottom-emission device and/or a double-sided emission device, the TFT structure(s) 200 of the driving circuit 300 associated with an emissive region 1910 of a (sub-)pixel 340/264x, which may at least partially reduce the transmissivity of the surrounding substrate 110, may be located within the lateral aspect 420 of the surrounding non-emissive region(s) 1920 to avoid impacting the transmissive properties of the substrate 110 within the lateral aspect 410 of the emissive region 1910.

In some non-limiting examples, where the device 100 is a double-sided emission device, in respect of the lateral aspect 410 of an emissive region 1910 of a (sub-)pixel 340/264x, a first one of the electrode 120, 140 may be made substantially transmissive, including without limitation, by at least one of the mechanisms disclosed herein, in respect of the lateral aspect 410 of neighbouring and/or adjacent (sub-)pixel(s) 340/264x, a second one of the electrodes 120, 140 may be made substantially transmissive, including without limitation, by at least one of the mechanisms disclosed herein. Thus, the lateral aspect 410 of a first emissive region 1910 of a (sub-)pixel 340/264x may be made substantially top-emitting while the lateral aspect 410 of a second emissive region 1910 of a neighbouring (sub-)pixel 340/264x may be made substantially bottom-emitting, such that a subset of the (sub-)pixel(s) 340/264x are substantially top-emitting and a subset of the (sub-)pixel(s) 340/264x are substantially bottom-emitting, in an alternating (sub-)pixel 340/264x sequence, while only a single electrode 120, 140 of each (sub-)pixel 340/264x is made substantially transmissive.

In some non-limiting examples, a mechanism to make an electrode 120, 140, in the case of a bottom-emission device and/or a double-sided emission device, the first electrode 120, and/or in the case of a top-emission device and/or a double-sided emission device, the second electrode 140, transmissive is to form such electrode 120, 140 of a transmissive thin film.

In some non-limiting examples, an electrically conductive coating 830, in a thin film, including without limitation, those formed by a depositing a thin conductive film layer of a metal, including without limitation, Ag, Al and/or by depositing a thin layer of a metallic alloy, including without limitation, an Mg:Ag alloy and/or a Yb:Ag alloy, may exhibit transmissive characteristics. In some non-limiting examples, the alloy may comprise a composition ranging from between about 1:9 to about 9:1 by volume. In some non-limiting examples, the electrode 120, 140 may be formed of a plurality of thin conductive film layers of any combination of conductive coatings 830, any one or more of which may be comprised of TCOs, thin metal films, thin metallic alloy films and/or any combination of any of these.

In some non-limiting examples, especially in the case of such thin conductive films, a relatively thin layer thickness may be up to substantially a few tens of nm so as to contribute to enhanced transmissive qualities but also favorable optical properties (including without limitation, reduced microcavity effects) for use in an OLED device 100.

In some non-limiting examples, a reduction in the thickness of an electrode 120, 140 to promote transmissive qualities may be accompanied by an increase in the sheet resistance of the electrode 120, 140.

In some non-limiting examples, a device 100 having at least one electrode 120, 140 with a high sheet resistance creates a large current-resistance (IR) drop when coupled to the power source 15, in operation. In some non-limiting examples, such an IR drop may be compensated for, to some extent, by increasing a level (VDD) of the power source 15. However, in some non-limiting examples, increasing the level of the power source 15 to compensate for the IR drop due to high sheet resistance, for at least one (sub-)pixel 340/264x may call for increasing the level of a voltage to be supplied to other components to maintain effective operation of the device 100.

In some non-limiting examples, to reduce power supply demands for a device 100 without significantly impacting an ability to make an electrode 120, 140 substantially transmissive (by employing at least one thin film layer of any combination of TCOs, thin metal films and/or thin metallic alloy films), an auxiliary electrode 1750 and/or busbar structure 4150 may be formed on the device 100 to allow current to be carried more effectively to various emissive region(s) of the device 100, while at the same time, reducing the sheet resistance and its associated IR drop of the transmissive electrode 120, 140.

In some non-limiting examples, a sheet resistance specification, for a common electrode 120, 140 of an AMOLED display device 100, may vary according to a number of parameters, including without limitation, a (panel) size of the device 100 and/or a tolerance for voltage variation across the device 100. In some non-limiting examples, the sheet resistance specification may increase (that is, a lower sheet resistance is specified) as the panel size increases. In some non-limiting examples, the sheet resistance specification may increase as the tolerance for voltage variation decreases.

In some non-limiting examples, a sheet resistance specification may be used to derive an example thickness of an auxiliary electrode 1750 and/or a busbar 4150 to comply with such specification for various panel sizes. In one non-limiting example, an aperture ratio of 0.64 was assumed for all display panel sizes and a thickness of the auxiliary electrode 1750 for various example panel sizes were calculated for example voltage tolerances of 0.1 V and 0.2 V in Table 1 below.

TABLE 1
Example Auxiliary Electrode Thickness for
Various Panel Size and Voltage Tolerances
Panel Size (in.)	9.7	12.9	15.4	27	65
Specified Thickness (nm)	@0.1 V	132	239	335	1200	6500
	@0.2 V	67	117	175	516	21000

By way of non-limiting example, for a top-emission device, the second electrode 140 may be made transmissive. On the other hand, in some non-limiting examples, such auxiliary electrode 1750 and/or busbar 4150 may not be substantially transmissive but may be electrically coupled to the second electrode 140, including without limitation, by deposition of a conductive coating 830 therebetween, to reduce an effective sheet resistance of the second electrode 140.

In some non-limiting examples, such auxiliary electrode 1750 may be positioned and/or shaped in either or both of a lateral aspect and/or cross-sectional aspect so as not to interfere with the emission of photons from the lateral aspect 410 of the emissive region 1910 of a (sub-)pixel 340/264x.

In some non-limiting examples, a mechanism to make the first electrode 120, and/or the second electrode 140, is to form such electrode 120, 140 in a pattern across at least a part of the lateral aspect 410 of the emissive region(s) 1910 thereof and/or in some non-limiting examples, across at least a part of the lateral aspect 420 of the non-emissive region(s) 1920 surrounding them. In some non-limiting examples, such mechanism may be employed to form the auxiliary electrode 1750 and/or busbar 4150 in a position and/or shape in either or both of a lateral aspect and/or cross-sectional aspect so as not to interfere with the emission of photons from the lateral aspect 410 of the emissive region 1910 of a (sub-)pixel 340/264x, as discussed above.

In some non-limiting examples, the device 100 may be configured such that it is substantially devoid of a conductive oxide material in an optical path of photons emitted by the device 100. By way of non-limiting example, in the lateral aspect 410 of at least one emissive region 1910 corresponding to a (sub-)pixel 340/264x, at least one of the layers and/or coatings deposited after the at least one semiconducting layer 130, including without limitation, the second electrode 140, the NIC 810 and/or any other layers and/or coatings deposited thereon, may be substantially devoid of any conductive oxide material. In some non-limiting examples, being substantially devoid of any conductive oxide material may reduce absorption and/or reflection of light emitted by the device 100. By way of non-limiting example, conductive oxide materials, including without limitation, ITO and/or IZO, may absorb light in at least the B(lue) region of the visible spectrum, which may, in generally, reduce efficiency and/or performance of the device 100.

In some non-limiting examples, a combination of these and/or other mechanisms may be employed.

Additionally, in some non-limiting examples, in addition to rendering one or more of the first electrode 120, the second electrode 140, the auxiliary electrode 1750 and/or the busbar 4150, substantially transmissive across at least across a substantial part of the lateral aspect 410 of the emissive region 1910 corresponding to the (sub-)pixel(s) 340/264x of the device 100, in order to allow photons to be emitted substantially across the lateral aspect 410 thereof, it may be desired to make at least one of the lateral aspect(s) 420 of the surrounding non-emissive region(s) 1920 of the device 100 substantially transmissive in both the bottom and top directions, so as to render the device 100 substantially transmissive relative to light incident on an external surface thereof, such that a substantial part such externally-incident light may be transmitted through the device 100, in addition to the emission (in a top-emission, bottom-emission and/or double-sided emission) of photons generated internally within the device 100 as disclosed herein.

Conductive Coating

In some non-limiting examples, a conductive coating material 831 (FIG. 9) used to deposit a conductive coating 830 onto an exposed layer surface 111 of underlying material may be a mixture.

In some non-limiting examples, at least one component of such mixture is not deposited on such surface, may not be deposited on such exposed layer surface 111 during deposition and/or may be deposited in a small amount relative to an amount of remaining component(s) of such mixture that are deposited on such exposed layer surface 111.

In some non-limiting examples, such at least one component of such mixture may have a property relative to the remaining component(s) to selectively deposit substantially only the remaining component(s). In some non-limiting examples, the property may be a vapor pressure.

In some non-limiting examples, such at least one component of such mixture may have a lower vapor pressure relative to the remaining components.

In some non-limiting examples, the conductive coating material 831 may be a copper (Cu)-magnesium (Cu—Mg) mixture, in which Cu has a lower vapor pressure than Mg.

In some non-limiting examples, the conductive coating material 831 used to deposit a conductive coating 830 onto an exposed layer surface 111 may be substantially pure.

In some non-limiting examples, the conductive coating material 831 used to deposit Mg is and in some non-limiting examples, comprises substantially pure Mg. In some non-limiting examples, substantially pure Mg may exhibit substantially similar properties relative to pure Mg. In some non-limiting examples, purity of Mg may be about 95% or higher, about 98% or higher, about 99% or higher, about 99.9% or higher and/or about 99.99% and higher.

In some non-limiting examples, a conductive coating material 831 used to deposit a conductive coating 830 onto an exposed layer surface 111 may comprise other metals in place of and/or in combination of Mg. In some non-limiting examples, a conductive coating material 831 comprising such other metals may include high vapor pressure materials, including without limitation, Yb, Cd, Zn and/or any combination of any of these.

In some non-limiting examples, a conductive coating 830 in an opto-electronic device according to various example includes Mg. In some non-limiting examples, the conductive coating 830 comprises substantially pure Mg. In some non-limiting examples, the conductive coating 830 includes other metals in place of and/or in combination with Mg. In some non-limiting examples, the conductive coating 830 includes an alloy of Mg with one or more other metals. In some non-limiting examples, the conductive coating 830 includes an alloy of Mg with Yb, Cd, Zn, and/or Ag. In some non-limiting examples, such alloy may be a binary alloy having a composition ranging from between about 5 vol. % Mg and about 95 vol. % Mg, with the remainder being the other metal. In some non-limiting examples, the conductive coating 830 includes a Mg:Ag alloy having a composition ranging from between about 1:10 to about 10:1 by volume.

Patterning

As a result of the foregoing, it may be desirable to selectively deposit, across the lateral aspect 410 of the emissive region 1910 of a (sub-)pixel 340/264x and/or the lateral aspect 420 of the non-emissive region(s) 1920 surrounding the emissive region 1910, a device feature, including without limitation, at least one of the first electrode 120, the second electrode 140, the auxiliary electrode 1750 and/or busbar 4150 and/or a conductive element electrically coupled thereto, in a pattern, on an exposed layer surface 111 of a frontplane 10 layer of the device 100. In some non-limiting examples, the first electrode 120, the second electrode 140, the auxiliary electrode 1750 and/or the busbar 4150 may be deposited in at least one of a plurality of conductive coatings 830.

However, it may not be feasible to employ a shadow mask such as a fine metal mask (FMM) that may, in some non-limiting examples, be used to form relatively small features, with a feature size on the order of tens of microns or smaller to achieve such patterning of a conductive coating 830, since, in some non-limiting examples:

• • an FMM may be deformed during a deposition process, especially at high temperatures, such as may be employed for deposition of a thin conductive film;
  • limitations on the mechanical (including, without limitation, tensile) strength of the FMM and/or shadowing effects, especially in a high-temperature deposition process, may impart a constraint on an aspect ratio of features that may be achievable using such FMMs;
  • the type and number of patterns that may be achievable using such FMMs may be constrained since, by way of non-limiting example, each part of the FMM will be physically supported so that, in some non-limiting examples, some patterns may not be achievable in a single processing stage, including by way of non-limiting example, where a pattern specifies an isolated feature;
  • FMMs may exhibit a tendency to warp during a high-temperature deposition process, which may, in some non-limiting examples, distort the shape and position of apertures therein, which may cause the selective deposition pattern to be varied, with a degradation in performance and/or yield;
  • FMMs that may be used to produce repeating structures spread across the entire surface of a device 100, may call for a large number of apertures to be formed in the FMM, which may compromise the structural integrity of the FMM;
  • repeated use of FMMs in successive depositions, especially in a metal deposition process, may cause the deposited material to adhere thereto, which may obfuscate features of the FMM and which may cause the selective deposition pattern to be varied, with a degradation in performance and/or yield;
  • while FMMs may be periodically cleaned to remove adhered non-metallic material, such cleaning procedures may not be suitable for use with adhered metal, and even so, in some non-limiting examples, may be time-consuming and/or expensive; and
  • irrespective of any such cleaning processes, continued use of such FMMs, especially in a high-temperature deposition process, may render them ineffective at producing a desired patterning, at which point they may be discarded and/or replaced, in a complex and expensive process.

FIG. 5 shows an example cross-sectional view of a device 500 that is substantially similar to the device 100, but further comprises a plurality of raised PDLs 440 across the lateral aspect(s) 420 of non-emissive regions 1920 surrounding the lateral aspect(s) 410 of emissive region(s) 1910 corresponding to (sub-)pixel(s) 340/264x.

When the conductive coating 830 is deposited, in some non-limiting examples, using an open-mask and/or a mask-free deposition process, the conductive coating 830 is deposited across the lateral aspect(s) 410 of emissive region(s) 1910 corresponding to (sub-)pixel(s) 340/264x to form (in the FIGURE) the second electrode 140 thereon, and also across the lateral aspect(s) 420 of non-emissive regions 1920 surrounding them, to form regions of conductive coating 830 on top of the PDLs 440. To ensure that each (segment) of the second electrode 140 is not electrically coupled to any of the at least one conductive region(s) 830, a thickness of the PDL(s) 440 is greater than a thickness of the second electrode(s) 140. In some non-limiting examples, the PDL(s) 440 may be provided, as shown in the FIGURE, with an undercut profile to further decrease a likelihood that any (segment) of the second electrode(s) 140 will be electrically coupled to any of the at least one conductive region(s) 830.

In some non-limiting examples, application of a barrier coating 1650 over the device 500 may result in poor adhesion of the barrier coating 1650 to the device 500, having regard to the highly non-uniform surface topography of the device 500.

In some non-limiting examples, it may be desirable to tune optical microcavity effects associated with sub-pixel(s) 264x of different colours (and/or wavelengths) by varying a thickness of the at least one semiconducting layer 130 (and/or a layer thereof) across the lateral aspect 410 of emissive region(s) 1910 corresponding to sub-pixel(s) 264x of one colour relative to the lateral aspect 410 of emissive region(s) 1910 corresponding to sub-pixel(s) 264x of another colour. In some non-limiting examples, the use of FMMs to perform patterning may not provide a precision called for to provide such optical microcavity tuning effects in at least some cases and/or, in some non-limiting examples, in a production environment for OLED displays 100.

Nucleation-Inhibiting and/or Promoting Material Properties

In some non-limiting examples, a conductive coating 830, that may be employed as, or as at least one of a plurality of layers of thin conductive films to form a device feature, including without limitation, at least one of the first electrode 120, the first electrode 140, an auxiliary electrode 1750 and/or a busbar 4150 and/or a conductive element electrically coupled thereto, may exhibit a relatively low affinity towards being deposited on an exposed layer surface 111 of an underlying material, so that the deposition of the conductive coating 830 is inhibited.

The relative affinity or lack thereof of a material and/or a property thereof to having a conductive coating 830 deposited thereon may be referred to as being “nucleation-promoting” or “nucleation-inhibiting” respectively.

In the present disclosure, “nucleation-inhibiting” refers to a coating, material and/or a layer thereof that has a surface that exhibits a relatively low affinity for (deposition of) a conductive coating 830 thereon, such that the deposition of the conductive coating 830 on such surface is inhibited.

In the present disclosure, “nucleation-promoting” refers to a coating, material and/or a layer thereof that has a surface that exhibits a relatively high affinity for (deposition of) a conductive coating 830 thereon, such that the deposition of the conductive coating 830 on such surface is facilitated.

The term “nucleation” in these terms references the nucleation stage of a thin film formation process, in which monomers in a vapor phase condense onto the surface to form nuclei.

Without wishing to be bound by a particular theory, it is postulated that the shapes and sizes of such nuclei and the subsequent growth of such nuclei into islands and thereafter into a thin film may depend upon a number of factors, including without limitation, interfacial tensions between the vapor, the surface and/or the condensed film nuclei.

In the present disclosure, such affinity may be measured in a number of fashions.

One measure of a nucleation-inhibiting and/or nucleation-promoting property of a surface is the initial sticking probability S₀ of the surface for a given electrically conductive material, including without limitation, Mg. In the present disclosure, the terms “sticking probability” and “sticking coefficient” may be used interchangeably.

In some non-limiting examples, the sticking probability S may be given by:

$S=\frac{N_{ads}}{N_{total}}$ where N_ads is a number of adsorbed monomers (“adatoms”) that remain on an exposed layer surface 111 (that is, are incorporated into a film) and N_total is a total number of impinging monomers on the surface. A sticking probability S equal to 1 indicates that all monomers that impinge on the surface are adsorbed and subsequently incorporated into a growing film. A sticking probability S equal to 0 indicates that all monomers that impinge on the surface are desorbed and subsequently no film is formed on the surface. A sticking probability S of metals on various surface can be evaluated using various techniques of measuring the sticking probability S, including without limitation, a dual quartz crystal microbalance (QCM) technique as described by Walker et al., J. Phys. Chem. C 2007, 111, 765 (2006).

As the density of islands increases (e.g., increasing average film thickness), a sticking probability S may change. By way of non-limiting example, a low initial sticking probability S₀ may increase with increasing average film thickness. This can be understood based on a difference in sticking probability S between an area of a surface with no islands, by way of non-limiting example, a bare substrate 110, and an area with a high density of islands. By way of non-limiting example, a monomer that impinges on a surface of an island may have a sticking probability S that approaches 1.

An initial sticking probability S₀ may therefore be specified as a sticking probability S of a surface prior to the formation of any significant number of critical nuclei. One measure of an initial sticking probability S₀ can involve a sticking probability S of a surface for a material during an initial stage of deposition of the material, where an average thickness of the deposited material across the surface is at or below a threshold value. In the description of some non-limiting examples a threshold value for an initial sticking probability S₀ can be specified as, by way of non-limiting example, 1 nm. An average sticking probability S may then be given by:

$\stackrel{\_}{S}=S_0\left(1-A_{nuc}\right)+S_{nuc}\left(A_{nuc}\right)$ where S_nuc is a sticking probability S of an area covered by islands, and A_nuc is a percentage of an area of a substrate surface covered by islands.

An example of an energy profile of an adatom adsorbed onto an exposed layer surface 111 of an underlying material (in the FIGURE, the substrate 110) is illustrated in FIG. 6. Specifically, FIG. 6 illustrates example qualitative energy profiles corresponding to: an adatom escaping from a local low energy site (610); diffusion of the adatom on the exposed layer surface 111 (620); and desorption of the adatom (630).

In 610, the local low energy site may be any site on the exposed layer surface 111 of an underlying material, onto which an adatom will be at a lower energy. Typically, the nucleation site may comprise a defect and/or an anomaly on the exposed layer surface 111, including without limitation, a step edge, a chemical impurity, a bonding site and/or a kink. Once the adatom is trapped at the local low energy site, there may in some non-limiting examples, typically be an energy barrier before surface diffusion takes place. Such energy barrier is represented as ΔE 611 in FIG. 6. In some non-limiting examples, if the energy barrier ΔE 611 to escape the local low energy site is sufficiently large, the site may act as a nucleation site.

In 620, the adatom may diffuse on the exposed layer surface 111. By way of non-limiting example, in the case of localized absorbates, adatoms tend to oscillate near a minimum of the surface potential and migrate to various neighboring sites until the adatom is either desorbed, and/or is incorporated into a growing film and/or growing islands formed by a cluster of adatoms. In FIG. 6, the activation energy associated with surface diffusion of adatoms is represented as E_s 621.

In 630, the activation energy associated with desorption of the adatom from the surface is represented as E_des 631. Those having ordinary skill in the relevant art will appreciate that any adatoms that are not desorbed may remain on the exposed layer surface 111. By way of non-limiting example, such adatoms may diffuse on the exposed layer surface 111, be incorporated as part of a growing film and/or coating, and/or become part of a cluster of adatoms that form islands on the exposed layer surface 111.

Based on the energy profiles 610, 620, 630 shown in FIG. 6, it may be postulated that NIC 810 materials exhibiting relatively low activation energy for desorption (E_des 631) and/or relatively high activation energy for surface diffusion (E_s 631) may be particularly advantageous for use in various applications.

One measure of a nucleation-inhibiting and/or nucleation-promoting property of a surface is an initial deposition rate of a given electrically conductive material, including without limitation, Mg, on the surface, relative to an initial deposition rate of the same conductive material on a reference surface, where both surfaces are subjected to and/or exposed to an evaporation flux of the conductive material.

Selective Coatings for Impacting Nucleation-Inhibiting and/or Promoting Material Properties

In some non-limiting examples, one or more selective coatings 710 (FIG. 7) may be selectively deposited on at least a first portion 701 (FIG. 7) of an exposed layer surface 111 of an underlying material to be presented for deposition of a thin film conductive coating 830 thereon. Such selective coating(s) 710 have a nucleation-inhibiting property (and/or conversely a nucleation-promoting property) with respect to the conductive coating 830 that differs from that of the exposed layer surface 111 of the underlying material. In some non-limiting examples, there may be a second portion 702 (FIG. 7) of the exposed layer surface 111 of an underlying material to which no such selective coating(s) 710, has been deposited.

Such a selective coating 710 may be an NIC 810 and/or a nucleation promoting coating (NPC 1120 (FIG. 11)).

It will be appreciated by those having ordinary skill in the relevant art that the use of such a selective coating 710 may, in some non-limiting examples, facilitate and/or permit the selective deposition of the conductive coating 830 without employing an FMM during the stage of depositing the conductive coating 830.

In some non-limiting examples, such selective deposition of the conductive coating 830 may be in a pattern. In some non-limiting examples, such pattern may facilitate providing and/or increasing transmissivity of at least one of the top and/or bottom of the device 100, within the lateral aspect 410 of one or more emissive region(s) 1910 of a (sub-)pixel 340/264x and/or within the lateral aspect 420 of one or more non-emissive region(s) 1920 that may, in some non-limiting examples, surround such emissive region(s) 1910.

In some non-limiting examples, the conductive coating 830 may be deposited on a conductive structure and/or in some non-limiting examples, form a layer thereof, for the device 100, which in some non-limiting examples may be the first electrode 120 and/or the second electrode 140 to act as one of an anode 341 and/or a cathode 342, and/or an auxiliary electrode 1750 and/or busbar 4150 to support conductivity thereof and/or in some non-limiting examples, be electrically coupled thereto.

In some non-limiting examples, an NIC 810 for a given conductive coating 830, including without limitation Mg, may refer to a coating having a surface that exhibits a relatively low initial sticking probability S₀ for the conductive coating 830 (in the example Mg) in vapor form, such that deposition of the conductive coating 830 (in the example Mg) onto the exposed layer surface 111 is inhibited. Thus, in some non-limiting examples, selective deposition of an NIC 810 may reduce an initial sticking probability S₀ of an exposed layer surface 111 (of the NIC 810) presented for deposition of the conductive coating 830 thereon.

In some non-limiting examples, an NPC 1120, for a given conductive coating 830, including without limitation Mg, may refer to a coating having an exposed layer surface 111 that exhibits a relatively high initial sticking probability S₀ for the conductive coating 830 in vapor form, such that deposition of the conductive coating 830 onto the exposed layer surface 111 is facilitated. Thus, in some non-limiting examples, selective deposition of an NPC 1120 may increase an initial sticking probability S₀ of an exposed layer surface 111 (of the NPC 1120) presented for deposition of the conductive coating 830 thereon.

When the selective coating 710 is an NIC 810, the first portion 701 of the exposed layer surface 111 of the underlying material, upon which the NIC 810 is deposited, will thereafter present a treated surface (of the NIC 810) whose nucleation-inhibiting property has been increased or alternatively, whose nucleation-promoting property has been reduced (in either case, the surface of the NIC 810 deposited on the first portion 701), such that it has a reduced affinity for deposition of the conductive coating 830 thereon relative to that of the exposed layer surface 111 of the underlying material upon which the NIC 810 has been deposited. By contrast the second portion 702, upon which no such NIC 810 has been deposited, will continue to present an exposed layer surface 111 (of the underlying substrate 110) whose nucleation-inhibiting property or alternatively, whose nucleation-promoting property (in either case, the exposed layer surface 111 of the underlying substrate 110 that is substantially devoid of the selective coating 710), has an affinity for deposition of the conductive coating 830 thereon that has not been substantially altered.

When the selective coating 710 is an NPC 1120, the first portion 701 of the exposed layer surface 111 of the underlying material, upon which the NPC 1120 is deposited, will thereafter present a treated surface (of the NPC 1120) whose nucleation-inhibiting property has been reduced or alternatively, whose nucleation-promoting property has been increased (in either case, the surface of the NPC 1120 deposited on the first portion 701), such that it has an increased affinity for deposition of the conductive coating 830 thereon relative to that of the exposed layer surface 111 of the underlying material upon which the NPC 1120 has been deposited. By contrast, the second portion 702, upon which no such NPC 1120 has been deposited, will continue to present an exposed layer surface 111 (of the underlying substrate 110) whose nucleation-inhibiting property or alternatively, whose nucleation-promoting property (in either case, the exposed layer surface 111 of the underlying substrate 110 that is substantially devoid of the NPC 1120), has an affinity for deposition of the conductive coating 830 thereon that has not been substantially altered.

In some non-limiting examples, both an NIC 810 and an NPC 1120 may be selectively deposited on respective first portions 701 and NPC portions 1103 (FIG. 11A) of an exposed layer surface 111 of an underlying material to respectively alter a nucleation-inhibiting property (and/or conversely a nucleation-promoting property) of the exposed layer surface 111 to be presented for deposition of a conductive coating 830 thereon. In some non-limiting examples, there may be a second portion 702 of the exposed layer surface 111 of an underlying material to which no selective coating 710 has been deposited, such that the nucleation-inhibiting property (and/or conversely its nucleation-promoting property) to be presented for deposition of the conductive coating 830 thereon is not substantially altered.

In some non-limiting examples, the first portion 701 and NPC portion 1103 may overlap, such that a first coating of an NIC 810 and/or an NPC 1120 may be selectively deposited on the exposed layer surface 111 of the underlying material in such overlapping region and the second coating of the NIC 810 and/or the NPC 1120 may be selectively deposited on the treated exposed layer surface 111 of the first coating. In some non-limiting examples, the first coating is an NIC 810. In some non-limiting examples, the first coating is an NPC 1120.

In some non-limiting examples, the first portion 701 (and/or NPC portion 1103) to which the selective coating 710 has been deposited, may comprise a removal region, in which the deposited selective coating 710 has been removed, to present the uncovered surface of the underlying material for deposition of the conductive coating 830 thereon, such that the nucleation-inhibiting property (and/or conversely its nucleation-promoting property) to be presented for deposition of the conductive coating 830 thereon is not substantially altered.

In some non-limiting examples, the underlying material may be at least one layer selected from the substrate 110 and/or at least one of the frontplane 10 layers, including without limitation, the first electrode 120, the second electrode 140, the at least one semiconducting layer 130 (and/or at least one of the layers thereof) and/or any combination of any of these.

In some non-limiting examples, the conductive coating 830 may have specific material properties. In some non-limiting examples, the conductive coating 830 may comprise Mg, whether alone or in a compound and/or alloy.

By way of non-limiting example, pure and/or substantially pure Mg may not be readily deposited onto some organic surfaces due to a low sticking probability S of Mg on some organic surfaces.

Deposition of Selective Coatings

In some non-limiting examples, a thin film comprising the selective coating 710, may be selectively deposited and/or processed using a variety of techniques, including without limitation, evaporation (including without limitation), thermal evaporation and/or electron beam evaporation), photolithography, printing (including without limitation, ink jet and/or vapor jet printing, reel-to-reel printing and/or micro-contact transfer printing), PVD (including without limitation, sputtering), CVD (including without limitation, PECVD and/or OVPD), laser annealing, LITI patterning, ALD, coating (including without limitation, spin coating, dip coating, line coating and/or spray coating), and/or combinations of any two or more thereof.

FIG. 7 is an example schematic diagram illustrating a non-limiting example of an evaporative process, shown generally at 700, in a chamber 70, for selectively depositing a selective coating 710 onto a first portion 701 of an exposed layer surface 111 of an underlying material (in the FIGURE, for purposes of simplicity of illustration only, the substrate 110).

In the process 700, a quantity of a selective coating material 711, is heated under vacuum, to evaporate and/or sublime 712 the selective coating material 711. In some non-limiting examples, the selective coating material 711 comprises entirely, and/or substantially, a material used to form the selective coating 710. Evaporated selective coating material 712 is directed through the chamber 70, including in a direction indicated by arrow 71, toward the exposed layer surface 111. When the evaporated selective coating material 712 is incident on the exposed layer surface 111, that is, in the first portion 701, the selective coating 710 is formed thereon.

In some non-limiting examples, as shown in the FIGURE for the process 700, the selective coating 710 may be selectively deposited only onto a portion, in the example illustrated, the first portion 701, of the exposed layer surface 111, by the interposition, between the selective coating material 711 and the exposed layer surface 111, of a shadow mask 715, which in some non-limiting examples, may be an FMM. The shadow mask 715 has at least one aperture 716 extending therethrough such that a part of the evaporated selective coating material 712 passes through the aperture 716 and is incident on the exposed layer surface 111 to form the selective coating 710. Where the evaporated selective coating material 712 does not pass through the aperture 716 but is incident on the surface 717 of the shadow mask 715, it is precluded from being disposed on the exposed layer surface 111 to form the selective coating 710 within the second portion 703. The second portion 702 of the exposed layer surface 111 is thus substantially devoid of the selective coating 710. In some non-limiting examples (not shown), the selective coating material 711 that is incident on the shadow mask 715 may be deposited on the surface 717 thereof.

Accordingly, a patterned surface is produced upon completion of the deposition of the selective coating 710.

In some non-limiting examples, for purposes of simplicity of illustration, the selective coating 710 employed in FIG. 7 may be an NIC 810. In some non-limiting examples, for purposes of simplicity of illustration, the selective coating 710 employed in FIG. 7 may be an NPC 1120.

FIG. 8 is an example schematic diagram illustrating a non-limiting example of a result of an evaporative process, shown generally at 800, in a chamber 70, for selectively depositing a conductive coating 830 onto a second portion 702 of an exposed layer surface 111 of an underlying material (in the FIGURE, for purposes of simplicity of illustration only, the substrate 110) that is substantially devoid of the NIC 810 that was selectively deposited onto a first portion 701, including without limitation, by the evaporative process 700 of FIG. 7. In some non-limiting examples, the second portion 702 comprises that part of the exposed layer surface 111 that lies beyond the first portion 701.

Once the NIC 810 has been deposited on a first portion 701 of an exposed layer surface 111 of an underlying material (in the FIGURE, the substrate 110), the conductive coating 830 may be deposited on the second portion 702 of the exposed layer surface 111 that is substantially devoid of the NIC 810.

In the process 800, a quantity of a conductive coating material 831, is heated under vacuum, to evaporate and/or sublime 832 the conductive coating material 831. In some non-limiting examples, the conductive coating material 831 comprises entirely, and/or substantially, a material used to form the conductive coating 830. Evaporated conductive coating material 832 is directed inside the chamber 70, including in a direction indicated by arrow 81, toward the exposed layer surface 111 of the first portion 701 and of the second portion 702. When the evaporated conductive coating material 832 is incident on the second portion 702 of the exposed layer surface 111, the conductive coating 830 is formed thereon.

In some non-limiting examples, deposition of the conductive coating material 831 may be performed using an open mask and/or mask-free deposition process, such that the conductive coating 830 is formed substantially across the entire exposed layer surface 111 of the underlying material (in the FIGURE, the substrate 110) to produce a treated surface (of the conductive coating 830).

It will be appreciated by those having ordinary skill in the relevant art that, contrary to that of an FMM, the feature size of an open mask is generally comparable to the size of a device 100 being manufactured. In some non-limiting examples, such an open mask may have an aperture that may generally correspond to a size of the device 100, which in some non-limiting examples, may correspond, without limitation, to about 1 inch for micro-displays, about 4-6 inches for mobile displays, and/or about 8-17 inches for laptop and/or tablet displays, so as to mask edges of such device 100 during manufacturing. In some non-limiting examples, the feature size of an open mask may be on the order of about 1 cm and/or greater. In some non-limiting examples, an aperture formed in an open mask may in some non-limiting examples be sized to encompass the lateral aspect(s) 410 of a plurality of emissive regions 1910 each corresponding to a (sub-) pixel 340/264x and/or surrounding and/or the lateral aspect(s) 420 of surrounding and/or intervening non-emissive region(s) 1920.

It will be appreciated by those having ordinary skill in the relevant art that, in some non-limiting examples, the use of an open mask may be omitted, if desired. In some non-limiting examples, an open mask deposition process described herein may alternatively be conducted without the use of an open mask, such that an entire target exposed layer surface 111 may be exposed.

In some non-limiting examples, as shown in the FIGURE for the process 800, deposition of the conductive coating 830 may be performed using an open mask and/or mask-free deposition process, such that the conductive coating 830 is formed substantially across the entire exposed layer surface 111 of the underlying material (in the FIGURE, of the substrate 110) to produce a treated surface (of the conductive coating 830).

Indeed, as shown in FIG. 8, the evaporated conductive coating material 832 is incident both on an exposed layer surface 111 of NIC 810 across the first portion 701 as well as the exposed layer surface 111 of the substrate 110 across the second portion 702 that is substantially devoid of NIC 810.

Since the exposed layer surface 111 of the NIC 810 in the first portion 701 exhibits a relatively low initial sticking probability S₀ for the conductive coating 830 compared to the exposed layer surface 111 of the substrate 110 in the second portion 702, the conductive coating 830 is selectively deposited substantially only on the exposed layer surface 111 of the substrate 110 in the second portion 702 that is substantially devoid of the NIC 810. By contrast, the evaporated conductive coating material 832 incident on the exposed layer surface 111 of NIC 810 across the first portion 701 tends not to be deposited, as shown (833) and the exposed layer surface 111 of NIC 810 across the first portion 701 is substantially devoid of the conductive coating 830.

In some non-limiting examples, an initial deposition rate of the evaporated conductive coating material 832 on the exposed layer surface 111 of the substrate 110 in the second portion 702 may be at least and/or greater than about 200 times, at least and/or greater than about 550 times, at least and/or greater than about 900 times, at least and/or greater than about 1,000 times, at least and/or greater than about 1,500 times, at least and/or greater than about 1,900 times and/or at least and/or greater than about 2,000 times an initial deposition rate of the evaporated conductive coating material 832 on the exposed layer surface 111 of the NIC 810 in the first portion 701.

The foregoing may be combined in order to effect the selective deposition of at least one conductive coating 830 to form a device feature, including without limitation, a patterned electrode 120, 140, 1750, 4150 and/or a conductive element electrically coupled thereto, without employing an FMM within the conductive coating 830 deposition process. In some non-limiting examples, such patterning may permit and/or enhance the transmissivity of the device 100.

In some non-limiting examples, the selective coating 710, which may be an NIC 810 and/or an NPC 1120 may be applied a plurality of times during the manufacturing process of the device 100, in order to pattern a plurality of electrodes 120, 140, 1750, 4150 and/or various layers thereof and/or a device feature comprising a conductive coating 830 electrically coupled thereto.

FIGS. 9A-9D illustrate non-limiting examples of open masks.

FIG. 9A illustrates a non-limiting example of an open mask 900 having and/or defining an aperture 910 formed therein. In some non-limiting examples, such as shown, the aperture 910 of the open mask 900 is smaller than a size of a device 100, such that when the mask 900 is overlaid on the device 100, the mask 900 covers edges of the device 100. In some non-limiting examples, as shown, the lateral aspect(s) 410 of the emissive regions 1910 corresponding to all and/or substantially all of the (sub-)pixel(s) 340/264x of the device 100 are exposed through the aperture 910, while an unexposed region 920 is formed between outer edges 91 of the device 100 and the aperture 910. It will be appreciated by those having ordinary skill in the relevant art that, in some non-limiting examples, electrical contacts and/or other components (not shown) of the device 100 may be located in such unexposed region 920, such that these components remain substantially unaffected throughout an open mask deposition process.

FIG. 9B illustrates a non-limiting example of an open mask 901 having and/or defining an aperture 911 formed therein that is smaller than the aperture 910 of FIG. 9A, such that when the mask 901 is overlaid on the device 100, the mask 901 covers at least the lateral aspect(s) 410a of the emissive region(s) 1910 corresponding to at least some (sub-)pixel(s) 340/264x. As shown, in some non-limiting examples, the lateral aspect(s) 410a of the emissive region(s) 1910 corresponding to outermost (sub-)pixel(s) 340/264x are located within an unexposed region 913 of the device 100, formed between the outer edges 91 of the device 100 and the aperture 911, are masked during an open mask deposition process to inhibit evaporated conductive coating material 832 from being incident on the unexposed region 913.

FIG. 9C illustrates a non-limiting example of an open mask 902 having and/or defining an aperture 912 formed therein defines a pattern that covers the lateral aspect(s) 410a of the emissive region(s) 1910 corresponding to at least some (sub-)pixel(s) 340/264x, while exposing the lateral aspect(s) 410b of the emissive region(s) 1910 corresponding to at least some (sub-)pixel(s) 340/264x. As shown, in some non-limiting examples, the lateral aspect(s) 410a of the emissive region(s) 1910 corresponding to at least some (sub-)pixel(s) 340/264x located within an unexposed region 914 of the device 100, are masked during an open mask deposition process to inhibit evaporated conductive coating material 830 from being incident on the unexposed region 914.

While in FIGS. 9B-9C, the lateral aspects 410a of the emissive region(s) 1910 corresponding to at least some of the outermost (sub-)pixel(s) 340/264x have been masked, as illustrated, those having ordinary skill in the relevant art will appreciate that, in some non-limiting examples, an aperture of an open mask 900-902 may be shaped to mask the lateral aspects 410 of other emissive region(s) 1910 and/or the lateral aspects 420 of non-emissive region(s) 1920 of the device 100.

Furthermore, while FIGS. 9A-9C show open masks 900-902 having a single aperture 910-912, those having ordinary skill in the relevant art will appreciate that such open masks 900-902 may, in some non-limiting examples (not shown), additional apertures (not shown) for exposing multiple regions of an exposed layer surface 111 of an underlying material of a device 100.

FIG. 9D illustrates a non-limiting example of an open mask 903 having and/or defining a plurality of apertures 917a-917d. The apertures 917a-917d are, in some non-limiting examples, positioned such that they may selectively expose certain regions 921 of the device 100, while masking other regions 922. In some non-limiting examples, the lateral aspects 410b of certain emissive region(s) 1910 corresponding to at least some (sub-)pixel(s) 340/264x are exposed through the apertures 917a-917d in the regions 921, while the lateral aspects 410a of other emissive region(s) 1910 corresponding to at least one some (sub-)pixel(s) 340/264x lie within regions 922 and are thus masked.

Turning now to FIG. 10, there is shown an example version 1000 of the device 100 shown in FIG. 1, but with a number of additional deposition steps that are described herein.

The device 1000 shows a lateral aspect of the exposed layer surface 111 of the underlying material. The lateral aspect comprises a first portion 1001 and a second portion 1002. In the first portion 1001, an NIC 810 is disposed on the exposed layer surface 111. However, in the second portion 1002, the exposed layer surface 111 is substantially devoid of the NIC 810.

After selective deposition of the NIC 810 across the first portion 1001, the conductive coating 830 is deposited over the device 1000, in some non-limiting examples, using an open mask and/or a mask-free deposition process, but remains substantially only within the second portion 1002, which is substantially devoid of NIC 810.

The NIC 810 provides, within the first portion 1001, a surface with a relatively low initial sticking probability S₀, for the conductive coating 830, and that is substantially less than the initial sticking probability S₀, for the conductive coating 830, of the exposed layer surface 111 of the underlying material of the device 1000 within the second portion 1002.

Thus, the first portion 1001 is substantially devoid of the conductive coating 830.

In this fashion, the NIC 810 may be selectively deposited, including using a shadow mask, to allow the conductive coating 830 to be deposited, including without limitation, using an open mask and/or a mask-free deposition process, so as to form a device feature, including without limitation, at least one of the first electrode 120, the second electrode 140, the auxiliary electrode 1750, a busbar 4150 and/or at least one layer thereof, and/or a conductive element electrically coupled thereto.

FIGS. 11A-11B illustrate a non-limiting example of an evaporative process, shown generally at 1100, in a chamber 70, for selectively depositing a conductive coating 830 onto a second portion 702 of an exposed layer surface 111 of an underlying material (in the FIGURE, for purposes of simplicity of illustration only, the substrate 110), that is substantially devoid of the NIC 810 that was selectively deposited onto a first portion 701, and onto an NPC portion 1103 of the first portion 701, on which the NIC 810 was deposited, including without limitation, by the evaporative process 700 of FIG. 7.

FIG. 11A describes a stage 1101 of the process 1100, in which, once the NIC 810 has been deposited on the first portion 701 of an exposed layer surface 111 of an underlying material (in the FIGURE, the substrate 110), the NPC 1120 may be deposited on the NPC portion 1103 of the exposed layer surface 111 of the NIC 810 disposed on the substrate 110 in the first portion 701. In the FIGURE, by way of non-limiting example, the NPC portion 1103 extends completely within the first portion 701.

In the stage 1101, a quantity of an NPC material 1121, is heated under vacuum, to evaporate and/or sublime 1122 the NPC material 1121. In some non-limiting examples, the NPC material 1121 comprises entirely, and/or substantially, a material used to form the NPC 1120. Evaporated NPC material 1122 is directed through the chamber 70, including in a direction indicated by arrow 1110, toward the exposed layer surface 111 of the first portion 701 and of the NPC portion 1103. When the evaporated NPC material 1122 is incident on the NPC portion 1103 of the exposed layer surface 111, the NPC 1120 is formed thereon.

In some non-limiting examples, deposition of the NPC material 1121 may be performed using an open mask and/or a mask-free deposition technique, such that the NPC 1120 is formed substantially across the entire exposed layer surface 111 of the underlying material (which could be, in the FIGURE, the NIC 810 throughout the first portion 701 and/or the substrate 110 through the second portion 702) to produce a treated surface (of the NPC 1120).

In some non-limiting examples, as shown in the FIGURE for the stage 1101, the NPC 1120 may be selectively deposited only onto a portion, in the example illustrated, the NPC portion 1103, of the exposed layer surface 111 (in the figure, of the NIC 810), by the interposition, between the NPC material 1121 and the exposed layer surface 111, of a shadow mask 1125, which in some non-limiting examples, may be an FMM. The shadow mask 1125 has at least one aperture 1126 extending therethrough such that a part of the evaporated NPC material 1122 passes through the aperture 1126 and is incident on the exposed layer surface 111 (in the FIGURE, by way of non-limiting example, of the NIC 810 within the NPC portion 1103 only) to form the NPC 1120. Where the evaporated NPC material 1122 does not pass through the aperture 1126 but is incident on the surface 1127 of the shadow mask 1125, it is precluded from being disposed on the exposed layer surface 111 to form the NPC 1120. The portion 1102 of the exposed layer surface 111 that lies beyond the NPC portion 1103, is thus substantially devoid of the NPC 1120. In some non-limiting examples (not shown), the evaporated NPC material 1122 that is incident on the shadow mask 1125 may be deposited on the surface 1127 thereof.

While the exposed layer surface 111 of the NIC 810 in the first portion 701 exhibits a relatively low initial sticking probability S₀ for the conductive coating 830, in some non-limiting examples, this may not necessarily be the case for the NPC coating 1120, such that the NPC coating 1120 is still selectively deposited on the exposed layer surface (in the FIGURE, of the NIC 810) in the NPC portion 1103.

Accordingly, a patterned surface is produced upon completion of the deposition of the NPC 1120.

FIG. 11B describes a stage 1104 of the process 1100, in which, once the NIC 810 has been deposited on the first portion 701 of an exposed layer surface 111 of an underlying material (in the FIGURE, the substrate 110) and the NPC 1120 has been deposited on the NPC portion 1103 of the exposed layer surface 111 (in the FIGURE, of the NIC 810), the conductive coating 830 may be deposited on the NPC portion 1103 and the second portion 702 of the exposed layer surface 111 (in the FIGURE, the substrate 110).

In the stage 1104, a quantity of a conductive coating material 831, is heated under vacuum, to evaporate and/or sublime 832 the conductive coating material 831. In some non-limiting examples, the conductive coating material 831 comprises entirely, and/or substantially, a material used to form the conductive coating 830. Evaporated conductive coating material 832 is directed through the chamber 70, including in a direction indicated by arrow 1120, toward the exposed layer surface 111 of the first portion 701, of the NPC portion 1103 and of the second portion 702. When the evaporated conductive coating material 832 is incident on the NPC portion 1103 of the exposed layer surface 111 (of the NPC 1120) and on the second portion 702 of the exposed layer surface 111 (of the substrate 110), that is, other than on the exposed layer surface 111 of the NIC 810, the conductive coating 830 is formed thereon.

In some non-limiting examples, as shown in the FIGURE for the stage 1104, deposition of the conductive coating 830 may be performed using an open mask and/or mask-free deposition process, such that the conductive coating 830 is formed substantially across the entire exposed layer surface 111 of the underlying material (other than where the underlying material is the NIC 810) to produce a treated surface (of the conductive coating 830).

Indeed, as shown in FIG. 11B, the evaporated conductive coating material 832 is incident both on an exposed layer surface 111 of NIC 810 across the first portion 701 that lies beyond the NPC portion 1103, as well as the exposed layer surface 111 of the NPC 1120 across the NPC portion 1103 and the exposed layer surface 111 of the substrate 110 across the second portion 702 that is substantially devoid of NIC 810.

Since the exposed layer surface 111 of the NIC 810 in the first portion 701 that lies beyond the NPC portion 1103 exhibits a relatively low initial sticking probability S₀ for the conductive coating 830 compared to the exposed layer surface 111 of the substrate 110 in the second portion 702, and/or since the exposed layer surface 111 of the NPC 1120 in the NPC portion 1103 exhibits a relatively high initial sticking probability S₀ for the conductive coating 830 compared to both the exposed layer surface 111 of the NIC 810 in the first portion 701 that lies beyond the NPC portion 1103 and the exposed layer surface 111 of the substrate 110 in the second portion 702, the conductive coating 830 is selectively deposited substantially only on the exposed layer surface 111 of the substrate 110 in the NPC portion 1103 and the second portion 702, both of which are substantially devoid of the NIC 810. By contrast, the evaporated conductive coating material 832 incident on the exposed layer surface 111 of NIC 810 across the first portion 701 that lies beyond the NPC portion 1103, tends not to be deposited, as shown (1123) and the exposed layer surface 111 of NIC 810 across the first portion 701 that lies beyond the NPC portion 1103 is substantially devoid of the conductive coating 830.

Accordingly, a patterned surface is produced upon completion of the deposition of the conductive coating 830.

FIGS. 12A-12C illustrate a non-limiting example of an evaporative process, shown generally at 1200, in a chamber 70, for selectively depositing a conductive coating 830 onto a second portion 1202 (FIG. 12C) of an exposed layer surface 111 of an underlying material.

FIG. 12A describes a stage 1201 of the process 1200, in which, a quantity of an NPC material 1121, is heated under vacuum, to evaporate and/or sublime 1122 the NPC material 1121. In some non-limiting examples, the NPC material 1121 comprises entirely, and/or substantially, a material used to form the NPC 1120. Evaporated NPC material 1122 is directed through the chamber 70, including in a direction indicated by arrow 1210, toward the exposed layer surface 111 (in the FIGURE, the substrate 110).

In some non-limiting examples, deposition of the NPC material 1121 may be performed using an open mask and/or mask-free deposition process, such that the NPC 1120 is formed substantially across the entire exposed layer surface 111 of the underlying material (in the FIGURE, the substrate 110) to produce a treated surface (of the NPC 1120).

In some non-limiting examples, as shown in the FIGURE for the stage 1201, the NPC 1120 may be selectively deposited only onto a portion, in the example illustrated, the NPC portion 1103, of the exposed layer surface 111, by the interposition, between the NPC material 1121 and the exposed layer surface 111, of the shadow mask 1125, which in some non-limiting examples, may be an FMM. The shadow mask 1125 has at least one aperture 1126 extending therethrough such that a part of the evaporated NPC material 1122 passes through the aperture 1126 and is incident on the exposed layer surface 111 to form the NPC 1120 in the NPC portion 1103. Where the evaporated NPC material 1122 does not pass through the aperture 1126 but is incident on the surface 1127 of the shadow mask 1125, it is precluded from being disposed on the exposed layer surface 111 to form the NPC 1120 within the portion 1102 of the exposed layer surface 111 that lies beyond the NPC portion 1103. The portion 1102 is thus substantially devoid of the NPC 1120. In some non-limiting examples (not shown), the NPC material 1121 that is incident on the shadow mask 1125 may be deposited on the surface 1127 thereof.

When the evaporated NPC material 1122 is incident on the exposed layer surface 111, that is, in the NPC portion 1103, the NPC 1120 is formed thereon.

Accordingly, a patterned surface is produced upon completion of the deposition of the NPC 1120.

FIG. 12B describes a stage 1202 of the process 1200, in which, once the NPC 1120 has been deposited on the NPC portion 1103 of an exposed layer surface 111 of an underlying material (in the FIGURE, the substrate 110), the NIC 810 may be deposited on a first portion 701 of the exposed layer surface 111. In the figure, by way of non-limiting example, the first portion 701 extends completely within the NPC portion 1103. As a result, in the FIGURE, by way of non-limiting example, the portion 1102 comprises that portion of the exposed layer surface 111 that lies beyond the first portion 701.

In the stage 1202, a quantity of an NIC material 1211, is heated under vacuum, to evaporate and/or sublime 1212 the NIC material 1211. In some non-limiting examples, the NIC material 1121 comprises entirely, and/or substantially, a material used to form the NIC 810. Evaporated NIC material 1212 is directed through the chamber 70, including in a direction indicated by arrow 1220, toward the exposed layer surface 111 of the first portion 701, of the NPC portion 1103 that extends beyond the first portion 701 and of the portion 1102. When the evaporated NIC material 1212 is incident on the first portion 701 of the exposed layer surface 111, the NIC 810 is formed thereon.

In some non-limiting examples, deposition of the NIC material 1211 may be performed using an open mask and/or mask-free deposition process, such that the NIC 810 is formed substantially across the entire exposed layer surface 111 of the underlying material to produce a treated surface (of the NIC 810).

In some non-limiting examples, as shown in the FIGURE for the stage 1202, the NIC 810 may be selectively deposited only onto a portion, in the example illustrated, the first portion 701, of the exposed layer surface 111 (in the FIGURE, of the NPC 1120), by the interposition, between the NIC material 1211 and the exposed layer surface 111, of a shadow mask 1215, which in some non-limiting examples, may be an FMM. The shadow mask 1215 has at least one aperture 1216 extending therethrough such that a part of the evaporated NIC material 1212 passes through the aperture 1216 and is incident on the exposed layer surface 111 (in the FIGURE, by way of non-limiting example, of the NPC 1120) to form the NIC 810. Where the evaporated NIC material 1212 does not pass through the aperture 1216 but is incident on the surface 1217 of the shadow mask 1215, it is precluded from being disposed on the exposed layer surface 111 to form the NIC 810 within the second portion 702 beyond the first portion 701. The second portion 702 of the exposed layer surface 111 that lies beyond the first portion 701, is thus substantially devoid of the NIC 810. In some non-limiting examples (not shown), the evaporated NIC material 1212 that is incident on the shadow mask 1215 may be deposited on the surface 1217 thereof.

While the exposed layer surface 111 of the NPC 1120 in the NPC portion 1103 exhibits a relatively high initial sticking probability S₀ for the conductive coating 830, in some non-limiting examples, this may not necessarily be the case for the NIC coating 810. Even so, in some non-limiting examples such affinity for the NIC coating 810 may be such that the NIC coating 810 is still selectively deposited on the exposed layer surface 111 (in the FIGURE, of the NPC 1120) in the first portion 701.

Accordingly, a patterned surface is produced upon completion of the deposition of the NIC 810.

FIG. 12C describes a stage 1204 of the process 1200, in which, once the NIC 810 has been deposited on the first portion 701 of an exposed layer surface 111 of an underlying material (in the FIGURE, the NPC 1120), the conductive coating 830 may be deposited on a second portion 702 of the exposed layer surface 111 (in the FIGURE, of the substrate 110 across the portion 1102 beyond the NPC portion 1103 and of the NPC 1120 across the NPC portion 1103 beyond the first portion 701).

In the stage 1204, a quantity of a conductive coating material 831, is heated under vacuum, to evaporate and/or sublime 832 the conductive coating material 831. In some non-limiting examples, the conductive coating material 831 comprises entirely, and/or substantially, a material used to form the conductive coating 830. Evaporated conductive coating material 832 is directed through the chamber 70, including in a direction indicated by arrow 1230, toward the exposed layer surface 111 of the first portion 701, of the NPC portion 1103 and of the portion 1102 beyond the NPC portion 1103. When the evaporated conductive coating material 832 is incident on the NPC portion 1103 of the exposed layer surface 111 (of the NPC 1120) beyond the first portion 701 and on the portion 1102 beyond the NPC portion 1103 of the exposed layer surface 111 (of the substrate 110), that is, on the second portion 702 other than on the exposed layer surface 111 of the NIC 810, the conductive coating 830 is formed thereon.

In some non-limiting examples, as shown in the FIGURE for the stage 1204, deposition of the conductive coating 830 may be performed using an open mask and/or mask-free deposition process, such that the conductive coating 830 is formed substantially across the entire exposed layer surface 111 of the underlying material (other than where the underlying material is the NIC 810) to produce a treated surface (of the conductive coating 830).

Indeed, as shown in FIG. 12C, the evaporated conductive coating material 832 is incident both on an exposed layer surface 111 of NIC 810 across the first portion 701 that lies within the NPC portion 1103, as well as the exposed layer surface 111 of the NPC 1120 across the NPC portion 1103 that lies beyond the first portion 701 and the exposed layer surface 111 of the substrate 110 across the portion 1102 that lies beyond the NPC portion 1103.

Since the exposed layer surface 111 of the NIC 810 in the first portion 701 exhibits a relatively low initial sticking probability S₀ for the conductive coating 830 compared to the exposed layer surface 111 of the substrate 110 in the second portion 702 that lies beyond the NPC portion 1103, and/or since the exposed layer surface 111 of the NPC 1120 in the NPC portion 1103 that lies beyond the first portion 701 exhibits a relatively high initial sticking probability S₀ for the conductive coating 830 compared to both the exposed layer surface 111 of the NIC 810 in the first portion 701 and the exposed layer surface 111 of the substrate 110 in the portion 1102 that lies beyond the NPC portion 1103, the conductive coating 830 is selectively deposited substantially only on the exposed layer surface 111 of the substrate 110 in the NPC portion 1103 that lies beyond the first portion 701 and on the portion 1102 that lies beyond the NPC portion 1103, both of which are substantially devoid of the NIC 810. By contrast, the evaporated conductive coating material 832 incident on the exposed layer surface 111 of NIC 810 across the first portion 701, tends not to be deposited, as shown (1233) and the exposed layer surface 111 of NIC 810 across the first portion 701 is substantially devoid of the conductive coating 830.

Accordingly, a patterned surface is produced upon completion of the deposition of the conductive coating 830.

In some non-limiting examples, an initial deposition rate of the evaporated conductive coating material 832 on the exposed layer surface 111 in the second portion 702 may be at least and/or greater than about 200 times, at least and/or greater than about 550 times, at least and/or greater than about 900 times, at least and/or greater than about 1,000 times, at least and/or greater than about 1,500 times, at least and/or greater than about 1,900 times and/or at least and/or greater than about 2,000 times an initial deposition rate of the evaporated conductive coating material 832 on the exposed layer surface 111 of the NIC 810 in the first portion 701.

FIGS. 13A-13C illustrate a non-limiting example of a printing process, shown generally at 1300, for selectively depositing a selective coating 710, which in some non-limiting examples may be an NIC 810 and/or an NPC 1120, onto an exposed layer surface 111 of an underlying material (in the FIGURE, for purposes of simplicity of illustration only, the substrate 110).

FIG. 13A describes a stage of the process 1300, in which a stamp 1310 having a protrusion 1311 thereon is provided with the selective coating 710 on an exposed layer surface 1312 of the protrusion 1311. Those having ordinary skill in the relevant art will appreciate that the selective coating 710 may be deposited and/or deposited on the protrusion surface 1312 using a variety of suitable mechanisms.

FIG. 13B describes a stage of the process 1300, in which the stamp 1310 is brought into proximity 1301 with the exposed layer surface 111, such that the selective coating 710 comes into contact with the exposed layer surface 111 and adheres thereto.

FIG. 13C describes a stage of the process 1300, in which the stamp 1310 is moved away 1303 from the exposed layer surface 111, leaving the selective coating 710 deposited on the exposed layer surface 111.

Selective Deposition of a Patterned Electrode

The foregoing may be combined in order to effect the selective deposition of at least one conductive coating 830 to form a patterned electrode 120, 140, 1750, 4150, which may, in some non-limiting examples, may be the second electrode 140 and/or an auxiliary electrode 1750, without employing an FMM within the high-temperature conductive coating 830 deposition process. In some non-limiting examples, such patterning may permit and/or enhance the transmissivity of the device 100.

FIG. 14 shows an example patterned electrode 1400 in plan view, in the FIGURE, the second electrode 140 suitable for use in an example version 1500 (FIG. 15) of the device 100. The electrode 1400 is formed in a pattern 1410 that comprises a single continuous structure, having or defining a patterned plurality of apertures 1420 therewithin, in which the apertures 1420 correspond to regions of the device 100 where there is no cathode 342.

In the FIGURE, by way of non-limiting example, the pattern 1410 is disposed across the entire lateral extent of the device 1500, without differentiation between the lateral aspect(s) 410 of emissive region(s) 1910 corresponding to (sub-)pixel(s) 340/264x and the lateral aspect(s) 420 of non-emissive region(s) 1920 surrounding such emissive region(s) 1910. Thus, the example illustrated may correspond to a device 1500 that is substantially transmissive relative to light incident on an external surface thereof, such that a substantial part of such externally-incident light may be transmitted through the device 1500, in addition to the emission (in a top-emission, bottom-emission and/or double-sided emission) of photons generated internally within the device 1500 as disclosed herein.

The transmittivity of the device 1500 may be adjusted and/or modified by altering the pattern 1410 employed, including without limitation, an average size of the apertures 1420, and/or a spacing and/or density of the apertures 1420.

Turning now to FIG. 15, there is shown a cross-sectional view of the device 1500, taken along line 15-15 in FIG. 14. In the FIGURE, the device 1500 is shown as comprising the substrate 110, the first electrode 120 and the at least one semiconducting layer 130. In some non-limiting examples, an NPC 1120 is disposed on substantially all of the exposed layer surface 111 of the at least one semiconducting layer 130. In some non-limiting examples, the NPC 1120 could be omitted.

An NIC 810 is selectively disposed in a pattern substantially corresponding to the pattern 1410 on the exposed layer surface 111 of the underlying material, which, as shown in the FIGURE, is the NPC 1120 (but, in some non-limiting examples, could be the at least one semiconducting layer 130 if the NPC 1120 has been omitted).

A conductive coating 830 suitable for forming the patterned electrode 1400, which in the FIGURE is the second electrode 140, is disposed on substantially all of the exposed layer surface 111 of the underlying material, using an open mask and/or a mask-free deposition process, neither of which employs any FMM during the high-temperature conductive coating deposition process. The underlying material comprises both regions of the NIC 810, disposed in the pattern 1410, and regions of NPC 1120, in the pattern 1410 where the NIC 810 has not been deposited. In some non-limiting examples, the regions of the NIC 810 may correspond substantially to a first portion comprising the apertures 1420 shown in the pattern 1410.

Because of the nucleation-inhibiting properties of those regions of the pattern 1410 where the NIC 810 was disposed (corresponding to the apertures 1420), the conductive coating 830 disposed on such regions tends not to remain, resulting in a pattern of selective deposition of the conductive coating 830, that corresponds substantially to the remainder of the pattern 1410, leaving those regions of the first portion of the pattern 1410 corresponding to the apertures 1420 substantially devoid of the conductive coating 830.

In other words, the conductive coating 830 that will form the cathode 342 is selectively deposited substantially only on a second portion comprising those regions of the NPC 1120 that surround but do not occupy the apertures 1420 in the pattern 1410.

FIG. 16A shows, in plan view, a schematic diagram showing a plurality of patterns 1620, 1640 of electrodes 120, 140, 1750.

In some non-limiting examples, the first pattern 1620 comprises a plurality of elongated, spaced-apart regions that extend in a first lateral direction. In some non-limiting examples, the first pattern 1620 may comprise a plurality of first electrodes 120. In some non-limiting examples, a plurality of the regions that comprise the first pattern 1620 may be electrically coupled.

In some non-limiting examples, the second pattern 1640 comprises a plurality of elongated, spaced-apart regions that extend in a second lateral direction. In some non-limiting examples, the second lateral direction may be substantially normal to the first lateral direction. In some non-limiting examples, the second pattern 1640 may comprise a plurality of second electrodes 140. In some non-limiting examples, a plurality of the regions that comprise the second pattern 1640 may be electrically coupled.

In some non-limiting examples, the first pattern 1620 and the second pattern 1640 may form part of an example version, shown generally at 1600 (FIG. 16C) of the device 100, which may comprise a plurality of PMOLED elements.

In some non-limiting examples, the lateral aspect(s) 410 of emissive region(s) 1910 corresponding to (sub-)pixel(s) 340/264x are formed where the first pattern 1620 overlaps the second pattern 1640. In some non-limiting examples, the lateral aspect(s) 420 of non-emissive region 1920 correspond to any lateral aspect other than the lateral aspect(s) 410.

In some non-limiting examples, a first terminal, which, in some non-limiting examples, may be a positive terminal, of the power source 15, is electrically coupled to at least one electrode 120, 140, 1750 of the first pattern 1620. In some non-limiting examples, the first terminal is coupled to the at least one electrode 120, 140, 1750 of the first pattern 1620 through at least one driving circuit 300. In some non-limiting examples, a second terminal, which, in some non-limiting examples, may be a negative terminal, of the power source 15, is electrically coupled to at least one electrode 120, 140, 1750 of the second pattern 1640. In some non-limiting examples, the second terminal is coupled to the at least one electrode 120, 140, 1750 of the second pattern 1740 through the at least one driving circuit 300.

Turning now to FIG. 16B, there is shown a cross-sectional view of the device 1600, at a deposition stage 1600b, taken along line 16B-16B in FIG. 16A. In the FIGURE, the device 1600 at the stage 1600b is shown as comprising the substrate 110. In some non-limiting examples, an NPC 1120 is disposed on the exposed layer surface 111 of the substrate 110. In some non-limiting examples, the NPC 1120 could be omitted.

An NIC 810 is selectively disposed in a pattern substantially corresponding to the inverse of the first pattern 1620 on the exposed layer surface 111 of the underlying material, which, as shown in the FIGURE, is the NPC 1120.

A conductive coating 830 suitable for forming the first pattern 1620 of electrodes 120, 140, 1750, which in the FIGURE is the first electrode 120, is disposed on substantially all of the exposed layer surface 111 of the underlying material, using an open mask and/or a mask-free deposition process, neither of which employs any FMM during the high-temperature conductive coating deposition process. The underlying material comprises both regions of the NIC 810, disposed in the inverse of the first pattern 1620, and regions of NPC 1120, disposed in the first pattern 1620 where the NIC 810 has not been deposited. In some non-limiting examples, the regions of the NPC 1120 may correspond substantially to the elongated spaced-apart regions of the first pattern 1620, while the regions of the NIC 810 may correspond substantially to a first portion comprising the gaps therebetween.

Because of the nucleation-inhibiting properties of those regions of the first pattern 1620 where the NIC 810 was disposed (corresponding to the gaps therebetween), the conductive coating 830 disposed on such regions tends not to remain, resulting in a pattern of selective deposition of the conductive coating 830, that corresponds substantially to elongated spaced-apart regions of the first pattern 1620, leaving a first portion comprising the gaps therebetween substantially devoid of the conductive coating 830.

In other words, the conductive coating 830 that will form the first pattern 1620 of electrodes 120, 140, 1750 is selectively deposited substantially only on a second portion comprising those regions of the NPC 1120 (or in some non-limiting examples, the substrate 110 if the NPC 1120 has been omitted), that define the elongated spaced-apart regions of the first pattern 1620.

Turning now to FIG. 16C, there is shown a cross-sectional view of the device 1600, taken along line 16C-16C in FIG. 16A. In the FIGURE, the device 1600 is shown as comprising the substrate 110; the first pattern 1620 of electrodes 120 deposited as shown in FIG. 16B, and the at least one semiconducting layer(s) 130.

In some non-limiting examples, the at least one semiconducting layer(s) 130 may be provided as a common layer across substantially all of the lateral aspect(s) of the device 1600.

In some non-limiting examples, an NPC 1120 is disposed on substantially all of the exposed layer surface 111 of the at least one semiconducting layer 130. In some non-limiting examples, the NPC 1120 could be omitted.

An NIC 810 is selectively disposed in a pattern substantially corresponding to the second pattern 1640 on the exposed layer surface 111 of the underlying material, which, as shown in the FIGURE, is the NPC 1120 (but, in some non-limiting examples, could be the at least one semiconducting layer 130 if the NPC 1120 has been omitted).

A conductive coating 830 suitable for forming the second pattern 1640 of electrodes 120, 140, 1750, which in the FIGURE is the second electrode 140, is disposed on substantially all of the exposed layer surface 111 of the underlying material, using an open mask and/or a mask-free deposition process, neither of which employs any FMM during the high-temperature conductive coating deposition process. The underlying material comprises both regions of the NIC 810, disposed in the inverse of the second pattern 1640, and regions of NPC 1120, in the second pattern 1640 where the NIC 810 has not been deposited. In some non-limiting examples, the regions of the NPC 1120 may correspond substantially to a first portion comprising the elongated spaced-apart regions of the second pattern 1640, while the regions of the NIC 810 may correspond substantially to the gaps therebetween.

Because of the nucleation-inhibiting properties of those regions of the second pattern 1640 where the NIC 810 was disposed (corresponding to the gaps therebetween), the conductive coating 830 disposed on such regions tends not to remain, resulting in a pattern of selective deposition of the conductive coating 830, that corresponds substantially to elongated spaced-apart regions of the second pattern 1640, leaving the first portion comprising the gaps therebetween substantially devoid of the conductive coating 830.

In other words, the conductive coating 830 that will form the second pattern 1640 of electrodes 120, 140, 1750 is selectively deposited substantially only on a second portion comprising those regions of the NPC 1120 that define the elongated spaced-apart regions of the second pattern 1640.

In some non-limiting examples, a thickness of the NIC 810 and of the conductive coating 830 deposited thereafter for forming either or both of the first pattern 1620 and/or the second pattern 1640 of electrodes 120, 140, 1750 may be varied according to a variety of parameters, including without limitation, a desired application and desired performance characteristics. In some non-limiting examples, the thickness of the NIC 810 may be comparable to and/or substantially less than a thickness of conductive coating 830 deposited thereafter. Use of a relatively thin NIC 810 to achieve selective patterning of a conductive coating deposited thereafter may be suitable to provide flexible devices 1600, including without limitation, PMOLED devices. In some non-limiting examples, a relatively thin NIC 810 may provide a relatively planar surface on which the barrier coating 1650 may be deposited. In some non-limiting examples, providing such a relatively planar surface for application of the barrier coating 1650 may increase adhesion of the barrier coating 1650 to such surface.

At least one of the first pattern 1620 of electrodes 120, 140, 1750 and at least one of the second pattern 1640 of electrodes 120, 140, 1750 may be electrically coupled to the power source 15, whether directly and/or, in some non-limiting examples, through their respective driving circuit(s) 300 to control photon emission from the lateral aspect(s) 410 of the emissive region(s) 1910 corresponding to (sub-)pixel(s) 340/264x.

Those having ordinary skill in the relevant art will appreciate that the process of forming the second electrode 140 in the second pattern 1640 shown in FIGS. 16A-16C may, in some non-limiting examples, be used in similar fashion to form an auxiliary electrode 1750 for the device 1600. In some non-limiting examples, the second electrode 140 thereof may comprise a common electrode, and the auxiliary electrode 1750 may be deposited in the second pattern 1640, in some non-limiting examples, above or in some non-limiting examples below, the second electrode 140 and electrically coupled thereto. In some non-limiting examples, the second pattern 1640 for such auxiliary electrode 1750 may be such that the elongated spaced-apart regions of the second pattern 1640 lie substantially within the lateral aspect(s) 420 of non-emissive region(s) 1920 surrounding the lateral aspect(s) 410 of emissive region(s) 1910 corresponding to (sub-)pixel(s) 340/264x. In some non-limiting examples, the second pattern 1640 for such auxiliary electrodes 1750 may be such that the elongated spaced-apart regions of the second pattern 1640 lie substantially within the lateral aspect(s) 410 of emissive region(s) 1910 corresponding to (sub-)pixel(s) 340/264x and/or the lateral aspect(s) 420 of non-emissive region(s) 1920 surrounding them.

FIG. 17 shows an example cross-sectional view of an example version 1700 of the device 100 that is substantially similar thereto, but further comprises at least one auxiliary electrode 1750 disposed in a pattern above and electrically coupled (not shown) with the second electrode 140.

The auxiliary electrode 1750 is electrically conductive. In some non-limiting examples, the auxiliary electrode 1750 may be formed by at least one metal and/or metal oxide. Non-limiting examples of such metals include Cu, Al, molybdenum (Mo) and/or Ag. By way of non-limiting examples, the auxiliary electrode 1750 may comprise a multi-layer metallic structure, including without limitation, one formed by Mo/Al/Mo. Non-limiting examples of such metal oxides include ITO, ZnO, IZO and/or other oxides containing In and/or Zn. In some non-limiting examples, the auxiliary electrode 1750 may comprise a multi-layer structure formed by a combination of at least one metal and at least one metal oxide, including without limitation, Ag/ITO, Mo/ITO, ITO/Ag/ITO and/or ITO/Mo/ITO. In some non-limiting examples, the auxiliary electrode 1750 comprises a plurality of such electrically conductive materials.

The device 1700 is shown as comprising the substrate 110, the first electrode 120 and the at least one semiconducting layer 130.

In some non-limiting examples, an NPC 1120 is disposed on substantially all of the exposed layer surface 111 of the at least one semiconducting layer 130. In some non-limiting examples, the NPC 1120 could be omitted.

The second electrode 140 is disposed on substantially all of the exposed layer surface 111 of the NPC 1120 (or the at least one semiconducting layer 130, if the NPC 1120 has been omitted).

In some non-limiting examples, particularly in a top-emission device 1700, the second electrode 140 may be formed by depositing a relatively thin conductive film layer (not shown) in order, by way of non-limiting example, to reduce optical interference (including, without limitation, attenuation, reflections and/or diffusion) related to the presence of the second electrode 140. In some non-limiting examples, as discussed elsewhere, a reduced thickness of the second electrode 140, may generally increase a sheet resistance of the second electrode 140, which may, in some non-limiting examples, reduce the performance and/or efficiency of the device 1700. By providing the auxiliary electrode 1750 that is electrically coupled to the second electrode 140, the sheet resistance and thus, the IR drop associated with the second electrode 140, may, in some non-limiting examples, be decreased.

In some non-limiting examples, the device 1700 may be a bottom-emission and/or double-sided emission device 1700. In such examples, the second electrode 140 may be formed as a relatively thick conductive layer without substantially affecting optical characteristics of such a device 1700. Nevertheless, even in such scenarios, the second electrode 140 may nevertheless be formed as a relatively thin conductive film layer (not shown), by way of non-limiting example, so that the device 1700 may be substantially transmissive relative to light incident on an external surface thereof, such that a substantial part such externally-incident light may be transmitted through the device 1700, in addition to the emission of photons generated internally within the device 1700 as disclosed herein.

An NIC 810 is selectively disposed in a pattern on the exposed layer surface 111 of the underlying material, which, as shown in the FIGURE, is the NPC 1120. In some non-limiting examples, as shown in the FIGURE, the NIC 810 may be disposed, in a first portion of the pattern, as a series of parallel rows 1720.

A conductive coating 830 suitable for forming the patterned auxiliary electrode 1750, is disposed on substantially all of the exposed layer surface 111 of the underlying material, using an open mask and/or a mask-free deposition process, neither of which employs any FMM during the high-temperature conductive coating deposition process. The underlying material comprises both regions of the NIC 810, disposed in the pattern of rows 1720, and regions of NPC 1120 where the NIC 810 has not been deposited.

Because of the nucleation-inhibiting properties of those rows 1720 where the NIC 810 was disposed, the conductive coating 830 disposed on such rows 1720 tends not to remain, resulting in a pattern of selective deposition of the conductive coating 830, that corresponds substantially to at least one second portion of the pattern, leaving the first portion comprising the rows 1720 substantially devoid of the conductive coating 830.

In other words, the conductive coating 830 that will form the auxiliary electrode 1750 is selectively deposited substantially only on a second portion comprising those regions of the NPC 1120, that surround but do not occupy the rows 1720.

In some non-limiting examples, selectively depositing the auxiliary electrode 1750 to cover only certain rows 1720 of the lateral aspect of the device 1700, while other regions thereof remain uncovered, may control and/or reduce optical interference related to the presence of the auxiliary electrode 1750.

In some non-limiting examples, the auxiliary electrode 1750 may be selectively deposited in a pattern that cannot be readily detected by the naked eye from a typical viewing distance.

In some non-limiting examples, the auxiliary electrode 1750 may be formed in devices other than OLED devices, including for decreasing an effective resistance of the electrodes of such devices.

Auxiliary Electrode

The ability to pattern electrodes 120, 140, 1750, 4150 including without limitation, the second electrode 140 and/or the auxiliary electrode 1750 without employing FMMs during the high-temperature conductive coating 830 deposition process by employing a selective coating 710, including without limitation, the process depicted in FIG. 17, allows numerous configurations of auxiliary electrodes 1750 to be deployed.

FIG. 18A shows, in plan view, a part of an example version 1800 of the device 100 having a plurality of emissive regions 1910a-1910j and at least one non-emissive region 1820 surrounding them. In some non-limiting examples, the device 1800 may be an AMOLED device in which each of the emissive regions 1910a-1910j corresponds to a (sub-)pixel 340/264x thereof.

FIGS. 18B-18D show examples of a part of the device 1800 corresponding to neighbouring emissive regions 1910a and 1910b thereof and a part of the at least one non-emissive region 1820 therebetween, in conjunction with different configurations 1750b-1750d of an auxiliary electrode 1750 overlaid thereon. In some non-limiting examples, while not expressly illustrated in FIGS. 18B-18D, the second electrode 140 of the device 1800, is understood to substantially cover at least both emissive regions 1910a and 1910b thereof and the part of the at least one non-emissive region 1820 therebetween.

In FIG. 18B, the auxiliary electrode configuration 1750b is disposed between the two neighbouring emissive regions 1910a and 1910b and electrically coupled to the second electrode 140. In this example, a width α of the auxiliary electrode configuration 1750b is less than a separation distance δ between the neighbouring emissive regions 1910a and 1910b. As a result, there exists a gap within the at least one non-emissive region 1820 on each side of the auxiliary electrode configuration 1830b. In some non-limiting examples, such an arrangement may reduce a likelihood that the auxiliary electrode configuration 1750b would interfere with an optical output of the device 1800, in some non-limiting examples, from at least one of the emissive regions 1910a and 1910b. In some non-limiting examples, such an arrangement may be appropriate where the auxiliary electrode configuration 1750b is relatively thick (in some non-limiting examples, greater than several hundred nm and/or on the order of a few microns in thickness). In some non-limiting examples, a ratio of a height (thickness) of the auxiliary electrode configuration 1750b a width thereof (“aspect ratio”) may be greater than about 0.05, such as about 0.1 or greater, about 0.2 or greater, about 0.5 or greater, about 0.8 or greater, about 1 or greater, and/or about 2 or greater. By way of non-limiting example, a height (thickness) of the auxiliary electrode configuration 1750b may be greater than about 50 nm, such as about 80 nm or greater, about 100 nm or greater, about 200 nm or greater, about 500 nm or greater, about 700 nm or greater, about 1000 nm or greater, about 1500 nm or greater, about 1700 nm or greater, or about 2000 nm or greater.

In FIG. 18C, the auxiliary electrode configuration 1750c is disposed between the two neighbouring emissive regions 1910a and 1910b and electrically coupled to the second electrode 140. In this example, the width α of the auxiliary electrode configuration 1750c is substantially the same as the separation distance δ between the neighbouring emissive regions 1910a and 1910b. As a result, there is no gap within the at least one non-emissive region 1820 on either side of the auxiliary electrode configuration 1750c. In some non-limiting examples, such an arrangement may be appropriate where the separation distance δ between the neighbouring emissive regions 1910a and 1910b is relatively small, by way of non-limiting example, in a high pixel density device 1800.

In FIG. 18D, the auxiliary electrode 1750d is disposed between the two neighbouring emissive regions 1910a and 1910b and electrically coupled to the second electrode 140. In this example, the width α of the auxiliary electrode configuration 1750d is greater than the separation distance δ between the neighbouring emissive regions 1910a and 1910b. As a result, a part of the auxiliary electrode configuration 1750d overlaps a part of at least one of the neighbouring emissive regions 1910a and/or 1910b. While the FIGURE shows that the extent of overlap of the auxiliary electrode configuration 1750d with each of the neighbouring emissive regions 1910a and 1910b, in some non-limiting examples, the extent of overlap and/or in some non-limiting examples, a profile of overlap between the auxiliary electrode configuration 1750d and at least one of the neighbouring emissive regions 1910a and 1910b may be varied and/or modulated.

FIG. 19 shows, in plan view, a schematic diagram showing an example of a pattern 1950 of the auxiliary electrode 1750 formed as a grid that is overlaid over both the lateral aspects 410 of emissive regions 1910, which may correspond to (sub-)pixel(s) 340/264x of an example version 1900 of device 100, and the lateral aspects 420 of non-emissive regions 1920 surrounding the emissive regions 1910.

In some non-limiting examples, the auxiliary electrode pattern 1950 extends substantially only over some but not all of the lateral aspects 420 of non-emissive regions 1920, so as not to substantially cover any of the lateral aspects 410 of the emissive regions 1910.

Those having ordinary skill in the relevant art will appreciate that while, in the FIGURE, the auxiliary electrode pattern 1950 is shown as being formed as a continuous structure such that all elements thereof are both physically connected and electrically coupled with one another and electrically coupled to at least one electrode 120, 140, 1750, 4150, which in some non-limiting examples may be the first electrode 120 and/or the second electrode 140, in some non-limiting examples, the auxiliary electrode pattern 1950 may be provided as a plurality of discrete elements of the auxiliary electrode pattern 1950 that, while remaining electrically coupled to one another, are not physically connected to one another. Even so, such discrete elements of the auxiliary electrode pattern 1950 may still substantially lower a sheet resistance of the at least one electrode 120, 140, 1750, 4150 with which they are electrically coupled, and consequently of the device 1900, so as to increase an efficiency of the device 1900 without substantially interfering with its optical characteristics.

In some non-limiting examples, auxiliary electrodes 1750 may be employed in devices 100 with a variety of arrangements of (sub-)pixel(s) 340/264x. In some non-limiting examples, the (sub-)pixel 340/264x arrangement may be substantially diamond-shaped.

By way of non-limiting example, FIG. 20A shows, in plan view, in an example version 2000 of device 100, a plurality of groups 2041-2043 of emissive regions 1910 each corresponding to a sub-pixel 264x, surrounded by the lateral aspects of a plurality of non-emissive regions 1920 comprising PDLs 440 in a diamond configuration. In some non-limiting examples, the configuration is defined by patterns 2041-2043 of emissive regions 1910 and PDLs 440 in an alternating pattern of first and second rows.

In some non-limiting examples, the lateral aspects 420 of the non-emissive regions 1920 comprising PDLs 440 may be substantially elliptically-shaped. In some non-limiting examples, the major axes of the lateral aspects 420 of the non-emissive regions 1920 in the first row are aligned and substantially normal to the major axes of the lateral aspects 420 of the non-emissive regions 1920 in the second row. In some non-limiting examples, the major axes of the lateral aspects 420 of the non-emissive regions 1920 in the first row are substantially parallel to an axis of the first row.

In some non-limiting examples, a first group 2041 of emissive regions 1910 correspond to sub-pixels 264x that emit light at a first wavelength, in some non-limiting examples the sub-pixels 264x of the first group 2041 may correspond to red (R) sub-pixels 2641. In some non-limiting examples, the lateral aspects 410 of the emissive regions 1910 of the first group 2041 may have a substantially diamond-shaped configuration. In some non-limiting examples, the emissive regions 1910 of the first group 2041 lie in the pattern of the first row, preceded and followed by PDLs 440. In some non-limiting examples, the lateral aspects 410 of the emissive regions 1910 of the first group 2041 slightly overlap the lateral aspects 420 of the preceding and following non-emissive regions 1920 comprising PDLs 440 in the same row, as well as of the lateral aspects 420 of adjacent non-emissive regions 1920 comprising PDLs 440 in a preceding and following pattern of the second row.

In some non-limiting examples, a second group 2042 of emissive regions 1910 correspond to sub-pixels 264x that emit light at a second wavelength, in some non-limiting examples the sub-pixels 264x of the second group 2042 may correspond to green (G) sub-pixels 2642. In some non-limiting examples, the lateral aspects 410 of the emissive regions 1910 of the second group 2041 may have a substantially elliptical configuration. In some non-limiting examples, the emissive regions 1910 of the second group 2041 lie in the pattern of the second row, preceded and followed by PDLs 440. In some non-limiting examples, the major axis of some of the lateral aspects 410 of the emissive regions 1910 of the second group 2041 may be at a first angle, which in some non-limiting examples, may be 45° relative to an axis of the second row. In some non-limiting examples, the major axis of others of the lateral aspects 410 of the emissive regions 1910 of the second group 2041 may be at a second angle, which in some non-limiting examples may be substantially normal to the first angle. In some non-limiting examples, the emissive regions 1910 of the first group 2041, whose lateral aspects 410 have a major axis at the first angle, alternate with the emissive regions 1910 of the first group 2041, whose lateral aspects 410 have a major axis at the second angle.

In some non-limiting examples, a third group 2043 of emissive regions 1910 correspond to sub-pixels 264x that emit light at a third wavelength, in some non-limiting examples the sub-pixels 264x of the third group 2043 may correspond to blue (B) sub-pixels 2643. In some non-limiting examples, the lateral aspects 410 of the emissive regions 1910 of the third group 2043 may have a substantially diamond-shaped configuration. In some non-limiting examples, the emissive regions 1910 of the third group 2043 lie in the pattern of the first row, preceded and followed by PDLs 440. In some non-limiting examples, the lateral aspects 410 of the emissive regions 1910 of the third group 2043 slightly overlap the lateral aspects 410 of the preceding and following non-emissive regions 1920 comprising PDLs 440 in the same row, as well as of the lateral aspects 420 of adjacent non-emissive regions 1920 comprising PDLs 440 in a preceding and following pattern of the second row. In some non-limiting examples, the pattern of the second row comprises emissive regions 1910 of the first group 2041 alternating emissive regions 1910 of the third group 2043, each preceded and followed by PDLs 440.

Turning now to FIG. 20B, there is shown an example cross-sectional view of the device 2000, taken along line 20B-20B in FIG. 20A. In the FIGURE, the device 2000 is shown as comprising a substrate 110 and a plurality of elements of a first electrode 120, formed on an exposed layer surface 111 thereof. The substrate 110 may comprise the base substrate 112 (not shown for purposes of simplicity of illustration) and/or at least one TFT structure 200, corresponding to and for driving each sub-pixel 264x. PDLs 440 are formed over the substrate 110 between elements of the first electrode 120, to define emissive region(s) 1910 over each element of the first electrode 120, separated by non-emissive region(s) 1920 comprising the PDL(s) 440. In the FIGURE, the emissive region(s) 1910 all correspond to the second group 2042.

In some non-limiting examples, at least one semiconducting layer 130 is deposited on each element of the first electrode 120, between the surrounding PDLs 440.

In some non-limiting examples, a second electrode 140, which in some non-limiting examples, may be a common cathode, may be deposited over the emissive region(s) 1910 of the second group 2042 to form the G(reen) sub-pixel(s) 2642 thereof and over the surrounding PDLs 440.

In some non-limiting examples, an NIC 810 is selectively deposited over the second electrode 140 across the lateral aspects 410 of the emissive region(s) 1910 of the second group 2042 of G(reen) sub-pixels 2642 to allow selective deposition of a conductive coating 830 over parts of the second electrode 140 that is substantially devoid of the NIC 810, namely across the lateral aspects 420 of the non-emissive region(s) 1920 comprising the PDLs 440. In some non-limiting examples, the conductive coating 830 may tend to accumulate along the substantially planar parts of the PDLs 440, as the conductive coating 830 may not tend to remain on the inclined parts of the PDLs 440, but tends to descend to a base of such inclined parts, which are coated with the NIC 810. In some non-limiting examples, the conductive coating 830 on the substantially planar parts of the PDLs 440 may form at least one auxiliary electrode 1750 that may be electrically coupled to the second electrode 140.

In some non-limiting examples, the device 2000 may comprise a capping layer and/or an outcoupling layer. By way of non-limiting example, such capping layer and/or outcoupling layer may be provided directly on a surface of the second electrode 140 and/or a surface of the NIC 810. In some non-limiting examples, such capping layer and/or outcoupling layer may be provided across the lateral aspect 410 of at least one emissive region 1910 corresponding to a (sub-) pixel 340/264x.

In some non-limiting examples, the NIC 810 may also act as an index-matching coating. In some non-limiting examples, the NIC 810 may also act as an outcoupling layer.

In some non-limiting examples, the device 2000 comprises an encapsulation layer. Non-limiting examples of such encapsulation layer include a glass cap, a barrier film, a barrier adhesive and/or a TFE layer 2050 such as shown in dashed outline in the FIGURE, provided to encapsulate the device 2000. In some non-limiting examples, the TFE layer 2050 may be considered a type of barrier coating 1650.

In some non-limiting examples, the encapsulation layer may be arranged above at least one of the second electrode 140 and/or the NIC 810. In some non-limiting example, the device 2000 comprises additional optical and/or structural layers, coatings and components, including without limitation, a polarizer, a color filter, an anti-reflection coating, an anti-glare coating, cover class and/or an optically-clear adhesive (OCA).

Turning now to FIG. 20C, there is shown an example cross-sectional view of the device 2000, taken along line 20C-20C in FIG. 20A. In the FIGURE, the device 2000 is shown as comprising a substrate 110 and a plurality of elements of a first electrode 120, formed on an exposed layer surface 111 thereof. PDLs 440 are formed over the substrate 110 between elements of the first electrode 120, to define emissive region(s) 1910 over each element of the first electrode 120, separated by non-emissive region(s) 1920 comprising the PDL(s) 440. In the figure, the emissive region(s) 1910 correspond to the first group 2041 and to the third group 2043 in alternating fashion.

In some non-limiting examples, at least one semiconducting layer 130 is deposited on each element of the first electrode 120, between the surrounding PDLs 440.

In some non-limiting examples, a second electrode 140, which in some non-limiting examples, may be a common cathode, may be deposited over the emissive region(s) 1910 of the first group 2041 to form the R(ed) sub-pixel(s) 2641 thereof, over the emissive region(s) 1910 of the third group 2043 to form the B(lue) sub-pixel(s) 2643 thereof, and over the surrounding PDLs 440.

In some non-limiting examples, an NIC 810 is selectively deposited over the second electrode 140 across the lateral aspects 410 of the emissive region(s) 1910 of the first group 2041 of R(ed) sub-pixels 2641 and of the third group of B(lue) sub-pixels 2643 to allow selective deposition of a conductive coating 830 over parts of the second electrode 140 that is substantially devoid of the NIC 810, namely across the lateral aspects 420 of the non-emissive region(s) 1920 comprising the PDLs 440. In some non-limiting examples, the conductive coating 830 may tend to accumulate along the substantially planar parts of the PDLs 440, as the conductive coating 830 may not tend to remain on the inclined parts of the PDLs 440, but tends to descend to a base of such inclined parts, which are coated with the NIC 810. In some non-limiting examples, the conductive coating 830 on the substantially planar parts of the PDLs 440 may form at least one auxiliary electrode 1750 that may be electrically coupled to the second electrode 140.

Turning now to FIG. 21, there is shown an example version 2100 of the device 100, which encompasses the device 100 shown in cross-sectional view in FIG. 4, but with a number of additional deposition steps that are described herein.

The device 2100 shows an NIC 810 selectively deposited over the exposed layer surface 111 of the underlying material, in the FIGURE, the second electrode 140, within a first portion of the device 2100, corresponding substantially to the lateral aspect 410 of emissive region(s) 1910 corresponding to (sub-)pixel(s) 340/264x and not within a second portion of the device 2100, corresponding substantially to the lateral aspect(s) 420 of non-emissive region(s) 1920 surrounding the first portion.

In some non-limiting examples, the NIC 810 may be selectively deposited using a shadow mask.

The NIC 810 provides, within the first portion, a surface with a relatively low initial sticking probability S₀ for a conductive coating 830 to be thereafter deposited on form an auxiliary electrode 1750.

After selective deposition of the NIC 810, the conductive coating 830 is deposited over the device 2100 but remains substantially only within the second portion, which is substantially devoid of NIC 810, to form the auxiliary electrode 1750.

In some non-limiting examples, the conductive coating 830 may be deposited using an open mask and/or a mask-free deposition process.

The auxiliary electrode 1750 is electrically coupled to the second electrode 140 so as to reduce a sheet resistance of the second electrode 140, including, as shown, by lying above and in physical contact with the second electrode 140 across the second portion that is substantially devoid of NIC 810.

In some non-limiting examples, the conductive coating 830 may comprise substantially the same material as the second electrode 140, to ensure a high initial sticking probability S₀ for the conductive coating 830 in the second portion.

In some non-limiting examples, the second electrode 140 may comprise substantially pure Mg and/or an alloy of Mg and another metal, including without limitation, Ag. In some non-limiting examples, an Mg:Ag alloy composition may range from about 1:9 to about 9:1 by volume. In some non-limiting examples, the second electrode 140 may comprise metal oxides, including without limitation, ternary metal oxides, such as, without limitation, ITO and/or IZO, and/or a combination of metals and/or metal oxides.

In some non-limiting examples, the conductive coating 830 used to form the auxiliary electrode 1750 may comprise substantially pure Mg.

Turning now to FIG. 22, there is shown an example version 2200 of the device 100, which encompasses the device 100 shown in cross-sectional view in FIG. 4, but with a number of additional deposition steps that are described herein.

The device 2200 shows an NIC 810 selectively deposited over the exposed layer surface 111 of the underlying material, in the FIGURE, the second electrode 140, within a first portion of the device 2200, corresponding substantially to a part of the lateral aspect 410 of emissive region(s) 1910 corresponding to (sub-) pixel(s) 340/264x, and not within a second portion. In the FIGURE, the first portion extends partially along the extent of an inclined part of the PDLs 440 defining the emissive region(s) 1910.

In some non-limiting examples, the NIC 810 may be selectively deposited using a shadow mask.

The NIC 810 provides, within the first portion, a surface with a relatively low initial sticking probability S₀ for a conductive coating 830 to be thereafter deposited on form an auxiliary electrode 1750.

After selective deposition of the NIC 810, the conductive coating 830 is deposited over the device 2200 but remains substantially only within the second portion, which is substantially devoid of NIC 810, to form the auxiliary electrode 1750. As such, in the device 2200, the auxiliary electrode 1750 extends partly across the inclined part of the PDLs 440 defining the emissive region(s) 1910.

In some non-limiting examples, the conductive coating 830 may be deposited using an open mask and/or a mask-free deposition process.

The auxiliary electrode 1750 is electrically coupled to the second electrode 140 so as to reduce a sheet resistance of the second electrode 140, including, as shown, by lying above and in physical contact with the second electrode 140 across the second portion that is substantially devoid of NIC 810.

In some non-limiting examples, the material of which the second electrode 140 may be comprised, may not have a high initial sticking probability S₀ for the conductive coating 830.

FIG. 23 illustrates such a scenario, in which there is shown an example version 2300 of the device 100, which encompasses the device 100 shown in cross-sectional view in FIG. 4, but with a number of additional deposition steps that are described herein.

The device 2300 shows an NPC 1120 deposited over the exposed layer surface 111 of the underlying material, in the FIGURE, the second electrode 140.

In some non-limiting examples, the NPC 1120 may be deposited using an open mask and/or a mask-free deposition process.

Thereafter, an NIC 810 is deposited selectively deposited over the exposed layer surface 111 of the underlying material, in the FIGURE, the NPC 1120, within a first portion of the device 2300, corresponding substantially to a part of the lateral aspect 410 of emissive region(s) 1910 corresponding to (sub-)pixel(s) 340/264x, and not within a second portion of the device 2300, corresponding substantially to the lateral aspect(s) 420 of non-emissive region(s) 1920 surrounding the first portion.

In some non-limiting examples, the NIC 810 may be selectively deposited using a shadow mask.

The NIC 810 provides, within the first portion, a surface with a relatively low initial sticking probability S₀ for a conductive coating 830 to be thereafter deposited on form an auxiliary electrode 1750.

After selective deposition of the NIC 810, the conductive coating 830 is deposited over the device 2300 but remains substantially only within the second portion, which is substantially devoid of NIC 810, to form the auxiliary electrode 1750.

In some non-limiting examples, the conductive coating 830 may be deposited using an open mask and/or a mask-free deposition process.

The auxiliary electrode 1750 is electrically coupled to the second electrode 140 so as to reduce a sheet resistance thereof. While, as shown, the auxiliary electrode 1750 is not lying above and in physical contact with the second electrode 140, those having ordinary skill in the relevant art will nevertheless appreciate that the auxiliary electrode 1750 may be electrically coupled to the second electrode 140 by a number of well-understood mechanisms. By way of non-limiting example, the presence of a relatively thin film (in some non-limiting examples, of up to about 50 nm) of an NIC 810 and/or an NPC 1120 may still allow a current to pass therethrough, thus allowing a sheet resistance of the second electrode 140 to be reduced.

Turning now to FIG. 24, there is shown an example version 2400 of the device 100, which encompasses the device 100 shown in cross-sectional view in FIG. 4, but with a number of additional deposition steps that are described herein.

The device 2400 shows an NIC 810 deposited over the exposed layer surface 111 of the underlying material, in the FIGURE, the second electrode 140.

In some non-limiting examples, the NIC 810 may be deposited using an open mask and/or a mask-free deposition process.

The NIC 810 provides a surface with a relatively low initial sticking probability S₀ for a conductive coating 830 to be thereafter deposited on form an auxiliary electrode 1750.

After deposition of the NIC 810, an NPC 1120 is selectively deposited over the exposed layer surface 111 of the underlying material, in the FIGURE, the NIC 810, within a NPC portion of the device 2400, corresponding substantially to a part of the lateral aspect 420 of non-emissive region(s) 1920 surrounding a second portion of the device 2400, corresponding substantially to the lateral aspect(s) 410 of emissive region(s) 1910 corresponding to (sub-)pixel(s) 340/264x.

In some non-limiting examples, the NPC 1120 may be selectively deposited using a shadow mask.

The NPC 1120 provides, within the first portion, a surface with a relatively high initial sticking probability S₀ for a conductive coating 830 to be thereafter deposited on form an auxiliary electrode 1750.

After selective deposition of the NPC 1120, the conductive coating 830 is deposited over the device 2400 but remains substantially only within the NPC portion, in which the NIC 810 has been overlaid with the NPC 1120, to form the auxiliary electrode 1750.

In some non-limiting examples, the conductive coating 830 may be deposited using an open mask and/or a mask-free deposition process.

The auxiliary electrode 1750 is electrically coupled to the second electrode 140 so as to reduce a sheet resistance of the second electrode 140.

Removal of Selective Coatings

In some non-limiting examples, the NIC 810 may be removed subsequent to deposition of the conductive coating 830, such that at least a part of a previously exposed layer surface 111 of an underlying material covered by the NIC 810 may become exposed once again. In some non-limiting examples, the NIC 810 may be selectively removed by etching and/or dissolving the NIC 810 and/or by employing plasma and/or solvent processing techniques that do not substantially affect or erode the conductive coating 830.

Turning now to FIG. 25A, there is shown an example cross-sectional view of an example version 2500 of the device 100, at a deposition stage 2500a, in which an NIC 810 has been selectively deposited on a first portion of an exposed layer surface 111 of an underlying material. In the FIGURE, the underlying material may be the substrate 110.

In FIG. 25B, the device 2500 is shown at a deposition stage 2500b, in which a conductive coating 830 is deposited on the exposed layer surface 111 of the underlying material, that is, on both the exposed layer surface 111 of NIC 810 where the NIC 810 has been deposited during the stage 2500a, as well as the exposed layer surface 111 of the substrate 110 where that NIC 810 has not been deposited during the stage 2500a. Because of the nucleation-inhibiting properties of the first portion where the NIC 810 was disposed, the conductive coating 830 disposed thereon tends not to remain, resulting in a pattern of selective deposition of the conductive coating 830, that corresponds to a second portion, leaving the first portion substantially devoid of the conductive coating.

In FIG. 25C, the device 2500 is shown at a deposition stage 2500c, in which the NIC 810 has been removed from the first portion of the exposed layer surface 111 of the substrate 110, such that the conductive coating 830 deposited during the stage 2500b remains on the substrate 110 and regions of the substrate 110 on which the NIC 810 had been deposited during the stage 2500a are now exposed or uncovered.

In some non-limiting examples, the removal of the NIC 810 in the stage 2500c may be effected by exposing the device 2500 to a solvent and/or a plasma that reacts with and/or etches away the NIC 810 without substantially impacting the conductive coating 830.

Transparent OLED

Turning now to FIG. 26A, there is shown an example plan view of a transmissive (transparent) version, shown generally at 2600, of the device 100. In some non-limiting examples, the device 2600 is an AMOLED device having a plurality of pixel regions 2610 and a plurality of transmissive regions 2620. In some non-limiting examples, at least one auxiliary electrode 1750 may be deposited on an exposed layer surface 111 of an underlying material between the pixel region(s) 2610 and/or the transmissive region(s) 2620.

In some non-limiting examples, each pixel region 2610 may comprise a plurality of emissive regions 1910 each corresponding to a sub-pixel 264x. In some non-limiting examples, the sub-pixels 264x may correspond to, respectively, R(ed) sub-pixels 2641, G(reen) sub-pixels 2642 and/or B(lue) sub-pixels 2643.

In some non-limiting examples, each transmissive region 2620 is substantially transparent and allows light to pass through the entirety of a cross-sectional aspect thereof.

Turning now to FIG. 26B, there is shown an example cross-sectional view of the device 2600, taken along line 26B-26B in FIG. 26A. In the FIGURE, the device 2600 is shown as comprising a substrate 110, a TFT insulating layer 280 and a first electrode 120 formed on a surface of the TFT insulating layer 280. The substrate 110 may comprise the base substrate 112 (not shown for purposes of simplicity of illustration) and/or at least one TFT structure 200, corresponding to and for driving each sub-pixel 264x positioned substantially thereunder and electrically coupled to the first electrode 120 thereof. PDL(s) 440 are formed in non-emissive regions 1920 over the substrate 110, to define emissive region(s) 1910 also corresponding to each sub-pixel 264x, over the first electrode 120 corresponding thereto. The PDL(s) 440 cover edges of the first electrode 120.

In some non-limiting examples, at least one semiconducting layer 130 is deposited over exposed region(s) of the first electrode 120 and, in some non-limiting examples, at least parts of the surrounding PDLs 440.

In some non-limiting examples, a second electrode 140 may be deposited over the at least one semiconducting layer(s) 130, including over the pixel region 2610 to form the sub-pixel(s) 264x thereof and, in some non-limiting examples, at least partially over the surrounding PDLs 440 in the transmissive region 2620.

In some non-limiting examples, an NIC 810 is selectively deposited over first portion(s) of the device 2600, comprising both the pixel region 2610 and the transmissive region 2620 but not the region of the second electrode 140 corresponding to the auxiliary electrode 1750.

In some non-limiting examples, the entire surface of the device 2600 is then exposed to a vapor flux of the conductive coating 830, which in some non-limiting examples may be Mg. The conductive coating 830 is selectively deposited over second portion(s) of the second electrode 140 that is substantially devoid of the NIC 810 to form an auxiliary electrode 1750 that is electrically coupled to and in some non-limiting examples, in physical contact with uncoated parts of the second electrode 140.

At the same time, the transmissive region 2620 of the device 2600 remains substantially devoid of any materials that may substantially affect the transmission of light therethrough. In particular, as shown in the FIGURE, the TFT structure 200 and the first electrode 120 are positioned, in a cross-sectional aspect, below the sub-pixel 264x corresponding thereto, and together with the auxiliary electrode 1750, lie beyond the transmissive region 2620. As a result, these components do not attenuate or impede light from being transmitted through the transmissive region 2620. In some non-limiting examples, such arrangement allows a viewer viewing the device 2600 from a typical viewing distance to see through the device 2600, in some non-limiting examples, when all of the (sub-) pixel(s) 340/264x are not emitting, thus creating a transparent AMOLED device 2600.

While not shown in the FIGURE, in some non-limiting examples, the device 2600 may further comprise an NPC 1120 disposed between the auxiliary electrode 1750 and the second electrode 140. In some non-limiting examples, the NPC 1120 may also be disposed between the NIC 810 and the second electrode 140.

In some non-limiting examples, the NIC 810 may be formed concurrently with the at least one semiconducting layer(s) 130. By way of non-limiting example, at least one material used to form the NIC 810 may also be used to form the at least one semiconducting layer(s) 130. In such non-limiting example, a number of stages for fabricating the device 2600 may be reduced.

Those having ordinary skill in the relevant art will appreciate that in some non-limiting examples, various other layers and/or coatings, including without limitation those forming the at least one semiconducting layer(s) 130 and/or the second electrode 140, may cover a part of the transmissive region 2620, especially if such layers and/or coatings are substantially transparent. In some non-limiting examples, the PDL(s) 440 may have a reduced thickness, including without limitation, by forming a well therein, which in some non-limiting examples is not dissimilar to the well defined for emissive region(s) 1910, to further facilitate light transmission through the transmissive region 2620.

Those having ordinary skill in the relevant art will appreciate that (sub-) pixel(s) 340/264x arrangements other than the arrangement shown in FIGS. 26A and 26B may, in some non-limiting examples, be employed.

Those having ordinary skill in the relevant art will appreciate that arrangements of the auxiliary electrode(s) 1750 other than the arrangement shown in FIGS. 26A and 26B may, in some non-limiting examples, be employed. By way of non-limiting example, the auxiliary electrode(s) 1750 may be disposed between the pixel region 2610 and the transmissive region 2620. By way of non-limiting example, the auxiliary electrode(s) 1750 may be disposed between sub-pixel(s) 264x within a pixel region 2610.

Turning now to FIG. 27A, there is shown an example plan view of a transparent version, shown generally at 2700 of the device 100. In some non-limiting examples, the device 2700 is an AMOLED device having a plurality of pixel regions 2610 and a plurality of transmissive regions 2620. The device 2700 differs from device 2600 in that no auxiliary electrode(s) 1750 lie between the pixel region(s) 2610 and/or the transmissive region(s) 2620.

In some non-limiting examples, each pixel region 2610 may comprise a plurality of emissive regions 1910 each corresponding to a sub-pixel 264x. In some non-limiting examples, the sub-pixels 264x may correspond to, respectively, R(ed) sub-pixels 2641, G(reen) sub-pixels 2642 and/or B(lue) sub-pixels 2643.

In some non-limiting examples, each transmissive region 2620 is substantially transparent and allows light to pass through the entirety of a cross-sectional aspect thereof.

Turning now to FIG. 27B, there is shown an example cross-sectional view of the device 2700, taken along line 27B-27B in FIG. 27A. In the FIGURE, the device 2700 is shown as comprising a substrate 110, a TFT insulating layer 280 and a first electrode 120 formed on a surface of the TFT insulating layer 280. The substrate 110 may comprise the base substrate 112 (not shown for purposes of simplicity of illustration) and/or at least one TFT structure 200 corresponding to and for driving each sub-pixel 264x positioned substantially thereunder and electrically coupled to the first electrode 120 thereof. PDL(s) 440 are formed in non-emissive regions 1920 over the substrate 110, to define emissive region(s) 1910 also corresponding to each sub-pixel 264x, over the first electrode 120 corresponding thereto. The PDL(s) 440 cover edges of the first electrode 120.

In some non-limiting examples, at least one semiconducting layer 130 is deposited over exposed region(s) of the first electrode 120 and, in some non-limiting examples, at least parts of the surrounding PDLs 440.

In some non-limiting examples, a first conductive coating 830a may be deposited over the at least one semiconducting layer(s) 130, including over the pixel region 2610 to form the sub-pixel(s) 264x thereof and over the surrounding PDLs 440 in the transmissive region 2620. In some non-limiting examples, the thickness of the first conductive coating 830a may be relatively thin such that the presence of the first conductive coating 830a across the transmissive region 2620 does not substantially attenuate transmission of light therethrough. In some non-limiting examples, the first conductive coating 830a may be deposited using an open mask and/or mask-free deposition process.

In some non-limiting examples, an NIC 810 is selectively deposited over first portions of the device 2700, comprising the transmissive region 2620.

In some non-limiting examples, the entire surface of the device 2700 is then exposed to a vapor flux of the conductive coating 830, which in some non-limiting examples may be Mg to selectively deposit a second conductive coating 830b over second portion(s) of the first conductive coating 830a that are substantially devoid of the NIC 810, in some examples, the pixel region 2610, such that the second conductive coating 830b is electrically coupled to and in some non-limiting examples, in physical contact with uncoated parts of the first conductive coating 830a, to form the second electrode 140.

In some non-limiting examples, a thickness of the first conductive coating 830a may be less than a thickness of the second conductive coating 830b. In this way, relatively high transmittance may be maintained in the transmissive region 2620, over which only the first conductive coating 830a extends. In some non-limiting examples, the thickness of the first conductive coating 830a may be less than about 30 nm, less than about 25 nm, less than about 20 nm, less than about 15 nm, less than about 10 nm, less than about 8 nm, and/or less than about 5 nm. In some non-limiting examples, the thickness of the second conductive coating 830b may be less than about 30 nm, less than about 25 nm, less than about 20 nm, less than about 15 nm, less than about 10 nm and/or less than about 8 nm.

Thus, in some non-limiting examples, a thickness of the second electrode 140 may be less than about 40 nm, and/or in some non-limiting examples, between about 5 nm and 30 nm, between about 10 nm and about 25 nm and/or between about 15 nm and about 25 nm.

In some non-limiting examples, the thickness of the first conductive coating 830a may be greater than the thickness of the second conductive coating 830b. In some non-limiting examples, the thickness of the first conductive coating 830a and the thickness of the second conductive coating 830b may be substantially the same.

In some non-limiting examples, at least one material used to form the first conductive coating 830a may be substantially the same as at least one material used to form the second conductive coating 830b. In some non-limiting examples, such at least one material may be substantially as described herein in respect of the first electrode 120, the second electrode 140, the auxiliary electrode 1750 and/or a conductive coating 830 thereof.

In some non-limiting examples, the transmissive region 2620 of the device 2700 remains substantially devoid of any materials that may substantially affect the transmission of light therethrough. In particular, as shown in the FIGURE, the TFT structure 200 and/or the first electrode 120 are positioned, in a cross-sectional aspect below the sub-pixel 264x corresponding thereto and beyond the transmissive region 2620. As a result, these components do not attenuate or impede light from being transmitted through the transmissive region 2620. In some non-limiting examples, such arrangement allows a viewer viewing the device 2700 from a typical viewing distance to see through the device 2700, in some non-limiting examples, when all of the (sub-)pixel(s) 340/264x are not emitting, thus creating a transparent AMOLED device 2700.

While not shown in the FIGURE, in some non-limiting examples, the device 2700 may further comprise an NPC 1120 disposed between the second conductive coating 830b and the first conductive coating 830a. In some non-limiting examples, the NPC 1120 may also be disposed between the NIC 810 and the first conductive coating 830a.

In some non-limiting examples, the NIC 810 may be formed concurrently with the at least one semiconducting layer(s) 130. By way of non-limiting example, at least one material used to form the NIC 810 may also be used to form the at least one semiconducting layer(s) 130. In such non-limiting example, a number of stages for fabricating the device 2700 may be reduced.

Those having ordinary skill in the relevant art will appreciate that in some non-limiting examples, various other layers and/or coatings, including without limitation those forming the at least one semiconducting layer(s) 130 and/or the first conductive coating 830a, may cover a part of the transmissive region 2620, especially if such layers and/or coatings are substantially transparent. In some non-limiting examples, the PDL(s) 440 may have a reduced thickness, including without limitation, by forming a well therein, which in some non-limiting examples is not dissimilar to the well defined for emissive region(s) 1910, to further facilitate light transmission through the transmissive region 2620.

Those having ordinary skill in the relevant art will appreciate that (sub-) pixel(s) 340/264x arrangements other than the arrangement shown in FIGS. 27A and 27B may, in some non-limiting examples, be employed.

Turning now to FIG. 27C, there is shown an example cross-sectional view of a different version of the device 100, shown as device 1910, taken along the same line 27B-27B in FIG. 27A. In the FIGURE, the device 1910 is shown as comprising a substrate 110, a TFT insulating layer 280 and a first electrode 120 formed on a surface of the TFT insulating layer 280. The substrate 110 may comprise the base substrate 112 (not shown for purposes of simplicity of illustration) and/or at least one TFT structure 200 corresponding to and for driving each sub-pixel 264x positioned substantially thereunder and electrically coupled to the first electrode 120 thereof. PDL(s) 440 are formed in non-emissive regions 1920 over the substrate 110, to define emissive region(s) 1910 also corresponding to each sub-pixel 264x, over the first electrode 120 corresponding thereto. The PDL(s) 440 cover edges of the first electrode 120.

In some non-limiting examples, at least one semiconducting layer 130 is deposited over exposed region(s) of the first electrode 120 and, in some non-limiting examples, at least parts of the surrounding PDLs 440.

In some non-limiting examples, an NIC 810 is selectively deposited over first portions of the device 2700, comprising the transmissive region 2620.

In some non-limiting examples, a conductive coating 830 may be deposited over the at least one semiconducting layer(s) 130, including over the pixel region 2610 to form the sub-pixel(s) 264x thereof but not over the surrounding PDLs 440 in the transmissive region 2620. In some non-limiting examples, the first conductive coating 830a may be deposited using an open mask and/or mask-free deposition process. In some non-limiting examples, such deposition may be effected by exposing the entire surface of the device 1910 to a vapour flux of the conductive coating 830, which in some non-limiting examples may be Mg to selectively deposit the conductive coating 830 over second portions of the at least one semiconducting layer(s) 130 that are substantially devoid of the NIC 810, in some examples, the pixel region 2610, such that the conductive coating 830 is deposited on the at least one semiconducting layer(s) 130 to form the second electrode 140.

In some non-limiting examples, the transmissive region 2620 of the device 1910 remains substantially devoid of any materials that may substantially affect the transmission of light therethrough. In particular, as shown in the FIGURE, the TFT structure 200 and/or the first electrode 120 are positioned, in a cross-sectional aspect below the sub-pixel 264x corresponding thereto and beyond the transmissive region 2620. As a result, these components do not attenuate or impede light from being transmitted through the transmissive region 2620. In some non-limiting examples, such arrangement allows a viewer viewing the device 2700 from a typical viewing distance to see through the device 2700, in some non-limiting examples, when all of the (sub-)pixel(s) 340/264x are not emitting, thus creating a transparent AMOLED device 1910.

By providing a transmissive region 2620 that is free and/or substantially devoid of any conductive coating 830, the transmittance in such region may, in some non-limiting examples, be favorably enhanced, by way of non-limiting example, by comparison to the device 2700 of FIG. 27B.

While not shown in the FIGURE, in some non-limiting examples, the device 1910 may further comprise an NPC 1120 disposed between the conductive coating 830 and the at least one semiconducting layer(s) 130. In some non-limiting examples, the NPC 1120 may also be disposed between the NIC 810 and the PDL(s) 440.

In some non-limiting examples, the NIC 810 may be formed concurrently with the at least one semiconducting layer(s) 130. By way of non-limiting example, at least one material used to form the NIC 810 may also be used to form the at least one semiconducting layer(s) 130. In such non-limiting example, a number of stages for fabricating the device 1910 may be reduced.

Those having ordinary skill in the relevant art will appreciate that in some non-limiting examples, various other layers and/or coatings, including without limitation those forming the at least one semiconducting layer(s) 130 and/or the conductive coating 830, may cover a part of the transmissive region 2620, especially if such layers and/or coatings are substantially transparent. In some non-limiting examples, the PDL(s) 440 may have a reduced thickness, including without limitation, by forming a well therein, which in some non-limiting examples is not dissimilar to the well defined for emissive region(s) 1910, to further facilitate light transmission through the transmissive region 2620.

Those having ordinary skill in the relevant art will appreciate that (sub-) pixel(s) 340/264x arrangements other than the arrangement shown in FIGS. 27A and 27C may, in some non-limiting examples, be employed.

Selective Deposition of a Conductive Coating Over Emissive Region(s)

As discussed above, modulating the thickness of an electrode 120, 140, 1750, 4150 in and across a lateral aspect 410 of emissive region(s) 1910 of a (sub-)pixel 340/264x may impact the microcavity effect observable. In some non-limiting examples, selective deposition of at least one conductive coating 830 through deposition of at least one selective coating 710, such as an NIC 810 and/or an NPC 1120, in the lateral aspects 410 of emissive region(s) 1910 corresponding to different sub-pixel(s) 264x in a pixel region 2610 may allow the optical microcavity effect in each emissive region 1910 to be controlled and/or modulated to optimize desirable optical microcavity effects on a sub-pixel 264x basis, including without limitation, an emission spectrum, a luminous intensity and/or an angular dependence of a brightness and/or a color shift of emitted light.

Such effects may be controlled by modulating the thickness of the selective coating 710, such as an NIC 810 and/or an NPC 1120, disposed in each emissive region 1910 of the sub-pixel(s) 264x independently of one another. By way of non-limiting example, the thickness of an NIC 810 disposed over a blue sub-pixel 2643 may be less than the thickness of an NIC 810 disposed over a green sub-pixel 2642, and the thickness of the NIC disposed over a green sub-pixel 2642 may be less than the thickness of an NIC 810 disposed over a red sub-pixel 2641.

In some non-limiting examples, such effects may be controlled to an even greater extent by independently modulating the thickness of not only the selective coating 710, but also the conductive coating 830 deposited in part(s) of each emissive region 1910 of the sub-pixel(s) 264x.

Such a mechanism is illustrated in the schematic diagrams of FIGS. 28A-28D. These diagrams illustrate various stages of manufacturing an example version, shown generally at 2800, of the device 100.

FIG. 28A shows a stage 2810 of manufacturing the device 2800. In the stage 2810, a substrate 110 is provided. The substrate 110 comprises a first emissive region 1910a and a second emissive region 1910b. In some non-limiting examples, the first emissive region 1910a and/or the second emissive region 1910b may be surrounded and/or spaced-apart by at least one non-emissive region 1920a-1920c. In some non-limiting examples, the first emissive region 1910a and/or the second emissive region 1910b may each correspond to a (sub-)pixel 340/264x.

FIG. 28B shows a stage 2820 of manufacturing the device 2800. In the stage 2820, a first conductive coating 830a is deposited on an exposed layer surface 111 of an underlying material, in this case the substrate 110. The first conductive coating 830a is deposited across the first emissive region 1910a and the second emissive region 1910b. In some non-limiting examples, the first conductive coating 830a is deposited across at least one of the non-emissive regions 1920a-1920c.

In some non-limiting examples, the first conductive coating 830a may be deposited using an open mask and/or a mask-free deposition process.

FIG. 28C shows a stage 2830 of manufacturing the device 2800. In the stage 2830, an NIC 810 is selectively deposited over a first portion of the first conductive coating 830a. As shown in the FIGURE, in some non-limiting examples, the NIC 810 is deposited across the first emissive region 1910a, while in some non-limiting examples, the second emissive region 1910b and/or in some non-limiting examples, at least one of the non-emissive regions 1920a-1920c are substantially devoid of the NIC 810.

FIG. 28D shows a stage 2840 of manufacturing the device 2800. In the stage 2840, a second conductive coating 830b may be deposited across those second portions of the device 2800 that is substantially devoid of the NIC 810. In some non-limiting examples, the second conductive coating 830b may be deposited across the second emissive region 1910b and/or, in some non-limiting examples, at least one of the non-emissive region 1920a-1920c.

Those having ordinary skill in the relevant art will appreciate that the evaporative process shown in FIG. 28D and described in detail in connection with any one or more of FIGS. 7-8, 11A-11B and/or 12A-12C may, although not shown, for simplicity of illustration, equally be deposited in any one or more of the preceding stages described in FIGS. 28A-28C.

Those having ordinary skill in the relevant art will appreciate that the manufacture of the device 2800 may in some non-limiting examples, encompass additional stages that are not shown for simplicity of illustration. Such additional stages may include, without limitation, depositing one or more NICs 810, depositing one or more NPCs 1120, depositing one or more additional conductive coatings 830, depositing an outcoupling coating and/or encapsulation of the device 2800.

Those having ordinary skill in the relevant art will appreciate that while the manufacture of the device 2800 has been described and illustrated in connection with a first emissive region 1910a and a second emissive region 1910b, in some non-limiting examples, the principles derived therefrom may equally be deposited on the manufacture of devices having more than two emissive regions 1910.

In some non-limiting examples, such principles may be deposited on deposit conductive coating(s) of varying thickness for emissive region(s) 1910 corresponding to sub-pixel(s) 264x, in some non-limiting examples, in an OLED display device 100, having different emission spectra. In some non-limiting examples, the first emissive region 1910a may correspond to a sub-pixel 264x configured to emit light of a first wavelength and/or emission spectrum and/or in some non-limiting examples, the second emissive region 1910b may correspond to a sub-pixel 264x configured to emit light of a second wavelength and/or emission spectrum. In some non-limiting examples, the device 2800 may comprise a third emissive region 1910c (FIG. 29A) that may correspond to a sub-pixel 264x configured to emit light of a third wavelength and/or emission spectrum.

In some non-limiting examples, the first wavelength may be less than, greater than, and/or equal to at least one of the second wavelength and/or the third wavelength. In some non-limiting examples, the second wavelength may be less than, greater than, and/or equal to at least one of the first wavelength and/or the third wavelength. In some non-limiting examples, the third wavelength may be less than, greater than and/or equal to at least one of the first wavelength and/or the second wavelength.

In some non-limiting examples, the device 2800 may also comprise at least one additional emissive region 1910 (not shown) that may in some non-limiting examples be configured to emit light having a wavelength and/or emission spectrum that is substantially identical to at least one of the first emissive region 1910a, the second emissive region 1910b and/or the third emissive region 1910c.

In some non-limiting examples, the NIC 810 may be selectively deposited using a shadow mask that may also have been used to deposit the at least one semiconducting layer 130 of the first emissive region 1910a. In some non-limiting examples, such shared use of a shadow mask may allow the optical microcavity effect(s) to be tuned for each sub-pixel 264x in a cost-effective manner.

The use of such mechanism to create an example version 2900 of the device 100 having sub-pixel(s) 264x of a given pixel 340 with modulated microcavity effects is described in FIGS. 29A-29D.

In FIG. 29A, a stage 2810 of manufacture of the device 2900 is shown as comprising a substrate 110, a TFT insulating layer 280 and a plurality of first electrodes 120a-120c, formed on a surface of the TFT insulating layer 280.

The substrate 110 may comprise the base substrate 112 (not shown for purposes of simplicity of illustration) and/or at least one TFT structure 200a-200c corresponding to and for driving an emissive region 1910a-1910c each having a corresponding sub-pixel 264x, positioned substantially thereunder and electrically coupled to its associated first electrode 120a-120c. PDL(s) 440a-440d are formed over the substrate 110, to define emissive region(s) 830a-1910c. The PDL(s) 440a-440d cover edges of their respective first electrodes 120a-120c.

In some non-limiting examples, at least one semiconducting layer 130a-130c is deposited over exposed region(s) of their respective first electrodes 120a-120c and, in some non-limiting examples, at least parts of the surrounding PDLs 440a-440d.

In some non-limiting examples, a first conductive coating 830a may be deposited over the at least one semiconducting layer(s) 130a-130c. In some non-limiting examples, the first conductive coating 830a may be deposited using an open mask and/or mask-free deposition process. In some non-limiting examples, such deposition may be effected by exposing the entire exposed layer surface 111 of the device 2900 to a vapor flux of the first conductive coating 830a, which in some non-limiting examples may be Mg, to deposit the first conductive coating 830a over the at least one semiconducting layer(s) 130a-130c to form a first layer of the second electrode 140a (not shown), which in some non-limiting examples may be a common electrode, at least for the first emissive region 1910a. Such common electrode has a first thickness t_c1 in the first emissive region 1910a. The first thickness t_c1 may correspond to a thickness of the first conductive coating 830a.

In some non-limiting examples, a first NIC 810a is selectively deposited over first portions of the device 2810, comprising the first emissive region 1910a.

In some non-limiting examples, a second conductive coating 830b may be deposited over the device 2900. In some non-limiting examples, the second conductive coating 830b may be deposited using an open mask and/or mask-free deposition process. In some non-limiting examples, such deposition may be effected by exposing the entire exposed layer surface 111 of the device 2810 to a vapour flux of the second conductive coating 830b, which in some non-limiting examples may be Mg, to deposit the second conductive coating 830b over the first conductive coating 830a that is substantially devoid of the first NIC 810a, in some examples, the second and third emissive region 1910b, 1910c and/or at least part(s) of the non-emissive region(s) 1920 in which the PDLs 440a-440d lie, such that the second conductive coating 830b is deposited on the second portion(s) of the first conductive coating 830a that are substantially devoid of the first NIC 810a to form a second layer of the second electrode 140b (not shown), which in some non-limiting examples, may be a common electrode, at least for the second emissive region 1910b. Such common electrode has a second thickness t_c2 in the second emissive region 1910b. The second thickness t_c2 may correspond to a combined thickness of the first conductive coating 830a and of the second conductive coating 830b and may in some non-limiting examples be greater than the first thickness t_c1.

In FIG. 29B, a stage 2920 of manufacture of the device 2900 is shown.

In some non-limiting examples, a second NIC 810b is selectively deposited over further first portions of the device 2900, comprising the second emissive region 1910b.

In some non-limiting examples, a third conductive coating 830c may be deposited over the device 2900. In some non-limiting examples, the third conductive coating 830c may be deposited using an open mask and/or mask-free deposition process. In some non-limiting examples, such deposition may be effected by exposing the entire exposed layer surface 111 of the device 2900 to a vapour flux of the third conductive coating 830c, which in some non-limiting examples may be Mg, to deposit the third conductive coating 830c over the second conductive coating 830b that is substantially devoid of either the first NIC 810a or the second NIC 810b, in some examples, the third emissive region 1910c and/or at least part(s) of the non-emissive region 1920 in which the PDLs 440a-440d lie, such that the third conductive coating 830c is deposited on the further second portion(s) of the second conductive coating 830b that are substantially devoid of the second NIC 810b to form a third layer of the second electrode 140c (not shown), which in some non-limiting examples, may be a common electrode, at least for the third emissive region 1910c. Such common electrode has a third thickness t_c3 in the third emissive region 1910c. The third thickness t_c3 may correspond to a combined thickness of the first conductive coating 830a, the second conductive coating 830b and the third conductive coating 830c and may in some non-limiting examples be greater than either or both of the first thickness t_c1 and the second thickness t_c2.

In FIG. 28C, a stage 2830 of manufacture of the device 2900 is shown.

In some non-limiting examples, a third NIC 810c is selectively deposited over additional first portions of the device 2900, comprising the third emissive region 1910b.

In FIG. 29D, a stage 2940 of manufacture of the device 2900 is shown.

In some non-limiting examples, at least one auxiliary electrode 1750 is disposed in the non-emissive region(s) 1920 of the device 2900 between neighbouring emissive region 1910a-1910c thereof and in some non-limiting examples, over the PDLs 440a-440d. In some non-limiting examples, the conductive coating 830 used to deposit the at least one auxiliary electrode 1750 may be deposited using an open mask and/or mask-free deposition process. In some non-limiting examples, such deposition may be effected by exposing the entire exposed layer surface 111 of the device 2900 to a vapour flux of the conductive coating 830, which in some non-limiting examples may be Mg, to deposit the conductive coating 830 over the exposed parts of the first conductive coating 830a, the second conductive coating 830b and the third conductive coating 830c that is substantially devoid of any of the first NIC 810a the second NIC 810b and/or the third NIC 810c, such that the conductive coating 830 is deposited on an additional second portion comprising the exposed part(s) of the first conductive coating 830a, the second conductive coating 830b and/or the third conductive coating 830c that are substantially devoid of any of the first NIC 810a, the second NIC 810b and/or the third NIC 810c to form the at least one auxiliary electrode 1750. Each of the at least one auxiliary electrode 1750 is electrically coupled to a respective one of the second electrodes 140a-140c. In some non-limiting examples, each of the at least one auxiliary electrode 1750 is in physical contact with such second electrode 140a-140c.

In some non-limiting examples, the first emissive region 1910a, the second emissive region 1910b and the third emissive region 1910c may be substantially devoid of the material used to form the at least one auxiliary electrode 1750.

In some non-limiting examples, at least one of the first conductive coating 830a, the second conductive coating 830b and/or the third conductive coating 830c may be transmissive and/or substantially transparent in at least a part of the visible wavelength range of the electromagnetic spectrum. Thus, if the second conductive coating 830b and/or the third conductive coating 830a (and/or any additional conductive coating(s) 830) is disposed on top of the first conductive coating 830a to form a multi-coating electrode 120, 140, 1750 that may also be transmissive and/or substantially transparent in at least a part of the visible wavelength range of the electromagnetic spectrum. In some non-limiting examples, the transmittance of any one or more of the first conductive coating 830a, the second conductive coating 830b, the third conductive coating 830c, any additional conductive coating(s) 830, and/or the multi-coating electrode 120, 140, 1750 may be greater than about 30%, greater than about 40% greater than about 45%, greater than about 50%, greater than about 60%, greater than about 70%, greater than about 75%, and/or greater than about 80% in at least a part of the visible wavelength range of the electromagnetic spectrum.

In some non-limiting examples, a thickness of the first conductive coating 830a, the second conductive coating 830b and/or the third conductive coating 830c may be made relatively thin to maintain a relatively high transmittance. In some non-limiting examples, the thickness of the first conductive coating 830a may be about 5 to 30 nm, about 8 to 25 nm, and/or about 10 to 20 nm. In some non-limiting examples, the thickness of the second conductive coating 830b may be about 1 to 25 nm, about 1 to 20 nm, about 1 to 15 nm, about 1 to 10 nm, and/or about 3 to 6 nm. In some non-limiting examples, the thickness of the third conductive coating 830c may be about 1 to 25 nm, about 1 to 20 nm, about 1 to 15 nm, about 1 to 10 nm, and/or about 3 to 6 nm. In some non-limiting examples, the thickness of a multi-coating electrode formed by a combination of the first conductive coating 830a, the second conductive coating 830b, the third conductive coating 830c and/or any additional conductive coating(s) 830 may be about 6 to 35 nm, about 10 to 30 nm, about 10 to 25 nm and/or about 12 to 18 nm.

In some non-limiting examples, a thickness of the at least one auxiliary electrode 1750 may be greater than the thickness of the first conductive coating 830a, the second conductive coating 830b, the third conductive coating 830c and/or a common electrode. In some non-limiting examples, the thickness of the at least one auxiliary electrode 1750 may be greater than about 50 nm, greater than about 80 nm, greater than about 100 nm, greater than about 150 nm, greater than about 200 nm, greater than about 300 nm, greater than about 400 nm, greater than about 500 nm, greater than about 700 nm, greater than about 800 nm, greater than about 1 μm, greater than about 1.2 μm, greater than about 1.5 μm, greater than about 2 μm, greater than about 2.5 μm, and/or greater than about 3 μm.

In some non-limiting examples, the at least one auxiliary electrode 1750 may be substantially non-transparent and/or opaque. However, since the at least one auxiliary electrode 1750 may be in some non-limiting examples provided in a non-emissive region 1920 of the device 2900, the at least one auxiliary electrode 1750 may not cause or contribute to significant optical interference. In some non-limiting examples, the transmittance of the at least one auxiliary electrode 1750 may be less than about 50%, less than about 70%, less than about 80%, less than about 85%, less than about 90%, and/or less than about 95% in at least a part of the visible wavelength range of the electromagnetic spectrum.

In some non-limiting examples, the at least one auxiliary electrode 1750 may absorb light in at least a part of the visible wavelength range of the electromagnetic spectrum.

In some non-limiting examples, a thickness of the first NIC 810a, the second NIC 810b, and/or the third NIC 810c disposed in the first emissive region 1910a, the second emissive region 1910b and/or the third emissive region 1910c respectively, may be varied according to a colour and/or emission spectrum of light emitted by each emissive region 1910a-1910c. As shown in FIGS. 29C-29D, the first NIC 810a may have a first NIC thickness t_n1, the second NIC 810b may have a second NIC thickness t_n2 and/or the third NIC 810c may have a third NIC thickness t_n3. In some non-limiting examples, the first NIC thickness t_n1, the second NIC thickness t_n2 and/or the third NIC thickness t_n3 may be substantially the same as one another. In some non-limiting examples, the first NIC thickness t_n1, the second NIC thickness t_n2 and/or the third NIC thickness t_n3 may be different from one another.

In some non-limiting examples, the device 2900 may also comprise any number of emissive regions 1910a-1910c and/or (sub-)pixel(s) 340/264x thereof. In some non-limiting examples, a device may comprise a plurality of pixels 340, wherein each pixel 340 comprises two, three or more sub-pixel(s) 264x.

Those having ordinary skill in the relevant art will appreciate that the specific arrangement of (sub-)pixel(s) 340/264x may be varied depending on the device design. In some non-limiting examples, the sub-pixel(s) 264x may be arranged according to known arrangement schemes, including without limitation, RGB side-by-side, diamond and/or PenTile®.

Conductive Coating for Electrically Coupling an Electrode to an Auxiliary Electrode

Turning to FIG. 30, there is shown a cross-sectional view of an example version 3000 of the device 100. The device 3000 comprises in a lateral aspect, an emissive region 1910 and an adjacent non-emissive region 1920.

In some non-limiting examples, the emissive region 1910 corresponds to a sub-pixel 264x of the device 3000. The emissive region 1910 has a substrate 110, a first electrode 120, a second electrode 140 and at least one semiconducting layer 130 arranged therebetween.

The first electrode 120 is disposed on an exposed layer surface 111 of the substrate 110. The substrate 110 comprises a TFT structure 200, that is electrically coupled to the first electrode 120. The edges and/or perimeter of the first electrode 120 is generally covered by at least one PDL 440.

The non-emissive region 1920 has an auxiliary electrode 1750 and a first part of the non-emissive region 1920 has a projecting structure 3060 arranged to project over and overlap a lateral aspect of the auxiliary electrode 1750. The projecting structure 3060 extends laterally to provide a sheltered region 3065. By way of non-limiting example, the projecting structure 3060 may be recessed at and/or near the auxiliary electrode 1750 on at least one side to provide the sheltered region 3065. As shown, the sheltered region 3065 may in some non-limiting examples, correspond to a region on a surface of the PDL 440 that overlaps with a lateral projection of the projecting structure 3060. The non-emissive region 1920 further comprises a conductive coating 830 disposed in the sheltered region 3065. The conductive coating 830 electrically couples the auxiliary electrode 1750 with the second electrode 140.

An NIC 810a is disposed in the emissive region 1910 over the exposed layer surface 111 of the second electrode 140. In some non-limiting examples, an exposed layer surface 111 of the projecting structure 3060 is coated with a residual thin conductive film 3040 from deposition of a thin conductive film to form the second electrode 140. In some non-limiting examples, a surface of the residual thin conductive film 3040 is coated with a residual NIC 810b from deposition of the NIC 810.

However, because of the lateral projection of the projecting structure 3060 over the sheltered region 3065, the sheltered region 3065 is substantially devoid of NIC 810. Thus, when a conductive coating 830 is deposited on the device 3000 after deposition of the NIC 810, the conductive coating 830 is deposited on and/or migrates to the sheltered region 3065 to couple the auxiliary electrode 1750 to the second electrode 140.

Those having ordinary skill in the relevant art will appreciate that a non-limiting example has been shown in FIG. 30 and that various modifications may be apparent. By way of non-limiting example, the projecting structure 3060 may provide a sheltered region 3065 along at least two of its sides. In some non-limiting examples, the projecting structure 3060 may be omitted and the auxiliary electrode 1750 may include a recessed portion that defines the sheltered region 3065. In some non-limiting examples, the auxiliary electrode 1750 and the conductive coating 830 may be disposed directly on a surface of the substrate 110, instead of the PDL 440.

Selective Deposition of Optical Coating

In some non-limiting examples, a device 100 (not shown), which in some non-limiting examples may be an opto-electronic device, comprises a substrate 110, an NIC 810 and an optical coating. The NIC 810 covers a first lateral portion of the substrate 110. The optical coating covers a second lateral portion of the substrate. At least a part of the NIC 810 is substantially devoid of the optical coating.

In some non-limiting examples, the optical coating may be used to modulate optical properties of light being transmitted, emitted and/or absorbed by the device 100, including without limitation, plasmon modes. By way of non-limiting example, the optical coating may be used as an optical filter, index-matching coating, optical out-coupling coating, scattering layer, diffraction grating, and/or parts thereof.

In some non-limiting examples, the optical coating may be used to modulate at least one optical microcavity effect in the device 100 by, without limitation, tuning the total optical path length and/or the refractive index thereof. At least one optical property of the device 100 may be affected by modulating at least one optical microcavity effect including without limitation, the output light, including without limitation, an angular dependence of a brightness and/or a color shift thereof. In some non-limiting examples, the optical coating may be a non-electrical component, that is, the optical coating may not be configured to conduct and/or transmit electrical current during normal device operations.

In some non-limiting examples, the optical coating may be formed of any material used as a conductive coating 830 and/or employing any mechanism of depositing a conductive coating 830 as described herein.

Edge Effects of NICs and Conductive Coatings

FIGS. 31A-31I describe various potential behaviours of NICs 810 at a deposition interface with conductive coatings 830.

Turning to FIG. 31A, there is shown a first example of a part of an example version 3100 of the device 100 at an NIC deposition boundary. The device 3100 comprises a substrate 110 having a layer surface 111. An NIC 810 is deposited over a first portion 3110 of the layer surface 111. A conductive coating 830 is deposited over a second portion 3120 of the layer surface 111. As shown, by way of non-limiting example, the first portion 3110 and the second portion 3120 are distinct and non-overlapping portions of the layer surface 111.

The conductive coating 830 comprises a first part 830a and a remaining part 830b. As shown, by way of non-limiting example, the first part 830a of the conductive coating 830 substantially covers the second portion 3120 and the second part 830b of the conductive coating 830 partially projects over and/or overlaps a first part of the NIC 810.

In some non-limiting examples, since the NIC 810 is formed such that its surface 3111 exhibits a relatively low affinity or initial sticking probability S₀ for a material used to form the conductive coating 830, there is a gap 3129 formed between the projecting and/or overlapping second part 830b of the conductive coating 830 and the surface 3111 of the NIC 810. As a result, the second part 830b is not in physical contact with the NIC 810 but is spaced-apart therefrom by the gap 3129 in a cross-sectional aspect. In some non-limiting examples, the first part 830a of the conductive coating 830 may be in physical contact with the NIC 810 at an interface and/or boundary between the first portion 3110 and the second portion 3120.

In some non-limiting examples, the projecting and/or overlapping second part 830b of the conductive coating 830 may extend laterally over the NIC 810 by a comparable extent as a thickness t₁ of the conductive coating 830. By way of non-limiting example, as shown, a width w₂ of the second part 830b may be comparable to the thickness t₁. In some non-limiting examples, a ratio of w₂:t₁ may be in a range of about 1:1 to about 1:3, about 1:1 to about 1:1.5, and/or about 1:1 to about 1:2. While the thickness t₁ may in some non-limiting examples be relatively uniform across the conductive coating 830, in some non-limiting examples, the extent to which the second part 830b projects and/or overlaps with the NIC 810 (namely w₂) may vary to some extent across different parts of the layer surface 111.

Turning now to FIG. 31B, the conductive coating 830 is shown to include a third part 830c disposed between the second part 830b and the NIC 810. As shown, the second part 830b of the conductive coating 830 extends laterally over and is spaced apart from the third part 830c of the conductive coating 830 and the third part 830c may be in physical contact with the surface 3111 of the NIC 810. A thickness t₃ of the third part 830c of the conductive coating 830 may be less and in some non-limiting examples, substantially less than the thickness t₁ of the first part 830a thereof. In some non-limiting examples, a width w₃ of the third part 830c may be greater than the width w₂ of the second part 830b. In some non-limiting examples, the third part 830c may extend laterally to overlap the NIC 810 to a greater extent than the second part 830b. In some non-limiting examples, a ratio of w₃:t₁ may be in a range of about 1:2 to about 3:1 and/or about 1:1.2 to about 2.5:1. While the thickness t₁ may in some non-limiting examples be relatively uniform across the conductive coating 830, in some non-limiting examples, the extent to which the third part 830c projects and/or overlaps with the NIC 810 (namely w₃) may vary to some extent across different parts of the layer surface 111.

The thickness t₃ of the third part 830c may be no greater than and/or less than about 5% of the thickness t₁ of the first part 830a. By way of non-limiting example, t₃ may be no greater than and/or less than about 4%, no greater than and/or less than about 3%, no greater than and/or less than about 2%, no greater than and/or less than about 1%, and/or no greater than and/or less than about 0.5% of t₁. Instead of, and/or in addition to, the third part 830c being formed as a thin film, as shown, the material of the conductive coating 830 may form as islands and/or disconnected clusters on a part of the NIC 810. By way of non-limiting example, such islands and/or disconnected clusters may comprise features that are physically separated from one another, such that the islands and/or clusters do not form a continuous layer.

Turning now to FIG. 31C, an NPC 1120 is disposed between the substrate 110 and the conductive coating 830. The NPC 1120 is disposed between the first part 830a of the conductive coating 830 and the second portion 3120 of the substrate 110. The NPC 1120 is illustrated as being disposed on the second portion 3120 and not on the first portion 3110, where the NIC 810 has been deposited. The NPC 1120 may be formed such that, at an interface and/or boundary between the NPC 1120 and the conductive coating 830, a surface of the NPC 1120 exhibits a relatively high affinity or initial sticking probability S₀ for the material of the conductive coating 830. As such, the presence of the NPC 1120 may promote the formation and/or growth of the conductive coating 830 during deposition.

Turning now to FIG. 31D, the NPC 1120 is disposed on both the first portion 3110 and the second portion 3120 of the substrate 110 and the NIC 810 covers a part of the NPC 1120 disposed on the first portion 3110. Another part of the NPC 1120 is substantially devoid of the NIC 810 and the conductive coating 830 covers such part of the NPC 1120.

Turning now to FIG. 31E, the conductive coating 830 is shown to partially overlap a part of the NIC 810 in a third portion 3130 of the substrate 110. In some non-limiting examples, in addition to the first part 830a and the second part 830b, the conductive coating 830 further includes a fourth part 830d. As shown, the fourth part 830d of the conductive coating 830 is disposed between the first part 830a and the second part 830b of the conductive coating 830 and the fourth part 830d may be in physical contact with the layer surface 3111 of the NIC 810. In some non-limiting examples, the overlap in the third portion 3130 may be formed as a result of lateral growth of the conductive coating 830 during an open mask and/or mask-free deposition process. In some non-limiting examples, while the layer surface 3111 of the NIC 810 may exhibit a relatively low initial sticking probability S₀ for the material of the conductive coating 830, and thus the probability of the material nucleating the layer surface 3111 is low, as the conductive coating 830 grows in thickness, the conductive coating 830 may also grow laterally and may cover a subset of the NIC 810 as shown.

Turning now to FIG. 31F the first portion 3110 of the substrate 110 is coated with the NIC 810 and the second portion 3120 adjacent thereto is coated with the conductive coating 830. In some non-limiting examples, it has been observed that conducting an open mask and/or mask-free deposition of the conductive coating 830 may result in the conductive coating 830 exhibiting a tapered cross-sectional profile at and/or near an interface between the conductive coating 830 and the NIC 810.

In some non-limiting examples, a thickness of the conductive coating 830 at and/or near the interface may be less than an average thickness of the conductive coating 830. While such tapered profile is shown as being curved and/or arched, in some non-limiting examples, the profile may, in some non-limiting examples be substantially linear and/or non-linear. By way of non-limiting example, the thickness of the conductive coating 830 may decrease, without limitation, in a substantially linear, exponential and/or quadratic fashion in a region proximal to the interface.

It has been observed that a contact angle θ_c of the conductive coating 830 at and/or near the interface between the conductive coating 830 and the NIC 810 may vary, depending on properties of the NIC 810, such as a relative affinity and/or an initial sticking probability S₀. It is further postulated that the contact angle θ_c of the nuclei may in some non-limiting examples, dictate the thin film contact angle of the conductive coating 830 formed by deposition. Referring to FIG. 31F by way of non-limiting example, the contact angle θ_c may be determined by measuring a slope of a tangent of the conductive coating 830 at or near the interface between the conductive coating 830 and the NIC 810. In some non-limiting examples, where the cross-sectional taper profile of the conductive coating 830 is substantially linear, the contact angle θ_c may be determined by measuring the slope of the conductive coating 830 at and/or near the interface. As will be appreciated by those having ordinary skill in the relevant art, the contact angle θ_c may be generally measured relative to an angle of the underlying surface. In the present disclosure, for purposes of simplicity of illustration, the coatings 810, 830 are shown deposited on a planar surface. However, those having ordinary skill in the relevant art will appreciate that such coatings 810, 830 may be deposited on non-planar surfaces.

In some non-limiting examples, the contact angle θ_c of the conductive coating 830 may be greater than about 90°. Referring now to FIG. 31G, by way of non-limiting example, the conductive coating 830 is shown as including a part extending past the interface between the NIC 810 and the conductive coating 830 and is spaced apart from the NIC by a gap 3129. In such non-limiting scenario, the contact angle θ_c may, in some non-limiting examples, be greater than about 90°.

In some non-limiting examples, it may be advantageous to form a conductive coating 830 exhibiting a relatively high contact angle θ_c. By way of non-limiting example, the contact angle θ_c may be greater than about 10°, greater than about 15°, greater than about 20°, greater than about 25°, greater than about 30°, greater than about 35°, greater than about 40°, greater than about 50°, greater than about 70°, greater than about 70°, greater than about 75°, and/or greater than about 80°. By way of non-limiting example, a conductive coating 830 having a relatively high contact angle θ_c may allow for creation of finely patterned features while maintaining a relatively high aspect ratio. By way of non-limiting example, it may be desirable to form a conductive coating 830 exhibiting a contact angle θ_c greater than about 90°. By way of non-limiting example, the contact angle θ_c may be greater than about 90°, greater than about 95°, greater than about 100°, greater than about 105°, greater than about 110° greater than about 120°, greater than about 130°, greater than about 135°, greater than about 140°, greater than about 145°, greater than about 150° and/or greater than about 170°.

Turning now to FIGS. 31H-31I, the conductive coating 830 partially overlaps a part of the NIC 810 in the third portion 3130 of the substrate 100, which is disposed between the first portion 3110 and the second portion 3120 thereof. As shown, the subset of the conductive coating 830 partially overlapping a subset of the NIC 810 may be in physical contact with the surface 3111 thereof. In some non-limiting examples, the overlap in the third region 3130 may be formed as a result of lateral growth of the conductive coating 830 during an open mask and/or mask-free deposition process. In some non-limiting examples, while the surface 3111 of the NIC 810 may exhibit a relatively low affinity or initial sticking probability S₀ for the material of the conductive coating 830 and thus the probability of the material nucleating on the layer surface 3111 is low, as the conductive coating 830 grows in thickness, the conductive coating 830 may also grow laterally and may cover a subset of the NIC 810.

In the case of FIGS. 31H-31I, the contact angle θ_c of the conductive coating 830 may be measured at an edge thereof near the interface between it and the NIC 810, as shown. In FIG. 31I, the contact angle θ_c may be greater than about 90°, which may in some non-limiting examples result in a subset of the conductive coating 830 being spaced apart from the NIC 810 by a gap 3129.

Partition and Recess

Turning to FIG. 32, there is shown a cross-sectional view of an example version 3200 of the device 100. The device 3200 comprises a substrate 110 having a layer surface 111. The substrate 110 comprises at least one TFT structure 200. By way of non-limiting example, the at least one TFT structure 200 may be formed by depositing and patterning a series of thin films when fabricating the substrate 110, in some non-limiting examples, as described herein.

The device 3200 comprises, in a lateral aspect, an emissive region 1910 having an associated lateral aspect 410 and at least one adjacent non-emissive region 1920, each having an associated lateral aspect 420. The layer surface 111 of the substrate 110 in the emissive region 1910 is provided with a first electrode 120, that is electrically coupled to the at least one TFT structure 200. A PDL 440 is provided on the layer surface 111, such that the PDL 440 covers the layer surface 111 as well as at least one edge and/or perimeter of the first electrode 120. The PDL 440 may, in some non-limiting examples, be provided in the lateral aspect 420 of the non-emissive region 1920. The PDL 440 defines a valley-shaped configuration that provides an opening that generally corresponds to the lateral aspect 410 of the emissive region 1910 through which a layer surface of the first electrode 120 may be exposed. In some non-limiting examples, the device 3200 may comprise a plurality of such openings defined by the PDLs 400, each of which may correspond to a (sub-)pixel 340/264x region of the device 3200.

As shown, in some non-limiting examples, a partition 3221 is provided on the layer surface 111 in the lateral aspect 420 of a non-emissive region 1920 and, as described herein, defines a sheltered region 3065, such as a recess 3222. In some non-limiting examples, the recess 3222 may be formed by an edge of a lower section 3323 (FIG. 33A) of the partition 3221 being recessed, staggered and/or offset with respect to an edge of an upper section 3324 (FIG. 33A) of the partition 3221 that overlaps and/or projects beyond the recess 3222.

In some non-limiting examples, the lateral aspect 410 of the emissive region 1910 comprises at least one semiconducting layer 130 disposed over the first electrode 120, a second electrode 140, disposed over the at least one semiconducting layer 130, and an NIC 810 disposed over the second electrode 140. In some non-limiting examples, the at least one semiconducting layer 130, the second electrode 140 and the NIC 810 may extend laterally to cover at least the lateral aspect 420 of a part of at least one adjacent non-emissive region 1920. In some non-limiting examples, as shown, the at least one semiconducting layer 130, the second electrode 140 and the NIC 810 may be disposed on at least a part of at least one PDL 440 and at least a part of the partition 3221. Thus, as shown, the lateral aspect 410 of the emissive region 1910, the lateral aspect 420 of a part of at least one adjacent non-emissive region 1920 and a part of at least one PDL 440 and at least a part of the partition 3221, together can make up a first portion, in which the second electrode 140 lies between the NIC 810 and the at least one semiconducting layer 130.

An auxiliary electrode 1750 is disposed proximate to and/or within the recess 3221 and a conductive coating 830 is arranged to electrically couple the auxiliary electrode 1750 to the second electrode 140. Thus as shown, the recess 3221 may comprise a second portion, in which the conductive coating 830 is disposed on the layer surface 111.

A non-limiting example of a method for fabricating the device 3200 is now described.

In a stage, the method provides the substrate 110 and at least one TFT structure 200. In some non-limiting examples, at least some of the materials for forming the at least one semiconducting layer 130 may be deposited using an open-mask and/or mask-free deposition process, such that the materials are deposited in and/or across both the lateral aspect 410 of both the emissive region 1910 and/or the lateral aspect 420 of at least a part of at least one non-emissive region 1920. Those having ordinary skill in the relevant art will appreciate that in some non-limiting examples, it may be appropriate to deposit the at least one semiconducting layer 130 in such manner so as to reduce any reliance on patterned deposition, which in some non-limiting examples, is performed using an FMM.

In a stage, the method deposits the second electrode 140 over the at least one semiconducting layer 130. In some non-limiting examples, the second electrode 140 may be deposited using an open-mask and/or mask-free deposition process. In some non-limiting examples, the second electrode 140 may be deposited by subjecting an exposed layer surface 111 of the at least one semiconducting layer 130 disposed in the lateral aspect 410 of the emissive region 1910 and/or the lateral aspect 420 of at least a part of at least one of the non-emissive region 1920 to an evaporated flux of a material for forming the second electrode 130.

In a stage, the method deposits the NIC 810 over the second electrode 140. In some non-limiting examples, the NIC 810 may be deposited using an open-mask and/or mask-free deposition process. In some non-limiting examples, the NIC 810 may be deposited by subjecting an exposed layer surface 111 of the second electrode 140 disposed in the lateral aspect 410 of the emissive region 1910 and/or the lateral aspect 420 of at least a part of at least one of the non-emissive region 1920 to an evaporated flux of a material for forming the NIC 810.

As shown, the recess 3222 is substantially free of, or is uncovered by the NIC 810. In some non-limiting examples, this may be achieved by masking, by the partition 3221, a recess 3222, in a lateral aspect thereof, such that the evaporated flux of a material for forming the NIC 810 is substantially precluded from being incident onto such recess 3222 of the layer surface 111. Accordingly, in such example, the recess 3222 of the layer surface 111 is substantially devoid of the NIC 810. By way of non-limiting example, a laterally projecting part of the partition 3221 may define the recess 3222 at a base of the partition 3221. In such example, at least one surface of the partition 3221 that defines the recess 3222 may also be substantially devoid of the NIC 810.

In a stage, the method deposits the conductive coating 830, in some non-limiting examples, after providing the NIC 810, on the device 3200. In some non-limiting examples, the conductive coating 830 may be deposited using an open-mask and/or mask-free deposition process. In some non-limiting examples, the conductive coating 830 may be deposited by subjecting the device 3200 to an evaporated flux of a material for forming the conductive coating 830. By way of non-limiting example, a source (not shown) of conductive coating 830 material may be used to direct an evaporated flux of material for forming the conductive coating 830 towards the device 3200, such that the evaporated flux is incident on such surface. However, in some non-limiting examples, the surface of the NIC 810 disposed in the lateral aspect 410 of the emissive region 1910 and/or the lateral aspect 420 of at least a part of at least one of the non-emissive region 1920 exhibits a relatively low initial sticking probability S₀, for the conductive coating 830, the conductive coating 830 may selectively deposit onto a second portion, including without limitation, the recessed portion of the device 3200, where the NIC 810 is not present.

In some non-limiting examples, at least a part of the evaporated flux of the material for forming the conductive coating 830 may be directed at a non-normal angle relative to a lateral plane of the layer surface 111. By way of non-limiting example, at least a part of the evaporated flux may be incident on the device 3200 at an angle of incidence that is, relative to such lateral plane of the layer surface 111, less than 90°, less than about 85°, less than about 80°, less than about 75°, less than about 70°, less than about 60°, and/or less than about 50°. By directing an evaporated flux of a material for forming the conductive coating 830, including at least a part thereof incident at a non-normal angle, at least one surface of and/or in the recess 3222 may be exposed to such evaporated flux.

In some non-limiting examples, a likelihood of such evaporated flux being precluded from being incident onto at least one surface of and/or in the recess 3222 due to the presence of the partition 3221, may be reduced since at least a part of such evaporated flux may be flowed at a non-normal angle of incidence.

In some non-limiting examples, at least a part of such evaporated flux may be non-collimated. In some non-limiting examples, at least a part of such evaporated flux may be generated by an evaporation source that is a point source, a linear source and/or a surface source.

In some non-limiting examples, the device 3200 may be displaced during deposition of the conductive coating 830. By way of non-limiting example, the device 3200 and/or the substrate 110 thereof and/or any layer(s) deposited thereon, may be subjected to a displacement that is angular, in a lateral aspect and/or in an aspect substantially parallel to the cross-sectional aspect.

In some non-limiting examples, the device 3200 may be rotated about an axis that substantially normal to the lateral plane of the layer surface 111 while being subjected to the evaporated flux.

In some non-limiting examples, at least a part of such evaporated flux may be directed toward the layer surface 111 of the device 3200 in a direction that is substantially normal to the lateral plane of the surface.

Without wishing to be bound by a particular theory, it is postulated that the material for forming the conductive coating 830 may nevertheless be deposited within the recess 3222 due to lateral migration and/or desorption of adatoms adsorbed onto the surface of the NIC 810. In some non-limiting examples, it is postulated that any adatoms adsorbed onto the surface of the NIC 810 may have a tendency to migrate and/or desorb from such surface due to unfavorable thermodynamic properties of the surface for forming a stable nucleus. In some non-limiting examples, it is postulated that at least some of the adatoms migrating and/or desorbing off such surface may be re-deposited onto the surfaces in the recess 3222 to form the conductive coating 830.

In some non-limiting examples, the conductive coating 830 may be formed such that the conductive coating 830 is electrically coupled to both the auxiliary electrode 1750 and the second electrode 140. In some non-limiting examples, the conductive coating 830 is in physical contact with at least one of the auxiliary electrode 1750 and/or the second electrode 140. In some non-limiting examples, an intermediate layer may be present between the conductive coating 830 and at least one of the auxiliary electrode 1750 and/or the second electrode 140. However, in such example, such intermediate layer may not substantially preclude the conductive coating 830 from being electrically coupled to the at least one of the auxiliary electrode 1750 and/or the second electrode 140. In some non-limiting examples, such intermediate layer may be relatively thin and be such as to permit electrical coupling therethrough. In some non-limiting examples, a sheet resistance of the conductive coating 830 may be equal to and/or less than a sheet resistance of the second electrode 140.

As shown in FIG. 32, the recess 3222 is substantially devoid of the second electrode 140. In some non-limiting examples, during the deposition of the second electrode 140, the recess 3222 is masked, by the partition 3221, such that the evaporated flux of the material for forming the second electrode 140 is substantially precluded form being incident on at least one surface of and/or in the recess 3222. In some non-limiting examples, at least a part of the evaporated flux of the material for forming the second electrode 140 is incident on at least one surface of and/or in the recess 3222, such that the second electrode 140 extends to cover at least a part of the recess 3222.

In some non-limiting examples, the auxiliary electrode 1750, the conductive coating 830 and/or the partition 3221 may be selectively provided in certain region(s) of a display panel. In some non-limiting examples, any of these features may be provided at and/or proximate to one or more edges of such display panel for electrically coupling at least one element of the frontplane 10, including without limitation, the second electrode 140, to at least one element of the backplane 20. In some non-limiting example, providing such features at and/or proximate to such edges may facilitate supplying and distributing electrical current to the second electrode 140 from an auxiliary electrode 1750 located at and/or proximate to such edges. In some non-limiting examples, such configuration may facilitate reducing a bezel size of the display panel.

In some non-limiting examples, the auxiliary electrode 1750, the conductive coating 830 and/or the partition 3221 may be omitted from certain regions(s) of such display panel. In some non-limiting examples, such features may be omitted from parts of the display panel, including without limitation, where a relatively high pixel density is to be provided, other than at and/or proximate to at least one edge thereof.

FIG. 33A shows a fragment of the device 3200 in a region proximal to the partition 3221 and at a stage prior to deposition of the at least one semiconducting layer 130. In some non-limiting examples, the partition 3221 comprises a lower section 3323 and an upper section 3324, with the upper section 3324 projecting over the lower section 3323, so as to form the recess 3222 where the lower section 3323 is laterally recessed relative to the upper section 3324. By way of non-limiting example, the recess 3222 may be formed such that it extends substantially laterally into the partition 3221. In some non-limiting examples, the recess 3221 may correspond to a space defined between a ceiling 3325 defined by the upper section 3324, a side 3326 of the lower section 3323 and a floor 3327 corresponding to the layer surface 111 of the substrate 110. In some non-limiting examples, the upper section 3324 comprises an angled section 3328. By way of non-limiting example, the angled section 3328 may be provided by a surface that is not substantially parallel to a lateral plane of the layer surface 111. By way of non-limiting example, the angled section may be tilted and/or offset from an axis that is substantially normal to the layer surface 111 by an angle θ_p. A lip 3329 is also provided by the upper section 3324. In some non-limiting examples, the lip 3329 may be provided at or near an opening of the recess 3222. By way of non-limiting example, the lip 3329 may be provided at a junction of the angled section 3328 and the ceiling 3325. In some non-limiting examples, at least one of the upper section 3324, the side 3326 and the floor 3327 may be electrically conductive so as to form at least a part of the auxiliary electrode 1750.

In some non-limiting examples, the angle θ_p, which represents the angle by which the angled section 3328 of the upper section 3324 is tilted and/or offset from the axis, may be less than or equal to about 60°. By way of non-limiting example, the angle may be less than or equal to about 50°, less than or equal to about 45°, less than or equal to about 40°, less than or equal to about 30°, less than or equal to about 25°, less than or equal to about 20°, less than or equal to about 15°, and/or less than or equal to about 10°. In some non-limiting examples, the angle may be between about 60° and about 25°, between about 60° and about 30° and/or between about 50° and about 30°. Without wishing to be bound by any particular theory, it may be postulated that providing an angled section 3328 may inhibit deposition of the material for forming the NIC 810 at or near the lip 3329, so as to facilitate the deposition of the material for forming the conductive coating 830 at or near the lip 3229.

FIGS. 33B-33P show various non-limiting examples of the fragment of the device 3200 shown in FIG. 33A after the stage of depositing the conductive coating 830. In FIGS. 33B-33P, for purposes of simplicity of illustration, not all features of the partition 3221 and/or the recess 3222 as described in FIG. 33A may always be shown and the auxiliary electrode 1750 has been omitted, but it will be appreciated by those having ordinary skill in the relevant art, that such feature(s) and/or the auxiliary electrode 1750 may, in some non-limiting examples, nevertheless be present. It will be appreciated by those having ordinary skill in the relevant art that the auxiliary electrode 1750 may be present in any of the examples of FIGS. 33B-33P, in any form and/or position, including without limitation, those shown in any of the examples of FIGS. 34A-34G described herein.

In these FIGURES, a device stack 3310 is shown comprising the at least one semiconducting layer 130, the second electrode 140 and the NIC 810 deposited on the upper section 3324.

In these FIGURES, a residual device stack 3311 is shown comprising the at least one semiconducting layer 130, the second electrode 140 and the NIC 810 deposited on the substrate 100 beyond the partition 3221 and recess 3222. From comparison with FIG. 32, it may be seen that the residual device stack 3311 may, in some non-limiting examples, correspond to the semiconductor layer 130, second electrode 140 and the NIC 810 as it approaches the recess 3221 at and/or proximate to the lip 3329. In some non-limiting examples, the residual device stack 3311 may be formed when an open mask and/or mask-free deposition process is used to deposit various materials of the device stack 3310.

In a non-limiting example 3300b shown in FIG. 33B, the conductive coating 830 is substantially confined to and/or substantially fills all of the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the ceiling 3325, the side 3326 and the floor 3327 and thus be electrically coupled to the auxiliary electrode 1750.

Without wishing to be bound by any particular theory, it may be postulated that substantially filling all of the recess 3222 may reduce a likelihood that any unwanted substances (including without limitation, gases) would be trapped within the recess 3222 during fabrication of the device 3200.

In some non-limiting examples, a coupling and/or contact region (CR) may correspond to a region of the device 3200 wherein the conductive coating 830 is in physical contact with the device stack 3310 in order to electrically couple the second electrode 140 with the conductive coating 830. In some non-limiting examples, the CR extends between about 50 nm and about 1500 nm from an edge of the device stack 3310 proximate to the partition 3221. By way of non-limiting examples, the CR may extend between about 50 nm and about 1000 nm, between about 100 nm and about 500 nm, between about 100 nm and about 350 nm, between about 100 nm and about 300 nm, between about 150 nm and about 300 nm, and/or between about 100 nm and about 200 nm. In some non-limiting examples, the CR may encroach on the device stack 3310 substantially laterally away from an edge thereof by such distance.

In some non-limiting examples, an edge of the residual device stack 3311 may be formed by the at least one semiconducting layer 130, the second electrode 140 and the NIC 810, wherein an edge of the second electrode 140 may be coated and/or covered by the NIC 810. In some non-limiting examples, the edge of the residual device stack 3311 may be formed in other configurations and/or arrangements. In some non-limiting examples, the edge of the NIC 810 may be recessed relative to the edge of the second electrode 140, such that the edge of the second electrode 140 may be exposed, such that the CR may include such exposed edge of the second electrode 140 in order that the second electrode 140 may be in physical contact with the conductive coating 830 to electrically couple them. In some non-limiting examples, the edges of the at least one semiconducting layer 130, the second electrode 140 and the NIC 810 may be aligned with one another, such that the edges of each layer is exposed. In some non-limiting examples, the edges of the second electrode 140 and of the NIC 810 may be recessed relative to the edge of the at least one semiconducting layer 130, such that the edge of the residual device stack 3311 is substantially provided by the semiconductor layer 130.

Additionally, as shown, in some non-limiting examples, within a small CR and arranged at and/or near the lip 3329 of the partition 3221, the conductive coating 830 extends to cover at least an edge of the NIC 810 within the residual device stack 3311 arranged closest to the partition 3221. In some non-limiting examples, the NIC 810 may comprise a semiconducting material and/or an insulating material.

While it has been described herein that direct deposition of the material for forming the conductive coating 830 on the surface of the NIC 810 is generally inhibited, in some non-limiting examples, it has been discovered that a part of the conductive coating 830 may nevertheless overlap at least a part of the NIC 810. By way of non-limiting example, during deposition of the conductive coating 830, the material for forming the conductive coating 830 may initial deposit within the recess 3221. Thereafter continuing to deposit the material for forming the conductive coating 830 may, in some non-limiting examples, cause the conductive coating 830 to extend laterally beyond the recess 830a and overlap at least a part of the NIC 810 within the residual device stack 3311.

Those having ordinary skill in the relevant art will appreciate that while the conductive coating 830 has been shown as overlapping a part of the NIC 810, the lateral extent 410 of the emissive region 1910 remains substantially devoid of the material for forming the conductive coating 830. In some non-limiting examples, the conductive coating 830 may be arranged within the lateral extent 420 of at least a part of at least one non-emissive region 1920 of the device 3200, in some non-limiting examples, without substantially interfering with emission of photons from emissive region(s) 1910 of the device 3200.

In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween so as to reduce an effective sheet resistance of the second electrode 140.

In some non-limiting examples, the NIC 810 may be formed using an electrically conductive material and/or otherwise exhibit a level of charge mobility that allows current to tunnel and/or pass therethrough.

In some non-limiting examples, the NIC 810 may have a thickness that allows current to pass therethrough. In some non-limiting examples, the thickness of the NIC 810 may be between about 3 nm and about 65 nm, between about 3 nm and about 50 nm, between about 5 nm and about 50 nm, between about 5 nm and about 30 nm, and/or between about 5 nm and about 15 nm, between about 5 nm and about 10 nm. In some non-limiting examples, the NIC 810 may be provided with a relatively low thickness (in some non-limiting examples, a thin coating thickness), in order to reduce contact resistance that may be created due to the presence of the NIC 810 in the path of such electric current.

Without wishing to be bound by any particular theory, it may be postulated that substantially filling all of the recess 3221 may, in some non-limiting examples, enhance reliability of electrical coupling between the conductive coating 830 and at least one of the second electrode 140 and the auxiliary electrode 1750.

Further, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300c shown in FIG. 33C, the conductive coating 830 is substantially confined to and/or partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the side 3326, the floor 3327 and, in some non-limiting examples, at least a part of the ceiling 3325 and thus be electrically coupled to the auxiliary electrode 1750.

As shown, in some non-limiting examples, at least a part of the ceiling 3325 is substantially devoid of the conductive coating 830. In some non-limiting examples, such part is proximate to the lip 3329.

Additionally, as shown, in some non-limiting examples, within the small CR arranged at and/or near the lip 3329 of the partition 3221, the conductive coating 830 extends to cover at least an edge of the NIC 810 within the residual device stack 3311 arranged closest to the partition 3221. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300d shown in FIG. 33D, the conductive coating 830 is substantially confined to and/or partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the floor 3327 and in some non-limiting examples, at least a part of the side 3326 and thus be electrically coupled to the auxiliary electrode 1750.

As shown, in some non-limiting examples, the ceiling 3325 is substantially devoid of the conductive coating 830.

Additionally, as shown, in some non-limiting examples, within the small CR arranged at and/or near the lip 3329 of the partition 3221, the conductive coating 830 extends to cover at least an edge of the NIC 810 within the residual device stack 3311 arranged closest to the partition 3221. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300e shown in FIG. 33E, the conductive coating 830 substantially fills all of the recess 3221. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the ceiling 3325, the side 3326 and the floor 3327 and thus be electrically coupled to the auxiliary electrode 1750.

Additionally, as shown, in some non-limiting examples, within the CR, the conductive coating 830 extends to cover at least a part of the NIC 810 within the residual device stack 3311 in order to electrically couple the second electrode 140 with the conductive coating 830.

Further, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 of the device stack 3310 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300f shown in FIG. 33F, the conductive coating 830 is substantially confined to and/or partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the ceiling 3325, the side 3326, and in some non-limiting examples, at least a part of the floor 3327 and thus be electrically coupled to the auxiliary electrode 1750.

As shown, in some non-limiting examples, a cavity 3320 may be formed between the conductive coating 830 and the floor 3327. In some non-limiting examples, the cavity 3320 may correspond to a gap separating the conductive coating 830 from at least a part of the floor 3327, such that the conductive coating 830 is not in physical contact therealong.

As shown, in some non-limiting examples, the cavity 3320 engages a part of the floor 3327 and a part of the residual device stack 3311 and has a relatively thin profile.

In some non-limiting examples, the cavity 3320 may correspond to a volume that is between about 1% and about 30%, between about 5% and about 25%, between about 5% and about 20% and/or between about 5% and about 10% of a volume of the recess 3222.

Additionally, as shown, in some non-limiting examples, within the CR, the conductive coating 830 extends to cover at least a part of the NIC 810 within the residual device stack 3311 in order to electrically couple the second electrode 140 with the conductive coating 830.

In a non-limiting example 3300g shown in FIG. 33G, the conductive coating 830 partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the ceiling 3325, the side 3326 and in some non-limiting examples, at least a part of the floor 3327 and thus be electrically coupled to the auxiliary electrode 1750.

As shown, in some non-limiting examples, a cavity 3320 may be formed between the conductive coating 830 and the floor 3327. In some non-limiting examples, the cavity 3320 may correspond to a gap separating the conductive coating 830 from at least a part of the floor 3327, such that the conductive coating 830 is not in physical contact therealong.

As shown, in some non-limiting examples, the cavity 3320 engages a part of the floor 3327 and a part of the residual device stack 3311 and has a relatively thin profile.

In some non-limiting examples, the cavity 3320 may correspond to a volume that is between about 1% and about 30%, between about 5% and about 25%, between about 5% and about 20% and/or between about 5% and about 10% of a volume of the recess 3222.

Additionally, as shown, in some non-limiting examples, within the CR, the conductive coating 830 extends to cover at least a part of the NIC 810 within the residual device stack 3311 in order to electrically couple the second electrode 140 with the conductive coating 830.

In a non-limiting example 3300h shown in FIG. 33H, the conductive coating 830 partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the ceiling 3325, the side 3326 and, in some non-limiting examples, at least a part of the floor 3327.

As shown, in some non-limiting examples, a cavity 3320 may be formed between the conductive coating 830 and the floor 3327. In some non-limiting examples, the cavity 3320 may correspond to a gap separating the conductive coating 830 from at least a part of the floor 3327, such that the conductive coating 830 is not in physical contact therealong.

As shown, in some non-limiting examples, the cavity 3320 engages a part of the floor 3327 and a part of the residual device stack 3311 and has a relatively thin profile.

In some non-limiting examples, the cavity 3320 may correspond to a volume that is between about 1% and about 30%, between about 5% and about 25%, between about 5% and about 20% and/or between about 5% and about 10% of a volume of the recess 3222.

Additionally, as shown, in some non-limiting examples, within the CR, the conductive coating 830 extends to cover at least a part of the NIC 810 within the residual device stack 3311. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

Further, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 of the device stack 3310 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300i shown in FIG. 33I, the conductive coating 830 partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the ceiling 3325, the side 3326 and, in some non-limiting examples, at least a part of the floor 3327.

As shown, in some non-limiting examples, a cavity 3320 may be formed between the conductive coating 830 and the floor 3327. In some non-limiting examples, the cavity 3320 may correspond to a gap separating the conductive coating 830 from at least a part of the floor 3327, such that the conductive coating 830 is not in physical contact therealong.

As shown, in some non-limiting examples, the cavity 3320 engages a part of the floor 3327 and has a relatively thicker profile than the cavity 3320 shown in examples 3300f-3300h.

In some non-limiting examples, the cavity 3320 may correspond to a volume that is between about 10% and about 80%, between about 10% and about 70%, between about 20% and about 60%, between about 10% and about 30%, between about 25% and about 50%, between about 50% and about 80% and/or between about 70% and about 95% of a volume of the recess 3222.

Additionally, as shown, in some non-limiting examples, within the CR, the conductive coating 830 extends to cover at least a part of the NIC 810 within the residual device stack 3311. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

Further, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 of the device stack 3310 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300j shown in FIG. 33J, the conductive coating 830 partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the ceiling 3325, the side 3326 and, in some non-limiting examples, at least a part of the floor 3327.

As shown, in some non-limiting examples, a cavity 3320 may be formed between the conductive coating 830 and the floor 3327. In some non-limiting examples, the cavity 3320 may correspond to a gap separating the conductive coating 830 from at least a part of the floor 3327, such that the conductive coating 830 is not in physical contact therealong.

As shown, in some non-limiting examples, the cavity 3320 engages a part of the floor 3327 and a [art of the residual device stack 3311 and has a relatively thicker profile than the cavity 3320 shown in examples 3300f-3300h.

In some non-limiting examples, the cavity 3320 may correspond to a volume that is between about 10% and about 80%, between about 10% and about 70%, between about 20% and about 60%, between about 10% and about 30%, between about 25% and about 50%, between about 50% and about 80% and/or between about 70% and about 95% of a volume of the recess 3222.

Additionally, as shown, in some non-limiting examples, within the CR, the conductive coating 830 extends to cover at least a part of the NIC 810 within the residual device stack 3311. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

Further, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 of the device stack 3310 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300k shown in FIG. 33K, the conductive coating 830 partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with, in some non-limiting examples, at least a part of the ceiling 3325 and, in some non-limiting examples, at least a part of the floor 3327.

As shown, in some non-limiting examples, a cavity 3320 may be formed between the conductive coating 830 and the side 3326, in some non-limiting examples, at least a part of the ceiling 3325 and in some non-limiting examples, at least a part of the floor 3327. In some non-limiting examples, the cavity 3320 may correspond to a gap separating the conductive coating 830 from the side 3326, in some non-limiting examples, at least a part of the ceiling 3325 and, in some non-limiting examples, at least a part of the floor 3327, such that the conductive coating 830 is not in physical contact therealong.

As shown, in some non-limiting examples, the cavity 3320 occupies substantially all of the recess 3222.

In some non-limiting examples, the cavity 3320 may correspond to a volume that is between about 10% and about 80%, between about 10% and about 70%, between about 20% and about 60%, between about 10% and about 30%, between about 25% and about 50%, between about 50% and about 80% and/or between about 70% and about 95% of a volume of the recess 3222.

Additionally, as shown, in some non-limiting examples, within the CR, the conductive coating 830 extends to cover at least a part of the NIC 810 within the residual device stack 3311. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

Further, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 of the device stack 3310 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300l shown in FIG. 33L, the conductive coating 830 partially fills the recess 3222.

As shown, in some non-limiting examples, a cavity 3320 may be formed between the conductive coating 830 and the side 3326, the floor 3327 and the ceiling 3325. In some non-limiting examples, the cavity 3320 may correspond to a gap separating the conductive coating 830 from the side 3326, the floor 3327 and the ceiling 3325, such that the conductive coating 830 is not in physical contact therealong.

As shown, in some non-limiting examples, the cavity 3320 occupies substantially all of the recess 3222.

In some non-limiting examples, the cavity 3320 may correspond to a volume that is greater than about 80% of a volume of the recess 3222.

Additionally, as shown, in some non-limiting examples, within the CR, the conductive coating 830 extends to cover at least a part of the NIC 810 within the residual device stack 3311. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

Further, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 of the device stack 3310 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300m shown in FIG. 33M, the conductive coating 830 is substantially confined to and/or partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with, in some non-limiting examples, at least a part of the ceiling 3325 and in some non-limiting examples, at least a part of the floor 3327.

As shown, in some non-limiting examples, a cavity 3320 may be formed between the conductive coating 830 and the side 3326, in some non-limiting examples, at least a part of the ceiling 3325 and in some non-limiting examples, at least a part of the floor 3327. In some non-limiting examples, the cavity 3320 may correspond to a gap separating the conductive coating 830 from the side, in some non-limiting examples, at least a part of the ceiling 3325 and, in some non-limiting examples, at least a part of the floor 3327, such that the conductive coating 830 is not in physical contact therealong.

As shown, in some non-limiting examples, the cavity 3320 occupies substantially all of the recess 3222.

In some non-limiting examples, the cavity 3320 may correspond to a volume that is between about 10% and about 80%, between about 10% and about 70%, between about 20% and about 60%, between about 10% and about 30%, between about 25% and about 50%, between about 50% and about 80% and/or between about 70% and about 95% of a volume of the recess 3222.

Additionally, as shown, in some non-limiting examples, within the CR, the conductive coating 830 extends to cover at least a part of the NIC 810 within the residual device stack 3311. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

Further, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 of the device stack 3310 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300n shown in FIG. 33N, the conductive coating 830 partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the ceiling 3325, the side 3326 and, in some non-limiting examples, at least a part of the floor 3327.

Additionally, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 of the device stack 3310 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300o shown in FIG. 33O, the conductive coating 830 partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the ceiling 3325, the side 3326 and, in some non-limiting examples, at least a part of the floor 3327.

Additionally, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 of the device stack 3310 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

In a non-limiting example 3300p shown in FIG. 33P, the conductive coating 830 partially fills the recess 3222. As such, in some non-limiting examples, the conductive coating 830 may be in physical contact with the ceiling 3325, in some non-limiting examples, at least a part of the side 3326.

Additionally, as shown, in some non-limiting examples, the conductive coating 830 extends to cover at least a part of the NIC 810 of the device stack 3310 disposed on the upper section 3324 of the partition 3221. In some non-limiting examples, a part of the NIC 810 at and/or proximate to the lip 3329 may be covered by the conductive coating 830. In some non-limiting examples, the conductive coating 830 may nevertheless be electrically coupled to the second electrode 140 despite the interposition of the NIC 810 therebetween.

FIGS. 34A-34G show various non-limiting examples of different locations of the auxiliary electrode 1750 throughout the fragment of the device 3200 shown in FIG. 33A, again at a stage prior to deposition of the at least one semiconducting layer 130. Accordingly, in FIGS. 34A-34G, the at least one semiconducting layer 130, the second electrode 140 and the NIC 810, whether or not as part of the residual device stack 3311, and the conductive coating 830 are not shown. Nevertheless, it will be appreciated by those having ordinary skill in the relevant art, that such feature(s) and/or layer(s) may be present, after deposition, in any of the examples of FIGS. 34A-34G, in any form and/or position, including without limitation, those shown in any of the examples of FIGS. 33B-33P.

In a non-limiting example 3400a shown in FIG. 34A, the auxiliary electrode 1750 is arranged adjacent to and/or within the substrate 110 such that a surface of the auxiliary electrode 1750 is exposed in the recess 3222. As shown, in some non-limiting examples, such surface of the auxiliary electrode 1750 is provided in and/or may form and/or provide at least a part of the floor 3327. By way of non-limiting example, the auxiliary electrode 1750 may be arranged to be disposed adjacent to the partition 3221. In some non-limiting examples, the auxiliary electrode 1750 may be formed of at least one electrically conductive material. In some non-limiting examples, the partition 3221 may be formed of at least one substantially insulating material including without limitation, photoresist. In some non-limiting examples, various features of the device 3200, including without limitation, the partition 3221 and/or the auxiliary electrode 1750, may be formed using techniques including without limitation, photolithography.

In a non-limiting example 3400b shown in FIG. 34B, the auxiliary electrode 1750 is formed integrally with and/or as part of the partition 3221 such that a surface of the auxiliary electrode 1750 is exposed in the recess 3222. As shown, in some non-limiting examples, such surface of the auxiliary electrode 1750 is provided in and/or may form and/or provide at least a part of the side 3326. By way of non-limiting example, the auxiliary electrode 1750 may be arranged to correspond to the lower section 3323. In some non-limiting examples, the auxiliary electrode 1750 may be formed of at least one electrically conductive material. In some non-limiting examples, the upper section 3324 may be formed of at least one substantially insulating material including without limitation, photoresist. In some non-limiting examples, various features of the device 3200, including without limitation, the upper section 3324 and/or the auxiliary electrode 1750, may be formed using techniques including without limitation, photolithography.

In a non-limiting example 3400c shown in FIG. 34C, the auxiliary electrode 1750 is arranged both adjacent to and/or within the substrate 110 and integrally with and/or as part of the partition 3221 such that a surface of the auxiliary electrode 1750 is exposed in the recess 3222. As shown, in some non-limiting examples, such surface of the auxiliary electrode 1750 is provided in and/or may form and/or provide at least a part of the side 3326 and/or at least a part of the floor 3327. By way of non-limiting example, the auxiliary electrode 1750 may be arranged to be disposed adjacent to the partition 3221 and/or to correspond to the lower section 3323. In some non-limiting examples, the part of the auxiliary electrode 1750 disposed adjacent to the partition 3221 may be electrically coupled and/or in physical contact with the part thereof that corresponds to the lower section 3323. In some non-limiting examples, such parts may be formed continuously and/or integrally with one another. In some non-limiting examples, the auxiliary electrode 1750 may be formed of at least one electrically conductive material. In some non-limiting examples, the parts thereof may be formed of different materials. In some non-limiting examples, the partition 3221 and/or the upper section 3324 thereof may be formed of at least one substantially insulating material including without limitation, photoresist. In some non-limiting examples, various features of the device 3200, including without limitation, the partition 3221, the upper section 3324 and/or the auxiliary electrode 1750, may be formed using techniques including without limitation, photolithography.

In a non-limiting example 3400d shown in FIG. 34D, the auxiliary electrode 1750 is arranged adjacent to and/or within the upper section 3324 such that a surface of the auxiliary electrode 1750 is exposed within the recess 3222. As shown, in some non-limiting examples, such surface of the auxiliary electrode 1750 is provided in and/or may form and/or provide at least a part of the ceiling 3325. By way of non-limiting example, the auxiliary electrode 1750 may be arranged to be disposed adjacent to the upper section 3324. In some non-limiting examples, the auxiliary electrode 1750 may be formed of at least one electrically conductive material. In some non-limiting examples, the partition 3221 may be formed of at least one substantially insulating material including without limitation, photoresist. In some non-limiting examples, various features of the device 3200, including without limitation, the partition 3221 and/or the auxiliary electrode 1750, may be formed using techniques including without limitation, photolithography.

In a non-limiting example 3400e shown in FIG. 34E, the auxiliary electrode 1750 is arranged both adjacent to and/or within the upper section 3324 and integrally with and/or as part of the partition 3221 such that a surface of the auxiliary electrode 1750 is exposed in the recess 3222. As shown, in some non-limiting examples, such surface of the auxiliary electrode 1750 is provided in and/or may form and/or provide at least a part of the ceiling 3325 and/or at least a part of the side 3326. By way of non-limiting example, the auxiliary electrode 1750 may be arranged to be disposed adjacent to the upper section 3324 and/or to correspond to the lower section 3323. In some non-limiting examples, the part of the auxiliary electrode 1750 disposed adjacent to the upper section 3324 may be electrically coupled and/or in physical contact with the part thereof that corresponds to the lower section 3323. In some non-limiting examples, such part may be formed continuously and/or integrally with one another. In some non-limiting examples, the auxiliary electrode 1750 may be formed of at least one electrically conductive material. In some non-limiting examples, the parts thereof may be formed of different materials. In some non-limiting examples, the upper section 3324 may be formed of at least one substantially insulating material including without limitation, photoresist. In some non-limiting examples, various features of the device 3200, including without limitation, the upper section 3324 and/or the auxiliary electrode 1750, may be formed using techniques including without limitation, photolithography.

In a non-limiting example 3400f shown in FIG. 34F, the auxiliary electrode 1750 is arranged both adjacent to and/or within the substrate 110 and adjacent to and/or within the upper section 3324 such that a surface of the auxiliary electrode 1750 is exposed within the recess 3222. As shown, in some non-limiting examples, such surface of the auxiliary electrode 1750 is provided in and/or may form and/or provide at least a part of the ceiling 3325 and/or at least a part of the floor 3327. By way of non-limiting example, the auxiliary electrode 1750 may be arranged to be disposed adjacent to the partition 3221 and/or adjacent to the upper section 3324 thereof. In some non-limiting examples, the part of the auxiliary electrode 1750 disposed adjacent to the partition may be electrically coupled to the part thereof that corresponds to the ceiling 3325. In some non-limiting examples, the auxiliary electrode 1750 may be formed of at least one electrically conductive material. In some non-limiting examples, the part thereof may be formed of different materials. In some non-limiting examples, the partition 3221 and/or the upper section 3324 thereof may be formed of at least one substantially insulating material including without limitation, photoresist. In some non-limiting examples, various features of the device 3200, including without limitation, the partition 3221, the upper section 3324 and/or the auxiliary electrode 1750, may be formed using techniques including without limitation, photolithography.

In a non-limiting example 3400g shown in FIG. 34G the auxiliary electrode 1750 is arranged both adjacent to and/or within the substrate 110, integrally with and/or as part of the partition 3221 and/or adjacent to and/or within the upper section 3324 such that a surface of the auxiliary electrode 1750 is exposed within the recess 3222. As shown, in some non-limiting examples, such surface of the auxiliary electrode 1750 is provided in and/or may form and/or provide at least a part of the ceiling 3325, at least a part of the side 3326 and/or at least a part of the floor 3327. By way of non-limiting example, the auxiliary electrode 1750 may be arranged to be disposed adjacent to the partition 3221, to correspond to the lower section 3323 and/or adjacent to the upper section 3324 thereof. In some non-limiting examples, the part of the auxiliary electrode 1750 disposed adjacent to the partition 3221 may be electrically coupled to at least one of the parts thereof that correspond to the lower section 3323 and/or to the ceiling 3325. In some non-limiting examples, the part of the auxiliary electrode 1750 that corresponds to the lower section 3323 may be electrically coupled to at least one of the parts thereof disposed adjacent to the partition 3221 and/or to the ceiling 3325. In some non-limiting examples, the part of the auxiliary electrode 1750 that corresponds to the ceiling 3325 may be electrically coupled to at least one of the parts thereof disposed adjacent to the partition and/or to the lower section 3323. In some non-limiting examples, the part of the auxiliary electrode 1750 that corresponds to the lower section 3323 may be in physical contact with at least one of the parts thereof disposed adjacent to the partition 3221 and/or that corresponds to the upper section 3324. In some non-limiting examples, the auxiliary electrode 1750 may be formed of at least one electrically conductive material. In some non-limiting examples, the parts thereof may be formed of different materials. In some non-limiting examples, the partition 3221, the lower section 3323 and/or the upper section 3324 thereof may be formed of at least one substantially insulating material including without limitation, photoresist. In some non-limiting examples, various features of the device 3200, including without limitation, the partition 3221, the lower section 3323 and/or the upper section 3324 thereof and/or the auxiliary electrode 1750, may be formed using techniques including without limitation, photolithography.

In some non-limiting examples, various features described in relation to FIGS. 33B-33P may be combined with various features described in relation to FIGS. 34A-34GH. In some non-limiting examples, the residual device stack 3311 and the conductive coating 830 according to any one of FIGS. 33B, 33C, 33E, 33F, 33G, 33H, 33I and/or 33J may be combined together with the partition 3221 and the auxiliary electrode 1750 according to any one of FIGS. 34A-34G. In some non-limiting examples, any one of FIGS. 33K-33M may be independently combined with any one of FIGS. 34D-34G. In some non-limiting examples, any one of FIGS. 33C-33D may be combined with any one of FIGS. 34A, 34C, 34F and/or 34G.

Aperture in Non-Emissive Region

Turning now to FIG. 35A, there is shown a cross-sectional view of an example version 3500 of the device 100. The device 3500 differs from the device 3200 in that a pair of partitions 3221 in the non-emissive region 1920 are disposed in a facing arrangement to define a sheltered region 3065, such as an aperture 3522, therebetween. As shown, in some non-limiting examples, at least one of the partitions 3221 may function as a PDL 440 that covers at least an edge of the first electrode 120 and that defines at least one emissive region 1910. In some non-limiting examples, at least one of the partitions 3221 may be provided separately from a PDL 440.

A sheltered region 3065, such as the recess 3222, is defined by at least one of the partitions 3221. In some non-limiting examples, the recess 3222 may be provided in a part of the aperture 3522 proximal to the substrate 110. In some non-limiting examples, the aperture 3522 may be substantially elliptical when viewed in plan view. In some non-limiting examples, the recess 3222 may be substantially annular when viewed in plan view and surround the aperture 3522.

In some non-limiting examples, the recess 3222 may be substantially devoid of materials for forming each of the layers of the device stack 3310 and/or of the residual device stack 3311.

In some non-limiting examples, the residual device stack 3311 may be disposed within the aperture 3522. In some non-limiting examples, evaporated materials for forming each of the layers of the device stack 3310 may be deposited within the aperture 3522 to form the residual device stack 3311 therein.

In some non-limiting examples, the auxiliary electrode 1750 is arranged such that at least a part thereof is disposed within the recess 3222. By way of non-limiting example, the auxiliary electrode 1750 may be disposed relative to the recess 3222 by any one of the examples shown in FIGS. 34A-34G. As shown, in some non-limiting examples, the auxiliary electrode 1750 is arranged within the aperture 3522, such that the residual device stack 3311 is deposited onto a surface of the auxiliary electrode 1750.

A conductive coating 830 is disposed within the aperture 3522 for electrically coupling the electrode 140 to the auxiliary electrode 1750. By way of non-limiting example, at least a part of the conductive coating 830 is disposed within the recess 3222. By way of non-limiting example, the conductive coating 830 may be disposed relative to the recess 3222 by any one of the examples shown in FIGS. 33A-33P. By way of non-limiting example, the arrangement shown in FIG. 35A may be seen to be a combination of the example shown in FIG. 33P in combination with the example shown in FIG. 34C.

Turning now to FIG. 35B, there is shown a cross-sectional view of a further example of the device 3500. As shown, the auxiliary electrode 1750 is arranged to form at least a part of the side 3326. As such, the auxiliary electrode 1750 may be substantially annular when viewed in plan view and surround the aperture 3522. As shown, in some non-limiting examples, the residual device stack 3311 is deposited onto an exposed layer surface 111 of the substrate 110.

By way of non-limiting examples, the arrangement shown in FIG. 35B may be seen to be a combination of the example shown in FIG. 33O in combination with the example shown in FIG. 34B.

In the present disclosure, the terms “overlap” and/or “overlapping” may refer generally to two or more layers and/or structures arranged to intersect a cross-sectional axis extending substantially normally away from a surface onto which such layers and/or structures may be disposed.

NPCs

Without wishing to be bound by a particular theory, it is postulated that providing an NPC 1120 may facilitate deposition of the conductive coating 830 onto certain surfaces.

Non-limiting examples of suitable materials for forming an NPC 1120 include without limitation, at least one of metals, including without limitation, alkali metals, alkaline earth metals, transition metals and/or post-transition metals, metal fluorides, metal oxides and/or fullerene.

In the present disclosure, the term “fullerene” may refer generally to a material including carbon molecules. Non-limiting examples of fullerene molecules include carbon cage molecules, including without limitation, a three-dimensional skeleton that includes multiple carbon atoms that form a closed shell and which may be, without limitation, spherical and/or semi-spherical in shape. In some non-limiting examples, a fullerene molecule can be designated as C_n, where n is an integer corresponding to a number of carbon atoms included in a carbon skeleton of the fullerene molecule. Non-limiting examples of fullerene molecules include where n is in the range of 50 to 250, such as, without limitation, C₇₀, C₇₀, C₇₂, C₇₄, C₇₆, C₇₈, C₈₀, C₈₂, and C₈₄. Additional non-limiting examples of fullerene molecules include carbon molecules in a tube and/or a cylindrical shape, including without limitation, single-walled carbon nanotubes and/or multi-walled carbon nanotubes.

Non-limiting examples of such materials include Ca, Ag, Mg, Yb, ITO, IZO, ZnO, ytterbium fluoride (YbF₃), magnesium fluoride (MgF₂) and/or cesium fluoride (CsF).

Based on findings and experimental observations, it is postulated that nucleation promoting materials, including without limitation, fullerenes, metals, including without limitation, Ag and/or Yb, and/or metal oxides, including without limitation, ITO and/or IZO, as discussed further herein, may act as nucleation sites for the deposition of a conductive coating 830, including without limitation Mg.

In some non-limiting examples, the NPC 1120 may be provided by a part of the at least one semiconducting layer 130. By way of non-limiting example, a material for forming the EIL 139 may be deposited using an open mask and/or mask-free deposition process to result in deposition of such material in both an emissive region 1910 and/or a non-emissive region 1920 of the device 100. In some non-limiting examples, a part of the at least one semiconducting layer 130, including without limitation the EIL 139, may be deposited to coat one or more surfaces in the sheltered region 3065. Non-limiting examples of such materials for forming the EIL 139 include at least one or more of alkali metals, including without limitation, Li, alkaline earth metals, fluorides of alkaline earth metals, including without limitation, MgF₂, fullerene, Yb, YbF₃, and/or CsF.

In some non-limiting examples, the NPC 1120 may be provided by the second electrode 140 and/or a portion, layer and/or material thereof. In some non-limiting examples, the second electrode 140 may extend laterally to cover the layer surface 3111 arranged in the sheltered region 3065. In some non-limiting examples, the second electrode 140 may comprise a lower layer thereof and a second layer thereof, wherein the second layer thereof is deposited on the lower layer thereof. In some non-limiting examples, the lower layer of the second electrode 140 may comprise an oxide such as, without limitation, ITO, IZo and/or ZnO, In some non-limiting examples, the upper layer of the second electrode 140 may comprise a metal such as, without limitation, at least one of Ag, Mg, Mg:Ag, Yb/Ag, other alkali metals and/or other alkali earth metals.

In some non-limiting examples, the lower layer of the second electrode 140 may extend laterally to cover a surface of the sheltered region 3065, such that it forms the NPC 1120. In some non-limiting examples, one or more surfaces defining the sheltered region 3065 may be treated to form the NPC 1020. In some non-limiting examples, such NPC 1120 may be formed by chemical and/or physical treatment, including without limitation, subjecting the surface(s) of the sheltered region 3065 to a plasma, UV and/or UV-ozone treatment.

Without wishing to be bound to any particular theory, it is postulated that such treatment may chemically and/or physically alter such surface(s) to modify at least one property thereof. By way of non-limiting example, such treatment of the surface(s) may increase a concentration of C—O and/or C—OH bonds on such surface(s), increase a roughness of such surface(s) and/or increase a concentration of certain species and/or functional groups, including without limitation, halogens, nitrogen-containing functional groups and/or oxygen-containing functional groups to thereafter act as an NPC 1120.

In some non-limiting examples, the partition 830a includes and/or if formed by an NPC 1120. By way of non-limiting examples, the auxiliary electrode 1750 may act as an NPC 1120.

In some non-limiting examples, suitable materials for use to form an NPC 1120, may include those exhibiting or characterized as having an initial sticking probability S₀ for a material of a conductive coating 830 of at least about 0.4 (or 40%), at least about 0.5, at least about 0.6, at least about 0.7, at least about 0.75, at least about 0.8, at least about 0.9, at least about 0.93, at least about 0.95, at least about 0.98, and/or at least about 0.99.

By way of non-limiting example, in scenarios where Mg is deposited using without limitation, an evaporation process on a fullerene-treated surface, in some non-limiting examples, the fullerene molecules may act as nucleation sites that may promote formation of stable nuclei for Mg deposition.

In some non-limiting examples, less than a monolayer of an NPC 1120, including without limitation, fullerene, may be provided on the treated surface to act as nucleation sites for deposition of Mg.

In some non-limiting examples, treating a surface by depositing several monolayers of an NPC 1120 thereon may result in a higher number of nucleation sites and accordingly, a higher initial sticking probability S₀.

Those having ordinary skill in the relevant art will appreciate than an amount of material, including without limitation, fullerene, deposited on a surface, may be more, or less than one monolayer. By way of non-limiting example, such surface may be treated by depositing 0.1 monolayer, 1 monolayer, 10 monolayers, or more of a nucleation promoting material and/or a nucleation inhibiting material.

In some non-limiting examples, a thickness of the NPC 1120 deposited on an exposed layer surface 111 of underlying material(s) may be between about 1 nm and about 5 nm and/or between about 1 nm and about 3 nm.

While the present disclosure discusses thin film formation, in reference to at least one layer and/or coating, in terms of vapor deposition, those having ordinary skill in the relevant art will appreciate that, in some non-limiting examples, various components of the electro-luminescent device 100 may be deposited using a wide variety of techniques, including without limitation, evaporation (including without limitation, thermal evaporation and/or electron beam evaporation), photolithography, printing (including without limitation, ink jet and/or vapor jet printing, reel-to-reel printing and/or micro-contact transfer printing), PVD (including without limitation, sputtering), CVD (including without limitation, PECVD and/or OVPD), laser annealing, LITI patterning, ALD, coating (including without limitation, spin coating, dip coating, line coating and/or spray coating), and/or combinations of any two or more thereof. Such processes may be used in combination with a shadow mask to achieve various patterns.

NICs

Without wishing to be bound by a particular theory, it is postulated that, during thin film nucleation and growth at and/or near an interface between the exposed layer surface 111 of the substrate 110 and the NIC 810, a relatively high contact angle θ_c between the edge of the film and the substrate 110 be observed due to “dewetting” of the solid surface of the thin film by the NIC 810. Such dewetting property may be driven by minimization of surface energy between the substrate 110, thin film, vapor 7 and the NIC 810 layer. Accordingly, it may be postulated that the presence of the NIC 810 and the properties thereof may have, in some non-limiting examples, an effect on nuclei formation and a growth mode of the edge of the conductive coating 830.

Without wishing to be bound by a particular theory, it is postulated that, in some non-limiting examples, the contact angle θ_c of the conductive coating 830 may be determined, based at least partially on the properties (including, without limitation, initial sticking probability S₀) of the NIC 810 disposed adjacent to the area onto which the conductive coating 830 is formed. Accordingly, NIC 810 material that allow selective deposition of conductive coatings 830 exhibiting relatively high contact angles θ_c may provide some benefit.

Without wishing to be bound by a particular theory, it is postulated that, in some non-limiting examples, the relationship between various interfacial tensions present during nucleation and growth may be dictated according to Young's equation in capillarity theory:

${\gamma }_{sv}={\gamma }_{\mathrm{fs}}+{\gamma }_{\mathrm{vf}}\cos \theta$ wherein γ_sv corresponds to the interfacial tension between substrate 110 and vapor, γ_fs corresponds to the interfacial tension between the thin film and the substrate 110, γ_vf corresponds to the interfacial tension between the vapor and the film, and θ is the film nucleus contact angle. FIG. 36 illustrates the relationship between the various parameters represented in this equation.

On the basis of Young's equation, it may be derived that, for island growth, the film nucleus contact angle θ is greater than 0 and therefore θ_sv<θ_fs+θ_vf.

For layer growth, where the deposited film “wets” the substrate 110, the nucleus contact angle θ=0, and therefore θ_sv=θ_fs+θ_vf.

For Stranski-Krastanov (S-K) growth, where the strain energy per unit area of the film overgrowth is large with respect to the interfacial tension between the vapor and the film, θ_sv>θ_fs+θ_vf.

It may be postulated that the nucleation and growth mode of the conductive coating 830 at an interface between the NIC 810 and the exposed layer surface 111 of the substrate 110 may follow the island growth model, where θ>0. Particularly in cases where the NIC 810 exhibits a relatively low affinity and/or low initial sticking probability S₀ (i.e. dewetting) towards the material used to form the conductive coating 830, resulting in a relatively high thin film contact angle of the conductive coating 830. On the contrary, when a conductive coating 830 is selectively deposited on a surface without the use of an NIC 810, by way of non-limiting example, by employing a shadow mask, the nucleation and growth mode of the conductive coating 830 may differ. In particular, it has been observed that the conductive coating 830 formed using a shadow mask patterning process may, at least in some non-limiting examples, exhibit relatively low thin film contact angle of less than about 10°.

Those having ordinary skill in the relevant art will appreciate that, while not explicitly illustrated, a material used to form the NIC 810 may also be present to some extent at an interface between the conductive coating 830 and an underlying surface (including without limitation, a surface of a NPC 1120 layer and/or the substrate 110). Such material may be deposited as a result of a shadowing effect, in which a deposited pattern is not identical to a pattern of a mask and may, in some non-limiting examples, result in some evaporated material being deposited on a masked part of a target surface 111. By way of non-limiting examples, such material may form as islands and/or disconnected clusters, and/or as a thin film having a thickness that may be substantially less than an average thickness of the NIC 810.

In some non-limiting examples, it may be desirable for the activation energy for desorption (E_des 631) to be less than about 2 times the thermal energy (k_BT), less than about 1.5 times the thermal energy (k_BT), less than about 1.3 times the thermal energy (k_BT), less than about 1.2 times the thermal energy (k_BT), less than the thermal energy (k_BT), less than about 0.8 times the thermal energy (k_BT), and/or less than about 0.5 times the thermal energy (k_BT). In some non-limiting examples, it may be desirable for the activation energy for surface diffusion (E_s 621) to be greater than the thermal energy (k_BT), greater than about 1.5 times the thermal energy (k_BT), greater than about 1.8 times the thermal energy (k_BT), greater than about 2 times the thermal energy (k_BT), greater than about 3 times the thermal energy (k_BT), greater than about 5 times the thermal energy (k_BT), greater than about 7 times the thermal energy (k_BT), and/or greater than about 10 times the thermal energy (k_BT).

In some non-limiting examples, suitable materials for use to form an NIC 810, may include those exhibiting and/or characterized as having an initial sticking probability S₀ for a material of a conductive coating 830 of no greater than and/or less than about 0.3 (or 30%), no greater than and/or less than about 0.2, no greater than and/or less than about 0.1, no greater than and/or less than about 0.05, no greater than and/or less than 0.03, no greater than and/or less than 0.02, no greater than and/or less than 0.01, no greater than and/or less than about 0.08, no greater than and/or less than about 0.005, no greater than and/or less that about 0.003, no greater than and/or less than about 0.001, no greater than and/or less than about 0.0008, no greater than and/or less than about 0.0005, and/or no greater than and/or less than about 0.0001.

In some non-limiting examples, suitable materials for use to form an NIC 810 include those exhibiting and/or characterized has having initial sticking probability S₀ for a material of a conductive coating 830 of between about 0.03 and about 0.0001, between about 0.03 and about 0.0003, between about 0.03 and about 0.0005, between about 0.03 and about 0.0008, between about 0.03 and about 0.001, between about 0.03 and about 0.005, between about 0.03 and about 0.008, between about 0.03 and about 0.01, between about 0.02 and about 0.0001, between about 0.02 and about 0.0003, between about 0.02 and about 0.0005, between about 0.02 and about 0.0008, between about 0.02 and about 0.0005, between about 0.02 and about 0.0008, between about 0.02 and about 0.001, between about 0.02 and about 0.005, between about 0.02 and about 0.008, between about 0.02 and about 0.01, between about 0.01 and about 0.0001, between about 0.01 and about 0.0003, between about 0.01 and about 0.0005, between about 0.01 and about 0.0008, between about 0.01 and about 0.001, between about 0.01 and about 0.005, between about 0.01 and about 0.008, between about 0.008 and about 0.0001, between about 0.008 and about 0.0003, between about 0.008 and about 0.0005, between about 0.008 and about 0.0008, between about 0.008 and about 0.001, between about 0.008 and about 0.005, between about 0.005 and about 0.0001, between about 0.005 and about 0.0003, between about 0.005 and about 0.0005, between about 0.005 and about 0.0008, and/or between about 0.005 and about 0.001.

In some non-limiting examples, suitable materials for use to form an NIC 810, may include organic materials, such as small molecule organic materials and/or organic polymers.

Non-limiting examples of suitable materials for use to form an NIC 810 include at least one material described in at least one of U.S. Pat. No. 10,270,033, PCT International Application No. PCT/IB2018/052881, PCT International Application No. PCT/IB2019/053706 and/or PCT International Application No. PCT/IB2019/050839.

In some embodiments, the NIC comprises a compound of Formulae (I), (II), (III), (IV), (V), (VI), (VII), (VIII), (IX), (X), (XI), (XII), (XIII), (XIV), (XV), (XVI), (XVII), (XVIII), (XIX) and/or (XX).

In Formulae (I), (II), (III), (IV), (V), (VI), (VII), (VIII), (IX), (X), (XI), (XII), (XIII), (XIV), (XV), (XVI), (XVII), (XVIII), (XIX) and/or (XX):

L¹ represents C, CR², CR²R³, N, NR³, S, O, substituted or unsubstituted cycloalkylene having 3-6 carbon atoms, substituted or unsubstituted arylene group having 5-60 carbon atoms, or a substituted or unsubstituted heteroarylene group having 4-60 carbon atoms. Example of cycloalkylene include, but are not limited to cyclopropylene, cyclopentylene and cyclohexylene. Examples of arylene group include, but are not limited to, the following: phenylene, indenylene, naphthylene, fluorenylene, anthracylene, phenanthrylene, pyrylene, and chrysenylene. Other examples of L₁ may include cyclopentylene. For example, L¹ may be an arylene group having 5-30 carbon atoms. Examples of heteroarylene group include, but are not limited to, heteroarylene groups derived by replacing one, two, three, four, or more ring carbon atom(s) of arylene groups with a corresponding number of heteroatom(s). For example, one or more such heteroatom(s) may be individually selected from: nitrogen, oxygen, and sulphur. For example, L¹ may be a heteroarylene group having 4-30 carbon atoms. In some embodiments, L¹ optionally includes one or more substituents. Examples of such substituents include but are not limited to the following: H, D (deutero), F, Cl, alkyl including C1-C6 alkyl, cycloaklyl including C3-C6 cycloalkyl, alkoxy including C1-C6 alkoxy, fluoroalkyl, haloaryl, heteroaryl, haloalkoxy, fluoroaryl, fluoroalkoxy, fluoroalkylsulfanyl, fluoromethyl, difluoromethyl, trifluoromethyl, difluoromethoxy, trifluoromethoxy, fluoroethyl, polyfluoroethyl, 4-fluorophenyl, 3,4,5-trifluorophenyl, polyfluoroaryl, 4-(trifluoromethoxy)phenyl, SF₄Cl, SF₅, (O(CF₂)_b)_dCF₃, (CF₂)_e(O(CF₂)_b)_d)CF₃, (CF₂)_aSF₅, (Ob)(CF₂)_dCF₃, and trifluoromethylsulfanyl.

Ar¹ represents a substituted or unsubstituted aryl group having 5 to 60 carbon atoms, a substituted or unsubstituted haloaryl group having 5 to 60 carbon atoms, or a substituted or unsubstituted heteroaryl group having 4 to 60 carbon atoms. Examples of Ar¹ include, but are not limited to, the following: cyclopentadienyl, phenyl; 1-naphthyl; 2-naphthyl; 1-phenanthryl; 2-phenanthryl; 9-phenanthryl; 10-phenanthryl; 1-anthracenyl; 2-anthracenyl; 3-anthracenyl; 9-anthracenyl; benzanthracenyl (including 5-, 6-, 7-, 8- and 9-benzathracenyl); pyrenyl (including 1-, 2-, and 4-pyrenyl), chrysenyl (including 3-, 4-, 5-, 6-, 9-, and 10-chrysenyl), fluorenyl (including 2-, 4-, 5-, 6-, and 9-fluorenyl), and pentacenyl. Ar¹ may be substituted with one or more substituents. Examples of such substituents include but are not limited to the following: H, D (deutero), F, Cl, alkyl including C1-C6 alkyl, cycloaklyl including C3-C6 cycloalkyl, alkoxy including C1-C6 alkoxy, fluoroalkyl, haloaryl, heteroaryl, haloalkoxy, fluoroaryl, fluoroalkoxy, fluoroalkylsulfanyl, fluoromethyl, difluoromethyl, trifluoromethyl, difluoromethoxy, trifluoromethoxy, fluoroethyl, polyfluoroethyl, 4-fluorophenyl, 3,4,5-trifluorophenyl, polyfluoroaryl, 4-(trifluoromethoxy)phenyl, SF₄Cl, SF₅, (CF₂)_aSF₅, (O(CF₂)_b)_dCF₃, (CF₂)_e(O(CF₂)_b)_d)CF₃, and trifluoromethylsulfanyl.

R¹ individually represents H, D (deutero), F, Cl, alkyl including C1-C6 alkyl, cycloaklyl including C3-C6 cycloalkyl, alkoxy including C1-C6 alkoxy, fluoroalkyl, haloaryl, heteroaryl, haloalkoxy, fluoroaryl, fluoroalkoxy, fluoroalkylsulfanyl, fluoromethyl, difluoromethyl, trifluoromethyl, difluoromethoxy, trifluoromethoxy, fluoroethyl, polyfluoroethyl, 4-fluorophenyl, 3,4,5-trifluorophenyl, polyfluoroaryl, 4-(trifluoromethoxy)phenyl, SF₄Cl, SF₅, (CF₂)_aSF₅, (O(CF₂)_b)_dCF₃, (CF₂)_e(O(CF₂)_b)_d)CF₃, and trifluoromethylsulfanyl.

• • s represents an integer of 0 to 4.
  • r represents an integer of 1 to 3, or an integer of 1 to 2.
  • p represents an integer of 0 to 6, an integer of 0 to 5, an integer of 0 to 4, an integer of 0 to 3, or an integer of 0 to 2.
  • q represents an integer of 0 to 8, an integer of 0 to 6, an integer of 0 to 5, an integer of 0 to 4, an integer of 0 to 3, or an integer of 0 to 2. In some embodiments, q represents an integer of 1 to 8, an integer of 1 to 6, an integer of 1 to 5, an integer of 1 to 4, an integer of 1 to 3, or an integer of 1 to 2.

The sum of r and s is 5. The sum of r and u is 3.

In Formula (VI) and (XV), Z represents F or Cl.

In Formula (X) and (XI), h represents and integer of 0 to 3, or an integer of 0 to 2. The sum of r and h is 4.

In Formula (XIII), v represents an integer of 2 to 4, or an integer of 2 to 3.

In Formula (XIV), j represents an integer of 1 to 3, and k represents an integer of 1 to 4.

In Formula (XV), t represents an integer of 2 to 6, or an integer of 2 to 4.

In Formula (XVI), u represents an integer of 0 to 2.

In Formula (XX), i represents an integer of 1 to 4, or 1 to 3, or 1 to 2.

In all Formulae herein, it is assumed that if a particular position is not substituted with a non-hydrogen atom, a hydrogen atom is included at that position to include proper valence considerations.

In some embodiments, the sum of s and r is less than or equal to 5 in each instance of (L¹)_p-(Ar¹)_q group. For example, the sum of s and r may be less than or equal to 4, or less than or equal to 3. In some embodiments, the sum of p and q is equal to or greater than 1. For example, in each (L¹)_p-(Ar¹)_q group, at least one of p and q is a non-zero integer.

In some embodiments, in each instance of (L¹)_p-(Ar¹)_q group, L¹, or if p=0, Ar¹, is bonded to at least one of 1-, 2-, 4-, 5-, and/or 6-position of the substituted phenyl as indicated in the each formulae above. For example, in cases wherein r is 1, L¹ or Ar¹ of the (L¹)_p-(Ar¹)_q group is bonded to 1-, 2-, 4-, 5-, and/or 6-position of the substituted phenyl. In other non-limiting examples wherein r is 2, L¹ or Ar¹ from each (L¹)_p-(Ar¹)_q group is bonded at, for example, 1- and 4-positions, 1- and 5-positions, 2- and 4-positions, 2- and 5-positions, 2- and 6-positions, or 4- and 6-positions. In other non-limiting examples wherein r is 3, L¹ or Ar¹ from each (L¹)_p-(Ar¹)_q group is bonded to the substituted phenyl at 2-, 4-, and 6-positions. For example, one or more R¹ groups may be bonded to any available bonding site(s) of the substituted phenyl.

In some embodiments wherein r is 1, p is 1 or greater, and q is 1 or greater. For example, p is an integer of 1 to 5, an integer of 1 to 4, an integer of 1 to 3, or an integer of 1 to 2, and q is an integer of 1 to 6, an integer of 1 to 5, an integer of 1 to 4, an integer of 1 to 3, or an integer of 1 to 2.

In some embodiments wherein r is 2 or 3, p represents zero (0) or a non-zero integer in each instance, and q represents zero (0) or a non-zero integer in each instance, provided however that at least one instance of p is a non-zero integer, and at least one instance of q is a non-zero integer. It will generally be understood that, if p is 0 for a given instance, Ar¹ associated with such instance may be bonded directly to the substituted phenyl group. In some embodiments wherein r is 2 or 3, and at least one instance of p is 0, q associated with such at least one instance is 1.

In some embodiments wherein s is 2 or greater, two or more R¹ groups may bind to each other to form a ring or an aromatic structure.

In various embodiments described herein, a substituent group is indicated as R^x wherein x represents an integer. It will be appreciated that features generally described herein in relation to R^x may apply to any such substituent group, including but not limited to substituent groups represented as R¹, R², R³, R⁴, R⁵, unless otherwise specified.

In reference with regard to some embodiments of the substituent groups R^x, a represents an integer of 2 to 6 or an integer of 2 to 4. In some embodiments, b represents an integer of 1 to 4, or an integer of 1 to 3. In some embodiments, d represents an integer of 1 to 3, or an integer of 1 to 2. In some embodiments, e represents an integer of 1 to 4, or an integer of 1 to 3.

In some embodiments wherein two or more substituent groups, R^x, having the same value of x are provided in any single molecule, such two or more substituent groups may be fused to form one or more aryl groups or heteroaryl groups. For example, in a molecule containing two (s=2) R¹ substituent groups, the two R¹ may fuse together to form one or more aryl groups or heteroaryl groups, which may be bonded to the substituted phenyl of Formulae (I), (II), (III), (IV), (V), (VI), (VII), (VIII), (IX), (X), (XI), (XII), (XIII), (XIV), (XV), (XVI), (XVII), (XVIII), (XIX) and/or (XX) at two or more bonding positions due to the substituent groups being fused.

In some non-limiting examples, a (L¹)_p-(Ar¹)_q group is represented by a formula according to the following table. In any Formula containing two or more of L¹ and/or Ar¹ groups, the presence of each such group is indicated using a subscript for differentiation.

In various embodiments described herein, a molecule may include a substituted or unsubstituted aryl and/or a substituted or unsubstituted heteroaryl group. In some non-limiting example, L¹, Ar¹, and/or R^x may contain such aryl or heteroaryl group. In some embodiments, such aryl and heteroaryl group are represented by any of the following.

In each of Formula (AR-1) to (AR-31):

• • X independently represents N or CR⁴.
  • Q independently represents CR⁴R⁵, NR⁴, S, O, or SiR⁴R⁵.

R⁴ and R⁵ each independently represents H, D (deutero), F, Cl, alkyl including C1-C6 alkyl, cycloaklyl including C3-C6 cycloalkyl, alkoxy including C1-C6 alkoxy, aryl, fluoroalkyl, haloaryl, heteroaryl, haloalkoxy, fluoroaryl, fluoroalkoxy, fluoroalkylsulfanyl, fluoromethyl, difluoromethyl, trifluoromethyl, difluoromethoxy, trifluoromethoxy, fluoroethyl, polyfluoroethyl, 4-fluorophenyl, 3,4,5-trifluorophenyl, polyfluoroaryl, 4-(trifluoromethoxy)phenyl, SF₄Cl, SF₅, (CF₂)_aSF₅, (O(CF₂)_b)_dCF₃, (CF₂)_e(O(CF₂)_b)_d)CF₃, trifluoromethylsulfanyl, and a bond between the aryl or heteroaryl group and a part of the molecule to which the aryl or heteroaryl group is attached.

Some non-limiting examples of aryl and heteroaryl groups include the following.

It will be appreciated that any of the aryl or heteroaryl group according to Formulae (AN-1) to (AN-66), when representing L¹, Ar¹, and/or R^x, would be bonded to another part of the molecule at any carbon or heteroatom site available for formation of such bond(s). For example, in formulae containing a NH group, the hydrogen may be replaced with a “bond” to another part of the molecule such that, for example, a N—C bond is formed between the nitrogen of the heteroaryl group and a carbon of another part of the molecule.

In some embodiments, cycloalkyl may be represented by cyclopropyl, cyclobutyl, cyclopentyl, and/or cyclohexyl.

In some non-limiting examples, Ar¹ and/or R^x may include an aryl and/or a heteroaryl group represented by above Formulae (AR-1) to (AR-31) and (AN-1) to (AN-66).

In some non-limiting examples, substituted or unsubstituted arylene and/or substituted or unsubstituted heteroarylene according to various embodiments described herein may be represented by suitable substitutions of groups represented by any of Formulae (AR-1) to (AR-31) and (AN-1) to (AN-66). In some non-limiting examples, L₁ may include such arylene and/or heteroarylene groups.

In some embodiments, L¹ is independently selected from the following:

In Formula (LR-53), (LR-55), (LR-59), (LR-60) and (LR-62), R² and R³ each independently represents H, D (deutero), F, Cl, alkyl including C1-C6 alkyl, cycloaklyl including C3-C6 cycloalkyl, alkoxy including C1-C6 alkoxy, fluoroalkyl, haloaryl, heteroaryl, haloalkoxy, fluoroaryl, fluoroalkoxy, fluoroalkylsulfanyl, fluoromethyl, difluoromethyl, trifluoromethyl, difluoromethoxy, trifluoromethoxy, fluoroethyl, polyfluoroethyl, 4-fluorophenyl, 3,4,5-trifluorophenyl, polyfluoroaryl, 4-(trifluoromethoxy)phenyl, SF₄Cl, SF₅, (CF₂)_aSF₅, (O(CF₂)_b)_dCF₃, (CF₂)_e(O(CF₂)_b)_d)CF₃, or trifluoromethylsulfanyl.

In Formula (LR-59) and (LR-60), u represents an integer of 0 to 7, Q represents CR⁴R⁵, NR⁴, S, O, or SiR⁴R⁵, and Y represents CR⁴, N, or SiR⁴. In some embodiments, w represents an integer of 0 to 6.

In some embodiments, Ar¹ is selected from the following:

In some embodiments, R^x is independently selected from the following:

It will be appreciated that, in each of the L¹, Ar¹, and R^x groups illustrated above, additional substituents and/or additional bonds to such groups may be provided in some examples.

It will be appreciated that, in some embodiments wherein the molecule includes two or more of the same groups as represented in any of the formulae provided herein, such as for example, a molecule represented by a formula including two or more L¹ groups, two or more Ar¹ groups, and/or two or more R^x groups, each such group may be individually selected in each instance unless otherwise specified herein.

In some embodiments, a (L¹)_p-(Ar¹)_q group is represented by Formula (D-2). In some further embodiments, the bonding position of the (L¹)_p-(Ar¹)_q group to the substituted phenyl, L¹ and Ar¹ are selected from the following:

	Example	Bonding
	Number	Position	L1	Ar1
	D-2-1	1	(LR-14)	(AX-12)
	D-2-2	1	(LR-14)	(AX-2)
	D-2-3	1	(LR-14)	(AX-4)
	D-2-4	1	(LR-14)	(AX-47)
	D-2-5	1	(LR-14)	(AX-5)
	D-2-6	1	(LR-14)	(AX-8)
	D-2-7	1	(LR-25)	(AX-12)
	D-2-8	1	(LR-25)	(AX-2)
	D-2-9	1	(LR-25)	(AX-4)
	D-2-10	1	(LR-25)	(AX-47)
	D-2-11	1	(LR-25)	(AX-5)
	D-2-12	1	(LR-25)	(AX-8)
	D-2-13	1	(LR-26)	(AX-12)
	D-2-14	1	(LR-26)	(AX-2)
	D-2-15	1	(LR-26)	(AX-4)
	D-2-16	1	(LR-26)	(AX-47)
	D-2-17	1	(LR-26)	(AX-5)
	D-2-18	1	(LR-26)	(AX-8)
	D-2-19	1	(LR-34)	(AX-2)
	D-2-20	1	(LR-34)	(AX-4)
	D-2-21	1	(LR-34)	(AX-47)
	D-2-22	1	(LR-34)	(AX-47)
	D-2-23	1	(LR-34)	(AX-5)
	D-2-24	1	(LR-34)	(AX-8)
	D-2-25	6	(LR-14)	(AX-12)
	D-2-26	6	(LR-14)	(AX-2)
	D-2-27	6	(LR-14)	(AX-4)
	D-2-28	6	(LR-14)	(AX-47)
	D-2-29	6	(LR-14)	(AX-5)
	D-2-30	6	(LR-14)	(AX-8)
	D-2-31	6	(LR-25)	(AX-12)
	D-2-32	6	(LR-25)	(AX-2)
	D-2-33	6	(LR-25)	(AX-4)
	D-2-34	6	(LR-25)	(AX-47)
	D-2-35	6	(LR-25)	(AX-5)
	D-2-36	6	(LR-25)	(AX-8)
	D-2-37	6	(LR-26)	(AX-12)
	D-2-38	6	(LR-26)	(AX-2)
	D-2-39	6	(LR-26)	(AX-4)
	D-2-40	6	(LR-26)	(AX-47)
	D-2-41	6	(LR-26)	(AX-5)
	D-2-42	6	(LR-26)	(AX-8)
	D-2-43	6	(LR-34)	(AX-12)
	D-2-44	6	(LR-34)	(AX-2)
	D-2-45	6	(LR-34)	(AX-4)
	D-2-46	6	(LR-34)	(AX-47)
	D-2-47	6	(LR-34)	(AX-5)
	D-2-48	6	(LR-34)	(AX-8)

In some embodiments, a (L¹)_p-(Ar¹)_q group is represented by Formula (D-3). In some further embodiments, the bonding position of the (L¹)_p-(Ar¹)_q group to the substituted phenyl, L¹ and Ar¹ are selected from the following:

	Example	Bonding
	Number	Position	L11	L12	Ar1
	D-3-1	1	(LR-14)	(LR-3)	(AX-2)
	D-3-2	1	(LR-14)	(LR-3)	(AX-4)
	D-3-3	1	(LR-14)	(LR-4)	(AX-2)
	D-3-4	1	(LR-14)	(LR-54)	(AX-2)
	D-3-5	1	(LR-25)	(LR-3)	(AX-2)
	D-3-6	1	(LR-25)	(LR-3)	(AX-4)
	D-3-7	1	(LR-25)	(LR-4)	(AX-2)
	D-3-8	1	(LR-25)	(LR-54)	(AX-2)
	D-3-9	1	(LR-26)	(LR-3)	(AX-12)
	D-3-10	1	(LR-26)	(LR-3)	(AX-2)
	D-3-11	1	(LR-26)	(LR-4)	(AX-2)
	D-3-12	1	(LR-26)	(LR-54)	(AX-2)
	D-3-13	1	(LR-3)	(LR-14)	(AX-12)
	D-3-14	1	(LR-3)	(LR-14)	(AX-4)
	D-3-15	1	(LR-3)	(LR-14)	(AX-47)
	D-3-16	1	(LR-3)	(LR-14)	(AX-47)
	D-3-17	1	(LR-3)	(LR-25)	(AX-12)
	D-3-18	1	(LR-3)	(LR-25)	(AX-2)
	D-3-19	1	(LR-3)	(LR-25)	(AX-4)
	D-3-20	1	(LR-3)	(LR-25)	(AX-47)
	D-3-21	1	(LR-3)	(LR-25)	(AX-5)
	D-3-22	1	(LR-3)	(LR-25)	(AX-8)
	D-3-23	1	(LR-3)	(LR-26)	(AX-12)
	D-3-24	1	(LR-3)	(LR-26)	(AX-2)
	D-3-25	1	(LR-3)	(LR-26)	(AX-4)
	D-3-26	1	(LR-3)	(LR-26)	(AX-47)
	D-3-27	1	(LR-3)	(LR-26)	(AX-5)
	D-3-28	1	(LR-3)	(LR-26)	(AX-8)
	D-3-29	1	(LR-3)	(LR-34)	(AX-12)
	D-3-30	1	(LR-3)	(LR-34)	(AX-2)
	D-3-31	1	(LR-3)	(LR-34)	(AX-4)
	D-3-32	1	(LR-3)	(LR-34)	(AX-47)
	D-3-33	1	(LR-3)	(LR-34)	(AX-5)
	D-3-34	1	(LR-3)	(LR-34)	(AX-8)
	D-3-35	1	(LR-34)	(LR-3)	(AX-2)
	D-3-36	1	(LR-34)	(LR-3)	(AX-4)
	D-3-37	1	(LR-34)	(LR-4)	(AX-2)
	D-3-38	1	(LR-34)	(LR-54)	(AX-2)
	D-3-39	1	(LR-4)	(LR-14)	(AX-12)
	D-3-40	1	(LR-4)	(LR-14)	(AX-2)
	D-3-41	1	(LR-4)	(LR-14)	(AX-2)
	D-3-42	1	(LR-4)	(LR-14)	(AX-4)
	D-3-43	1	(LR-4)	(LR-14)	(AX-47)
	D-3-44	1	(LR-4)	(LR-14)	(AX-5)
	D-3-45	1	(LR-4)	(LR-14)	(AX-5)
	D-3-46	1	(LR-4)	(LR-14)	(AX-8)
	D-3-47	1	(LR-4)	(LR-14)	(AX-8)
	D-3-48	1	(LR-4)	(LR-25)	(AX-12)
	D-3-49	1	(LR-4)	(LR-25)	(AX-2)
	D-3-50	1	(LR-4)	(LR-25)	(AX-4)
	D-3-51	1	(LR-4)	(LR-25)	(AX-47)
	D-3-52	1	(LR-4)	(LR-25)	(AX-5)
	D-3-53	1	(LR-4)	(LR-25)	(AX-8)
	D-3-54	1	(LR-4)	(LR-26)	(AX-12)
	D-3-55	1	(LR-4)	(LR-26)	(AX-2)
	D-3-56	1	(LR-4)	(LR-26)	(AX-4)
	D-3-57	1	(LR-4)	(LR-26)	(AX-47)
	D-3-58	1	(LR-4)	(LR-26)	(AX-5)
	D-3-59	1	(LR-4)	(LR-26)	(AX-8)
	D-3-60	1	(LR-4)	(LR-34)	(AX-12)
	D-3-61	1	(LR-4)	(LR-34)	(AX-2)
	D-3-62	1	(LR-4)	(LR-34)	(AX-4)
	D-3-63	1	(LR-4)	(LR-34)	(AX-47)
	D-3-64	1	(LR-4)	(LR-34)	(AX-5)
	D-3-65	1	(LR-4)	(LR-34)	(AX-8)
	D-3-66	6	(LR-14)	(LR-3)	(AX-2)
	D-3-67	6	(LR-14)	(LR-3)	(AX-4)
	D-3-68	6	(LR-14)	(LR-4)	(AX-2)
	D-3-69	6	(LR-14)	(LR-54)	(AX-2)
	D-3-70	6	(LR-25)	(LR-3)	(AX-2)
	D-3-71	6	(LR-25)	(LR-3)	(AX-4)
	D-3-72	6	(LR-25)	(LR-4)	(AX-2)
	D-3-73	6	(LR-25)	(LR-54)	(AX-2)
	D-3-74	6	(LR-26)	(LR-3)	(AX-2)
	D-3-75	6	(LR-26)	(LR-3)	(AX-4)
	D-3-76	6	(LR-26)	(LR-4)	(AX-2)
	D-3-77	6	(LR-26)	(LR-54)	(AX-12)
	D-3-78	6	(LR-34)	(LR-3)	(AX-2)
	D-3-79	6	(LR-34)	(LR-3)	(AX-4)
	D-3-80	6	(LR-34)	(LR-4)	(AX-2)
	D-3-81	6	(LR-34)	(LR-54)	(AX-2)
	D-3-82	6	(LR-4)	(LR-14)	(AX-12)
	D-3-83	6	(LR-4)	(LR-14)	(AX-2)
	D-3-84	6	(LR-4)	(LR-14)	(AX-4)
	D-3-85	6	(LR-4)	(LR-14)	(AX-47)
	D-3-86	6	(LR-4)	(LR-14)	(AX-5)
	D-3-87	6	(LR-4)	(LR-14)	(AX-8)
	D-3-88	6	(LR-4)	(LR-25)	(AX-12)
	D-3-89	6	(LR-4)	(LR-25)	(AX-2)
	D-3-90	6	(LR-4)	(LR-25)	(AX-4)
	D-3-91	6	(LR-4)	(LR-25)	(AX-47)
	D-3-92	6	(LR-4)	(LR-25)	(AX-5)
	D-3-93	6	(LR-4)	(LR-25)	(AX-8)
	D-3-94	6	(LR-4)	(LR-26)	(AX-12)
	D-3-95	6	(LR-4)	(LR-26)	(AX-2)
	D-3-96	6	(LR-4)	(LR-26)	(AX-4)
	D-3-97	6	(LR-4)	(LR-26)	(AX-47)
	D-3-98	6	(LR-4)	(LR-26)	(AX-5)
	D-3-99	6	(LR-4)	(LR-26)	(AX-8)
	D-3-100	6	(LR-4)	(LR-34)	(AX-12)
	D-3-101	6	(LR-4)	(LR-34)	(AX-2)
	D-3-102	6	(LR-4)	(LR-34)	(AX-4)
	D-3-103	6	(LR-4)	(LR-34)	(AX-47)
	D-3-104	6	(LR-4)	(LR-34)	(AX-5)
	D-3-105	6	(LR-4)	(LR-34)	(AX-8)

In some embodiments, a (L¹)_p-(Ar¹)_q group is represented by Formula (D-4). In some further embodiments, the bonding position of the (L¹)_p-(Ar¹)_q group to the substituted phenyl, L¹ and Ar¹ are selected from the following:

Example	Bonding
Number	Position	L11	L12	L13	Ar1
D-4-1	1	(LR-3)	(LR-14)	(LR-3)	(AX-4)
D-4-2	1	(LR-3)	(LR-14)	(LR-4)	(AX-2)
D-4-3	1	(LR-3)	(LR-14)	(LR-54)	(AX-2)
D-4-4	1	(LR-3)	(LR-25)	(LR-3)	(AX-2)
D-4-5	1	(LR-3)	(LR-25)	(LR-3)	(AX-4)
D-4-6	1	(LR-3)	(LR-25)	(LR-4)	(AX-2)
D-4-7	1	(LR-3)	(LR-25)	(LR-54)	(AX-2)
D-4-8	1	(LR-3)	(LR-26)	(LR-3)	(AX-2)
D-4-9	1	(LR-3)	(LR-26)	(LR-3)	(AX-4)
D-4-10	1	(LR-3)	(LR-26)	(LR-4)	(AX-2)
D-4-11	1	(LR-3)	(LR-26)	(LR-54)	(AX-2)
D-4-12	1	(LR-3)	(LR-34)	(LR-3)	(AX-2)
D-4-13	1	(LR-3)	(LR-34)	(LR-3)	(AX-4)
D-4-14	1	(LR-3)	(LR-34)	(LR-4)	(AX-2)
D-4-15	1	(LR-3)	(LR-34)	(LR-54)	(AX-2)
D-4-16	1	(LR-4)	(LR-14)	(LR-3)	(AX-2)
D-4-17	1	(LR-4)	(LR-14)	(LR-3)	(AX-4)
D-4-18	1	(LR-4)	(LR-14)	(LR-4)	(AX-2)
D-4-19	1	(LR-4)	(LR-14)	(LR-54)	(AX-2)
D-4-20	1	(LR-4)	(LR-25)	(LR-3)	(AX-2)
D-4-21	1	(LR-4)	(LR-25)	(LR-3)	(AX-4)
D-4-22	1	(LR-4)	(LR-25)	(LR-4)	(AX-2)
D-4-23	1	(LR-4)	(LR-25)	(LR-54)	(AX-2)
D-4-24	1	(LR-4)	(LR-26)	(LR-3)	(AX-2)
D-4-25	1	(LR-4)	(LR-26)	(LR-3)	(AX-4)
D-4-26	1	(LR-4)	(LR-26)	(LR-4)	(AX-2)
D-4-27	1	(LR-4)	(LR-26)	(LR-54)	(AX-2)
D-4-28	1	(LR-4)	(LR-34)	(LR-3)	(AX-2)
D-4-29	1	(LR-4)	(LR-34)	(LR-3)	(AX-4)
D-4-30	1	(LR-4)	(LR-34)	(LR-4)	(AX-2)
D-4-31	1	(LR-4)	(LR-34)	(LR-54)	(AX-2)
D-4-32	6	(LR-4)	(LR-14)	(LR-3)	(AX-2)
D-4-33	6	(LR-4)	(LR-14)	(LR-3)	(AX-4)
D-4-34	6	(LR-4)	(LR-14)	(LR-4)	(AX-2)
D-4-35	6	(LR-4)	(LR-14)	(LR-54)	(AX-2)
D-4-36	6	(LR-4)	(LR-25)	(LR-3)	(AX-2)
D-4-37	6	(LR-4)	(LR-25)	(LR-3)	(AX-4)
D-4-38	6	(LR-4)	(LR-25)	(LR-4)	(AX-2)
D-4-39	6	(LR-4)	(LR-25)	(LR-54)	(AX-2)
D-4-40	6	(LR-4)	(LR-26)	(LR-3)	(AX-2)
D-4-41	6	(LR-4)	(LR-26)	(LR-3)	(AX-4)
D-4-42	6	(LR-4)	(LR-26)	(LR-4)	(AX-2)
D-4-43	6	(LR-4)	(LR-26)	(LR-54)	(AX-2)
D-4-44	6	(LR-4)	(LR-34)	(LR-3)	(AX-2)
D-4-45	6	(LR-4)	(LR-34)	(LR-3)	(AX-4)
D-4-46	6	(LR-4)	(LR-34)	(LR-4)	(AX-2)
D-4-47	6	(LR-4)	(LR-34)	(LR-54)	(AX-2)

In some non-limiting examples, the NIC contains a compound having the structure derived by bonding any of the (L¹)_p-(Ar¹)_q group listed above to the substituted phenyl according to any of Formulae (I), (II), (III), (IV), (V), (VI), (VII), (VIII), (IX), (X), (XI), (XII), (XIII), (XIV), (XV), (XVI), (XVII), (XVIII), (XIX) and/or (XX). In some further non-limiting examples, R¹ is independently selected from: H, D, F, trifluoromethyl, and trifluoromethoxy. In some further non-limiting examples, any R¹ present is selected from H and D. In some embodiments, r is 2. In some other embodiments, r is 1.

In some embodiments, the molecular weight of the compound is less than or equal to about 2200 g/mol. For example, the molecular weight of the compound may be less than about 2000 g/mol, less than about 1900 g/mol, less than about 1800 g/mol, less than about 1750 g/mol, less than about 1600 g/mol, less than about 1500 g/mol, less than about 1400 g/mol, less than about 1300 g/mol, less than about 1200 g/mol, less than about 1100 g/mol, less than about 1000 g/mol, less than about 900 g/mol, or less than about 800 g/mol.

In some embodiments, the molecular weight of the compound is greater than or equal to about 200 g/mol. For example, the molecular weight of the compound may be greater than or equal to about 250 g/mol, greater than or equal to about 300 g/mol, greater than or equal to about 330 g/mol, greater than or equal to about 350 g/mol, greater than or equal to about 400 g/mol, greater than or equal to about 450 g/mol, or greater than or equal to about 500 g/mol.

In some embodiments, the molecular weight of the compound is from about 200 g/mol to about 2200 g/mol. For example, the molecular weight of the compound may be from about 250 g/mol to about 2000 g/mol, from about 250 g/mol to about 1750 g/mol, from about 250 g/mol to about 1600 g/mol, from about 250 g/mol to about 1500 g/mol, from about 300 g/mol to about 1500 g/mol, from about 250 g/mol to about 1300 g/mol, from about 330 g/mol to about 1200 g/mol, from about 350 g/mol to about 1100 g/mol, or from about 350 g/mol to about 1000 g/mol.

In some embodiments, the molecular weight of the compound is from about 400 g/mol to about 1200 g/mol. For example, the molecular weight of the compound may be from about 400 g/mol to about 1000 g/mol, from about 400 g/mol to about 950 g/mol, from about 400 g/mol to about 900 g/mol, from about 400 g/mol to about 850 g/mol, from about 400 g/mol to about 800 g/mol, from about 400 g/mol to about 750 g/mol, from about 400 g/mol to about 700 g/mol, from about 450 g/mol to about 1200 g/mol, from about 450 g/mol to 1000 g/mol, from about 450 g/mol to about 900 g/mol, from about 450 g/mol to 800 g/mol, from about 450 g/mol to 750 g/mol, from about 450 g/mol to 700 g/mol, from about 500 g/mol to 1200 g/mol from about 500 g/mol to 1000 g/mol, from about 600 g/mol to 1200 g/mol, from about 600 g/mol to 1000 g/mol, from about 700 g/mol to 1200 g/mol, from about 700 g/mol to 1000 g/mol or from about 700 g/mol to 900 g/mol.

For example, the ratio of the number of fluorine atoms to the number of carbon atoms in a given molecular structure of a compound may be referred to as “fluorine:carbon” ratio or as “F:C”. In some embodiments, NIC contains a compound having an F:C of between about 1:50 and about 1:2. In some embodiments, the F:C is between about 1:45 and about 1:3, between about 1:40 and about 1:4, between about 1:35 and about 1:5, between about 1:30 and about 1:5, between about 1:25 and about 1:5, between about 1:20 and about 1:5, between about 1:15 and about 1:5, between about 1:10 and about 1:5, between about 1:20 and about 1:3, between about 1:11 and about 1:2, between about 1:9 and about 1:4, or between 1:8 and about 1:5. In some embodiments, F:C is between 1:7 and about 1:6.

In some embodiments wherein the NIC contains a compound according to Formula (VI) and/or (XV), the ratio of the number of sulphur atoms to the number of fluorine atoms in a given molecule may be represented as “sulphur to fluorine ratio” or as “S:F”. In some embodiments, S:F is between about 1:35 and about 1:2. In some embodiments, S:F is between about 1:33 and about 1:4. In some embodiments, S:F is between about 1:31 and about 1:5. In some embodiments, S:F is between about 1:29 and about 1:6. In some embodiments, S:F is between about 1:23 and about 1:7. In some embodiments, S:F is between 1:19 and about 1:8. In some embodiments, S:F is between 1:15 and about 1:9. In some embodiments, S:F is between 1:13 and about 1:11. In some further embodiments, the oxidation state of sulphur is 6+. In some embodiments, the ratio of the number of sulphur atoms in the oxidation state of 6+ to the number of fluorine atoms in a given molecule is between about 1:35 and about 1:2, between about 1:33 and about 1:4, between about 1:29 and about 1:5, between about 1:27 and about 1:6, between about 1:23 and about 1:7, between about 1:19 and about 1:8. between about 1:15 and about 1:9, or between about 1:13 and about 1:10.

For example, the ratio of the number of sulphur atoms to the number of carbon atoms in a given molecule may be represented as “sulphur to carbon ratio” or as “S:C”. In some embodiments, S:C is between about 1:51 and about 1:11. In some embodiments, S:C is between about 1:49 and about 1:13. In some embodiments, S:C is between about 1:47 and about 1:15. In some embodiments, S:C is between about 1:45 and about 1:18. In some embodiments, S:C is between about 1:43 and about 1:23. In some embodiments, S:C is between about 1:41 and about 1:26. In some embodiments, S:C is between about 1:39 and about 1:29. In some embodiments, S:C is between about 1:37 and about 1:31. In some embodiments, S:C is between about 1:36 and about 1:33.

For example, the ratio of the number of sulphur atoms to the number of fluorine atoms to the number of carbon atoms in a given molecule may be represented as “sulphur to fluorine to carbon ratio” or as “S:F:C”. In some embodiments, S:F:C is between about 1:35:51 and about 1:4:11. In some embodiments, S:F:C is between about 1:33:49 and about 1:5:12. In some embodiments, S:F:C is between about 1:31:47 and about 1:6:13. In some embodiments, S:F:C is between about 1:29:45 and about 1:7:15. In some embodiments, S:F:C is between about 1:27:43 and about 1:9:17. In some embodiments, S:F:C is between about 1:25:41 and about 1:11:19. In some embodiments, S:F:C is between about 1:23:39 and about 1:13:21. In some embodiments, S:F:C is between about 1:21:37 and about 1:15:23. In some embodiments, S:F:C is between about 1:19:35 and about 1:17:25. In some embodiments, S:F:C is between about 1:17:33 and about 1:18:23.

Various compounds described herein may be synthesised by carrying out various chemical reactions known in the art. One example of such reaction is Suzuki coupling reaction. It is a type of cross-coupling reaction where an aromatic halogen compound reacts with a boronic acid derivative using a palladium catalyst and a base. The boronic acid derivative may be used singly or in combination of two or more.

Suzuki coupling reaction is illustrated by the following Reaction Scheme 1.

In the above illustrated scheme, the aromatic halogen compound (A-X′) reacts with boronic acid derivative (X″-T) to form A-B. A and B represent the organic compounds, X′ represents a halogen, preferably bromo and X″ is a B(OH)₂.

In few of the embodiments, A is represented by fluorinated derivative of phenyl of the above compounds represented by Formula (I) and B is represented by L¹-Ar¹ derivative of the Formula (I).

Other examples of reaction schemes which may be used in synthesis of various compounds are described, for example, in Savoie, Paul R., and John T. Welch. “Preparation and utility of organic pentafluorosulfanyl-containing compounds.” Chemical reviews 115.2 (2015): 1130-1190.

In some non-limiting examples, the NIC 810 may act as an optical coating. In some non-limiting examples, the NIC 810 may modify at least property and/or characteristic of the light emitted from at least one emissive region 1910 of the device 100. In some non-limiting examples, the NIC 810 may exhibit a degree of haze, causing emitted light to be scattered. In some non-limiting examples, the NIC 810 may comprise a crystalline material for causing light transmitted therethrough to be scattered. Such scattering of light may facilitate enhancement of the outcoupling of light from the device in some non-limiting examples, In some non-limiting examples, the NIC 810 may initially be deposited as a substantially non-crystalline, including without limitation, substantially amorphous, coating, whereupon, after deposition thereof, the NIC 810 may become crystallized and thereafter serve as an optical coupling.

Where features or aspects of the present disclosure are described in terms of Markush groups, it will be appreciated by those having ordinary skill in the relevant art that the present disclosure is also thereby described in terms of any individual member of sub-group of members of such Markush group.

Aspects of some non-limiting examples will now be illustrated and described with reference to the following examples, which are not intended to limit the scope of the present disclosure in any way.

EXAMPLES

Synthesis of Compound Example 1: 4-(10-(phenanthren-9-yl)anthracen-9-yl)phenyl)pentafluoro Sulfane

The following reagents were mixed in a 500 mL reaction vessel: 9-bromo-10-(phenanthrene-9-yl) anthracene (1.600 g, 3.69 mmol); tetrakis(triphenylphosphine)palladium (0) (Pd(PPh₃)₄, 0.0363 g, 0.03 mmol); potassium carbonate (K₂CO₃, 0.8679 g, 6.28 mmol); and 3.13 mmol of a boronic acid. In the present example, (4-(pentafluoro-16-sulfanyl)phenyl)boronic acid (0.777 g) was used as the boronic acid. The reaction vessel containing the mixture was placed on a heating plate mantle and stirred using a magnetic stirrer. The reaction vessel was also connected to a water condenser. A well stirred 150 mL solvent mixture containing a 9:1 volumetric ratio of N-ethyl-2-pyrrolidine (NMP) and water was added to the flask. The reaction mixture was then heated to 90° C. and left over-night to react. After cooling the flask to room temperature, The reaction mixture was precipitated in an aqueous solution of NaOH (0.2 M, 3.2 L) and stirred for 40 minutes. The resulting product was isolated by filtration, washed with water, followed by air drying at 75° C. The product was further purified using train sublimation. Yield after purification was 1.72 g (83.7%). The yield of the sublimation step was approximately 1.2 g (58.4%).

Synthesis of Compound Example 2: 4-(9,10-di(naphthalen-2-yl)anthracen-2-yl)phenyl)pentafluoro-sulfane

The following reagents were mixed in a 500 mL reaction vessel: 9-bromo-9,10-dinaphthalen-2-yl) anthracene (1.996 g, 3.92 mmol); tetrakis(triphenylphosphine)palladium (0) (Pd(PPh₃)₄, 0.451 g, 0.39 mmol); potassium carbonate (K₂CO₃, 1.09 g, 7.89 mmol); and 5.20 mmol of a boronic acid. In the present example, (4-(pentafluoro-16-sulfanyl)phenyl)boronic acid (1.29 g) was used as the boronic acid. The reaction vessel containing the mixture was placed on a heating plate mantle and stirred using a magnetic stirrer. The reaction vessel was also connected to a water condenser. A well stirred 150 mL solvent mixture containing a 9:1 volumetric ratio of N-ethyl-2-pyrrolidine (NMP) and water was added to the flask. The reaction mixture was then heated to 90° C. and left over-night to react. After cooling the flask to room temperature, the reaction mixture was precipitated in an aqueous solution of NaOH (0.2 M, 3.2 L) and stirred for 40 minutes. The resulting product was isolated by filtration, washed with water, followed by air drying at 75° C. The product was further purified using train sublimation. Yield after purification was 1.3585 g (54.8%). The yield of the sublimation step was approximately 1.002 g 40.4%).

As used in the examples herein, a reference to a layer thickness of a material refers to an amount of the material deposited on a target surface (and/or target region(s) and/or portion(s) thereof of the surface in the case of selective deposition), which corresponds to an amount of the material to cover the target surface with a uniformly thick layer of the material having the referenced layer thickness. By way of example, depositing a layer thickness of 10 nm indicates that an amount of the material deposited on the surface corresponds to an amount of the material to form a uniformly thick layer of the material that is 10 nm thick. It will be appreciated that, by way of non-limiting example, due to possible stacking and/or clustering of molecules and/or atoms, an actual thickness of the deposited material may be non-uniform. By way of non-limiting example, depositing a layer thickness of 10 nm may yield some portions of the deposited material having an actual thickness greater than 10 nm, and/or other portions of the deposited material having an actual thickness less than 10 nm. A certain layer thickness of a material deposited on a surface can correspond to an average thickness of the deposited material across the surface.

A series of samples were fabricated by depositing an NIC 910 having a thickness of about 50 nm over a glass substrate. The surface of the NIC 910 was then subjected to open mask deposition of Mg. Each sample was subjected to an Mg vapor flux having an average evaporation rate of about 50 Å/s. In conducting the deposition of the Mg coating, a deposition time of about 100 seconds was used in order to obtain a reference layer thickness of Mg of about 500 nm.

Once the samples were fabricated, optical transmission measurements were taken to determine the relative amount of Mg deposited on the surface of the NIC 910. As will be appreciated, relatively thin Mg coatings having, by way of non-limiting example, thickness of less than a few nm are substantially transparent. However, light transmission decreases as the thickness of the Mg coating is increased. Accordingly, the relative performance of various NIC 910 materials may be assessed by measuring the light transmission through the samples, which directly correlates to the amount and/or thickness of Mg coating deposited thereon from the Mg deposition process. Upon accounting for any loss and/or absorption of light caused by the presence of the glass substrate and the NIC 910, it was found that both the sample prepared using Compound Example 1 as the NIC and another sample prepared using Compound Example 2 as the NIC exhibited relatively high transmission of greater than about 90% across the visible portion of the electromagnetic spectrum. High optical transmission can directly be attributed to a relatively small amount of Mg coating, if any, being present on the surface of the NIC 910 to absorb the light being transmitted through the sample. Accordingly, these NIC 910 materials generally exhibit relatively low affinity and/or initial sticking probability S₀ to Mg and thus may be particularly useful for achieving selective deposition and patterning of Mg coating in certain applications.

As used in this and other examples described herein, a reference layer thickness refers to a layer thickness of Mg that is deposited on a reference surface exhibiting a high initial sticking probability S₀ (e.g., a surface with an initial sticking probability S₀ of about and/or close to 1.0). Specifically, for these examples, the reference surface was a surface of a quartz crystal positioned inside a deposition chamber for monitoring a deposition rate and the reference layer thickness. In other words, the reference layer thickness does not indicate an actual thickness of Mg deposited on a target surface (i.e., a surface of the NIC 910). Rather, the reference layer thickness refers to the layer thickness of Mg that would be deposited on the reference surface upon subjecting the target surface and reference surface to identical Mg vapor flux for the same deposition period (i.e. the surface of the quartz crystal). As would be appreciated, in the event that the target surface and reference surface are not subjected to identical vapor flux simultaneously during deposition, an appropriate tooling factor may be used to determine and monitor the reference thickness.

Terminology

References in the singular form include the plural and vice versa, unless otherwise noted.

As used herein, relational terms, such as “first” and “second”, and numbering devices such as “a”, “b” and the like, may be used solely to distinguish one entity or element from another entity or element, without necessarily requiring or implying any physical or logical relationship or order between such entities or elements.

The terms “including” and “comprising” are used expansively and in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to”. The terms “example” and “exemplary” are used simply to identify instances for illustrative purposes and should not be interpreted as limiting the scope of the invention to the stated instances. In particular, the term “exemplary” should not be interpreted to denote or confer any laudatory, beneficial or other quality to the expression with which it is used, whether in terms of design, performance or otherwise.

The terms “couple” and “communicate” in any form are intended to mean either a direct connection or indirect connection through some interface, device, intermediate component or connection, whether optically, electrically, mechanically, chemically, or otherwise.

The terms “on” or “over” when used in reference to a first component relative to another component, and/or “covering” or which “covers” another component, may encompass situations where the first component is direct on (including without limitation, in physical contact with) the other component, as well as cases where one or more intervening components are positioned between the first component and the other component.

Directional terms such as “upward”, “downward”, “left” and “right” are used to refer to directions in the drawings to which reference is made unless otherwise stated. Similarly, words such as “inward” and “outward” are used to refer to directions toward and away from, respectively, the geometric center of the device, area or volume or designated parts thereof. Moreover, all dimensions described herein are intended solely to be by way of example of purposes of illustrating certain embodiments and are not intended to limit the scope of the disclosure to any embodiments that may depart from such dimensions as may be specified.

As used herein, the terms “substantially”, “substantial”, “approximately” and/or “about” are used to denote and account for small variations. When used in conjunction with an event or circumstance, such terms can refer to instances in which the event or circumstance occurs precisely, as well as instances in which the event or circumstance occurs to a close approximation. By way of non-limiting example, when used in conjunction with a numerical value, such terms may refer to a range of variation of less than or equal to ±10% of such numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, and/or less than equal to ±0.05%.

As used herein, the phrase “consisting substantially of” will be understood to include those elements specifically recited and any additional elements that do not materially affect the basic and novel characteristics of the described technology, while the phrase “consisting of” without the use of any modifier, excludes any element not specifically recited.

As will be understood by those having ordinary skill in the relevant art, for any and all purposes, particularly in terms of providing a written description, all ranges disclosed herein also encompass any and all possible sub-ranges and/or combinations of sub-ranges thereof. Any listed range may be easily recognized as sufficiently describing and/or enabling the same range being broken down at least into equal fractions thereof, including without limitation, halves, thirds, quarters, fifths, tenths etc. As a non-limiting example, each range discussed herein may be readily be broken down into a lower third, middle third and/or upper third, etc.

As will also be understood by those having ordinary skill in the relevant art, all language and/or terminology such as “up to”, “at least”, “greater than”, “less than”, and the like, may include and/or refer the recited range(s) and may also refer to ranges that may be subsequently broken down into sub-ranges as discussed herein.

As will be understood by those having ordinary skill in the relevant art, a range includes each individual member of the recited range.

General

The purpose of the Abstract is to enable the relevant patent office or the public generally, and specifically, persons of ordinary skill in the art who are not familiar with patent or legal terms or phraseology, to quickly determine from a cursory inspection, the nature of the technical disclosure. The Abstract is neither intended to define the scope of this disclosure, nor is it intended to be limiting as to the scope of this disclosure in any way.

The structure, manufacture and use of the presently disclosed examples have been discussed above. The specific examples discussed are merely illustrative of specific ways to make and use the concepts disclosed herein, and do not limit the scope of the present disclosure. Rather, the general principles set forth herein are considered to be merely illustrative of the scope of the present disclosure.

It should be appreciated that the present disclosure, which is described by the claims and not by the implementation details provided, and which can be modified by varying, omitting, adding or replacing and/or in the absence of any element(s) and/or limitation(s) with alternatives and/or equivalent functional elements, whether or not specifically disclosed herein, will be apparent to those having ordinary skill in the relevant art, may be made to the examples disclosed herein, and may provide many applicable inventive concepts that may be embodied in a wide variety of specific contexts, without straying from the present disclosure.

In particular, features, techniques, systems, sub-systems and methods described and illustrated in one or more of the above-described examples, whether or not described an illustrated as discrete or separate, may be combined or integrated in another system without departing from the scope of the present disclosure, to create alternative examples comprised of a combination or sub-combination of features that may not be explicitly described above, or certain features may be omitted, or not implemented. Features suitable for such combinations and sub-combinations would be readily apparent to persons skilled in the art upon review of the present application as a whole. Other examples of changes, substitutions, and alterations are easily ascertainable and could be made without departing from the spirit and scope disclosed herein.

All statements herein reciting principles, aspects and examples of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof and to cover and embrace all suitable changes in technology. Additionally, it is intended that such equivalents include both currently-known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

Accordingly, the specification and the examples disclosed therein are to be considered illustrative only, with a true scope of the disclosure being disclosed by the following numbered claims:

Claims

1. An opto-electronic device comprising: a nucleating inhibiting coating (NIC) disposed on a first layer surface of the device in a first portion of a lateral aspect thereof; anda conductive coating disposed on a second layer surface of the device in a second portion of the lateral aspect thereof;wherein an initial sticking probability for forming the conductive coating onto a surface of the NIC in the first portion, is substantially less than the initial sticking probability for forming the conductive coating onto the surface in the second portion, such that the surface of the NIC in the first portion is substantially devoid of the conductive coating; andwherein the NIC comprises a compound of Formula (I), (II), (III), (IV), (V), (VI), (VII), (VIII), (IX), (X), (XI), (XII), (XIII), (XIV), (XV), (XVI), (XVII), (XVIII), (XIX) and/or (XX):

2. The opto-electronic device of claim 1, wherein the first portion comprises at least one emissive region.

3. The opto-electronic device of claim 2, wherein a thickness of the NIC in the at least one emissive region of the first portion is modulated to adjust an optical microcavity effect thereof.

4. The opto-electronic device of claim 2, wherein at least a second part of the second portion overlaps at least a first part of the first portion, wherein a cross-sectional thickness of the conductive coating in the second part is less than a cross-sectional thickness of the conductive coating in a remaining part of the second portion.

5. The opto-electronic device of claim 4, wherein the conductive coating is disposed over the NIC along at least a section of the first portion proximate to the first part.

6. The opto-electronic device of claim 5, wherein the conductive coating is spaced apart from the NIC in a cross-sectional aspect.

7. The opto-electronic device of claim 4, wherein the conductive coating abuts the NIC at a boundary between the first part and the second portion.

8. The opto-electronic device of claim 7, wherein the conductive coating forms a contact angle with the NIC at the boundary.

9. The opto-electronic device of claim 8, wherein the contact angle exceeds 10 degrees.

10. The opto-electronic device of claim 8, wherein the contact angle exceeds 90 degrees.

11. The opto-electronic device of claim 2, wherein at least a first part of the first portion overlaps at least a second part of the second portion.

12. The opto-electronic device of claim 11, wherein the NIC is disposed on the surface of the device in the second part and the conductive coating is disposed over the NIC therein.

13. The opto-electronic device of claim 12, wherein the conductive coating is spaced apart from the NIC in a cross-sectional aspect.

14. The opto-electronic device of claim 2, wherein the second part extends between the first part and a third part of the second portion that includes the at least one emissive region.

15. The opto-electronic device of claim 14, wherein the at least one emissive region of the third part comprises a first electrode, a second electrode electrically coupled to the conductive coating and a semiconducting layer between the first electrode and the second electrode, wherein the second electrode extends between the NIC and the semiconducting layer in the third part.

16. The opto-electronic device of claim 2, wherein the conductive coating is electrically coupled to an auxiliary electrode.

17. The opto-electronic device of claim 16 wherein the conductive coating is in physical contact with the auxiliary electrode.

18. The opto-electronic device of claim 16, wherein the auxiliary electrode lies in the first part.

19. The opto-electronic device of claim 1, wherein the second portion comprises at least a part of a non-emissive region.

20. The opto-electronic device of claim 3, further comprising a first electrode, a second electrode and a semiconducting layer between the first electrode and the second electrode, wherein the second electrode extends between the NIC and the semiconducting layer in the first portion.

21. The opto-electronic device of claim 20, wherein the conductive coating is electrically coupled to the second electrode.

22. The opto-electronic device of claim 20, wherein the conductive coating coats at least a part of the second electrode in the second portion.

23. The opto-electronic device of claim 20, wherein the second portion comprises at least one additional emissive region.

24. The opto-electronic device of claim 23, wherein at least one of the additional emissive regions of the second portion of the device comprises a first electrode, a second electrode and a semiconducting layer between the first electrode and the second electrode, wherein the second electrode comprises the conductive coating.

25. The opto-electronic device of claim 23, wherein a wavelength of light emitted from the at least one additional emissive region of the second portion of the device differs from a wavelength of light emitted from the at least one emissive region of the first portion of the device.

26. The opto-electronic device of claim 20, wherein the conductive coating comprises an auxiliary electrode.

27. The opto-electronic device of claim 1, comprising at least one intermediate coating between the second electrode and the conductive coating along at least a part thereof.

28. The opto-electronic device of claim 27, wherein the intermediate coating comprises a nucleation promoting coating (NPC).

29. The opto-electronic device of claim 27, wherein the intermediate coating comprises an NIC that has been processed to substantially increase the initial sticking probability for forming the conductive coating onto the surface thereof.

30. The opto-electronic device of claim 29, wherein the intermediate coating has been processed by exposure to radiation.

31. The opto-electronic device of claim 1, wherein the second portion comprises a partition and a third electrode in a sheltered region of the partition; and wherein the conductive coating is electrically coupled to the second electrode and to the third electrode.

32. The opto-electronic device of claim 31, wherein the sheltered region is substantially devoid of the NIC.

33. The opto-electronic device of claim 31, wherein the sheltered region comprises a recess defined by the partition.

34. The opto-electronic device of claim 1, wherein the conductive coating is in physical contact with the third electrode.

35. The opto-electronic device of claim 1, wherein the conductive coating is electrically coupled to the second electrode in a coupling region (CR).

36. The opto-electronic device of claim 1, wherein the sheltered region comprises an aperture defined by the partition.

37. The opto-electronic device of claim 36, wherein the aperture is angled relative to an axis extending normally away from a surface of the device.

38. The opto-electronic device of claim 36, further comprising an undercut portion that overlaps a third layer surface of the third electrode in a cross-sectional aspect.

39. The opto-electronic device of claim 1 wherein the second portion comprises at least one emissive region.

40. The opto-electronic device of claim 39, wherein the first portion comprises at least a part of a non-emissive region.

41. The opto-electronic device of claim 39, wherein the first portion is substantially light-transmissive therethrough.

42. The opto-electronic device of claim 39, further comprising a first electrode, a second electrode and a semiconducting layer between the first electrode and the second electrode, wherein the second electrode extends between the NIC and the semiconducting layer in the first portion.

43. The opto-electronic device of claim 42, wherein the second electrode extends between the conductive coating and the semiconducting layer in the second portion.

44. The opto-electronic device of claim 39, further comprising a first electrode, a semiconducting layer between the first electrode and the conductive coating, wherein the conductive coating comprises a second electrode of the device.

45. The opto-electronic device of claim 1, wherein Ar1 represents cyclopentadienyl; phenyl; 1-naphthyl; 2-naphthyl; 1-phenanthryl; 2-phenanthryl; 10-phenanthryl; 9-phenanthryl; 1-anthracenyl; 2-anthracenyl; 3-anthracenyl; 9-anthracenyl; benzanthracenyl; pyrenyl; chrysenyl; fluorenyl; pentacenyl; pyridine; quinoline; isoquinoline; pyrazine; quinoxaline; acridine; pyrimidine; quinazoline; pyridazine; cinnoline or phthalazine.

46. The opto-electronic device of claim 1, wherein each R1, R2 and R3 individually represents H, D, F, Cl, methyl, methoxy, ethyl, t-butyl, fluoromethyl, difluoromethyl, trifluoromethyl, fluoromethoxy, difluoromethoxy, trifluoromethoxy, fluoroethyl, polyfluoroethyl, fluorophenyl, trifluorophenyl, trifluoromethoxyphenyl, SF4Cl, or SF5.

47. The opto-electronic device of claim 1, wherein L1 represents cyclohexylene, phenylene, indenylene, naphthylene, fluorenylene, anthracylene, phenanthrylene, pyrylene, chrysenylene, cyclopentylene, or a heteroarylene group derived by replacing one, two, three, or four ring carbon atoms of an arylene group with a corresponding number of heteroatoms.

48. The opto-electronic device of claim 47, wherein the heteroarylene group contains one or more heteroatoms individually selected from: nitrogen, oxygen, sulphur, and silicon.