The present invention relates broadly to a matrix addressing method, matrix addressing circuitry and a liquid crystal display device using the same. The invention relates more particularly to a matrix addressing method and circuitry and a display device using the same conforming to the alternate driving method used in liquid crystal display devices and the like.
The so-called alternate driving method has conventionally been applied to a number of active matrix type liquid crystal display devices. This method is measures against degradation phenomena such that material properties of liquid crystal are changed when the liquid crystal is driven with DC voltage for a long time and its resistance decreases, and is intended to invert the polarity of the driving voltage to apply to the liquid crystal on a frame basis. The more specific basic operation is disclosed in Non-Patent Document 1 and so on.
Basically, flicker occurs when the polarity inversion frequency of the driving voltage is one-half the frame frequency. In the alternate driving method, by averaging the polarity inversion in a screen spatially and temporally, the fundamental component of the optical response ripple is made at the frame frequency or more, thereby preventing an occurrence of flicker (visible flicker). More specifically, any one pixel and its adjacent pixels (or adjacent row of pixels or column of pixels) are made different in driving voltage polarity, and further, their polarities are inverted on a frame basis.
In this conventional technique, a polarity inversion rate of the driving voltage is high, and for this reason, the driving circuitry has a tendency to require large power consumption. In contrast thereto, Patent Document 1 filed by the same applicant as in the present invention is intended to make power savings while keeping a form of alternate driving. The addressing method according to this is a matrix addressing method for alternately driving pixels arranged in matrix, wherein: a plurality of row electrodes extending in a horizontal direction of a display screen are made to be selectively active for each horizontal scanning period of images to be displayed; a plurality of column electrodes extending in a vertical direction of the display screen are applied with respective pixel voltages that are responsive to the image and correspond to the horizontal scanning period while the pixel voltages have polarities alternating for each frame period of the images; and the pixel voltages have polarities alternating in the vertical direction spatially in a display area within the frame period, the method including: successively sequencing on a time series an application timing of the pixel voltages for one row electrode and an application timing of the pixel voltages for the other row electrode, the pixel voltages for the other row electrode being to be in the same polarities as the pixel voltages for the one row electrode; and activating the corresponding row electrode in response to each of the application timings of the pixel voltages for the one and the other row electrodes.
In Patent Document 1, such a method offers achievement of reduction in power consumption in that a polarity inversion rate of pixel voltages on the time axis is made lower while keeping a spatial inversion form of polarities of pixel voltages on a screen at the conventional alternating pattern.
[Non-Patent Document 1] Publication ‘Liquid Crystal Display Technology-Active Matrix LCD-’ MATSUMOTO, Shoichi, Nov. 14, 1997, 2nd Impression, Sangyo Tosho Kabushiki Kaisya, pages 69 to 74
[Patent Document 1 ] Japanese Patent Application Laid-Open No. 2003-114647 (particularly see Claims, FIGS. 2 and 3, and Paragraphs [0031] to [0059])
In the above-mentioned conventional technique, however, when making some gray or black display uniformly over the entire screen for example, it turned out that a problem on displaying occurs that relatively bright and dark horizontal stripes alternately appear repeatedly on the entire screen, another problem on displaying occurs and that the brightness gradually decreases or increases in the vertical direction on the screen for each set of row electrodes driven by one polarity and the adjacent row electrodes driven by the other polarity. Particularly, the latter problem becomes a serious issue in increasing the number of row electrodes to be driven with the same polarity. It should be noted that the aforementioned problems on displaying will be referred to as artefacts, and the former one is referred to as an inter-line artefact, while the latter one will be referred to as an intra-block (block-period-base) artefact. Claims are also defined in the same way.
A principal object of the invention is to provide matrix addressing circuitry and liquid crystal display device conforming to the alternate driving method, which can reduce power consumption while preventing an occurrence of the above-mentioned artefacts.
Another object of the invention is to provide a matrix addressing method and circuitry, and liquid crystal display device using the same, which can contribute to diversification of the alternate driving method capable of reducing power consumption by making good use of electronic circuit techniques such as memory.
In order to achieve the above-mentioned objects, a first aspect of the invention is a matrix addressing method for alternately driving pixels arranged in matrix, wherein: a plurality of row electrodes extending in a horizontal direction of a display screen are made to be selectively active for each horizontal scanning period of images to be displayed; a plurality of column electrodes extending in a vertical direction of the display screen are supplied with respective pixel voltages that are responsive to the image and correspond to the horizontal scanning period while the pixel voltages have polarities alternating for each frame period of the images; the pixel voltages have polarities alternating in the vertical direction spatially in a display area within the frame period; the frame period of the images is formed by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block and a second half block, the first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity; and the corresponding row electrode is made to be active in synchronization with each of the application timings of the pixel voltages for the row electrodes, wherein ones of even-numbered row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block; the others spatially adjoining the ones are selected in the second half block; a row electrode selecting order in the first half block and a row electrode selecting order in the second half block during one frame period are made differed from orders in the corresponding half blocks during the other frame period, respectively, so as to mitigate block-period-base visual artefact.
In this way, brightness variation patterns with respect to an intended value, which are represented by pixels of row electrodes selected in the first and second half blocks, are varied whenever a frame is changed, and it is thereby possible to make the artefact on a block basis difficult to visually identify. Further, it is possible to concurrently achieve maintenance of the alternating pattern for spatial polarity inversion of pixel voltages on the screen and reduction in power consumption due to decreases in polarity inversion rate of the pixel voltages on the time axis.
In this aspect, a row electrode selecting order may be inversed between the first and second half blocks in one frame period and the corresponding half blocks in the other frame period. By doing so, the tendency of increase or decrease in the brightness variation pattern with respect to the intended value, represented by the pixels of the row electrodes selected in the first and second half blocks is changed to the reverse tendency whenever the frame is changed, and line positions of the maximum value and minimum value in the brightness variation pattern are varied whenever the frame is changed. It is thus possible to make the artefact on a block basis more difficult to visually identify.
Further, in at least two frame periods, there may be a block period in which each of row electrode selecting orders in the first and second half blocks is ascending order and a block period which corresponds to said block period and in which each of row electrode selecting orders in the first and second half blocks is descending order. Furthermore, it may be possible that use is made of only block periods in which each of row electrode selecting orders in the first and second half blocks is set to ascending order in one frame period, and use is made of only block periods in which each of row electrode selecting orders in the first and second half blocks is set to descending order in the other frame period. It is thereby possible to reduce the visibility of the artefact with more reliably.
In order to achieve the above-mentioned objects, a second aspect of the invention is a matrix addressing method for alternately driving pixels arranged in matrix, wherein: a plurality of row electrodes extending in a horizontal direction of a display screen are made to be selectively active for each horizontal scanning period of images to be displayed; a plurality of column electrodes extending in a vertical direction of the display screen are supplied with respective pixel voltages that are responsive to the image and correspond to the horizontal scanning period while the pixel voltages have polarities alternating for each frame period of the images; the pixel voltages have polarities alternating in the vertical direction spatially in a display area within the frame period; the frame period of the images is formed by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block and a second half block, the first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity; and the corresponding row electrode is made to be active in synchronization with each of the application timings of the pixel voltages for the row electrodes, wherein ones of even-numbered row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block; the others spatially adjoining the ones are selected in the second half block; row electrode selecting orders in the first and second half blocks are changed between ascending order and descending order for each block period in a frame period, so as to mitigate block-period-base visual artefact.
In this way, taking example for the case where a brightness variation pattern with respect to the intended value, represented by the pixels of row electrodes selected in a block, has a tendency of increase from the minimum brightness to the maximum brightness, the brightness variation pattern in the subsequent block is set in a tendency of decrease from the maximum brightness to the minimum brightness. It is thus possible to moderate a change in brightness on the boundary between blocks in a frame, and to make the artefact for each block less visible.
In this aspect, a frame period may have mixture of block periods in which each of row electrode selecting orders in the first and second half blocks is ascending order and block periods in which each of row electrode selecting orders in the first and second half blocks is descending order. It is thereby possible to exhibit the artefact reduction effect with more reliability.
Further, use is made of ascending-ordered block periods in which each of row electrode selecting orders in the first and second half blocks is ascending order and descending-ordered block periods in which each of row electrode selecting orders in the first and second half blocks is descending order with the ascending-ordered block periods and the descending-ordered block periods being alternated with each other during one frame period, and each of row electrode selecting orders in the first and second half blocks in a block period corresponding to the ascending-ordered block period is descending order and each of row electrode selecting orders in the first and second half blocks in a block period corresponding to the descending-ordered block period is ascending order during the other frame period. By this means, the peak and trough of the brightness variation pattern are reversed whenever a frame is changed, and it is thus possible to further make the artefact unobtrusive.
Each of aforementioned aspects may be set in a mode wherein successive first to fourth frame periods, a row selecting pattern defined in the first frame period is used for one of the third and fourth frame periods and a row selecting pattern defined in the second frame period is used for the other of the third and fourth frame periods, in which the image is formed by repetition of the first to fourth frame periods or by a frame period sequence including the first to fourth frame periods, so that a frequency with which a drive polarity is the one polarity is substantially equal to a frequency with which a drive polarity is the other polarity for each row electrode. In this way, the balance is achieved between one and the other polarities shown in each row electrode, and it is thus possible to prevent each electrode from leaning to either polarity of potential due to successive image display operation.
Further, by making the number of row electrodes selected in each block period different between one frame period and the other frame period, it is possible to change a variation period of the brightness variation pattern whenever the frame is changed, and the artefacts are thus averaged and hard to visually identify.
Furthermore, a specific frame period including an exceptional block period having the number of selected row electrodes different from that in other block periods may be used every two frame periods or every predetermined number of frame periods. By this means, in the specific frame period, the brightness variation pattern is shifted with respect to the other frame period due to existence of the exceptional block period, and it is possible to average the artefacts and to reduce the visibility of the artefacts. In this mode, by using the exceptional block period as a beginning block period in a frame period, it is possible to obtain the intended effects with reliability.
In each of the above-mentioned aspects and modes, row electrodes selected in a preceding half block in the block period in one frame period may be made row electrodes selected in a following half block in the block period in the next frame period. It is thereby possible to also reduce the artefacts of horizontal stripes as described above.
The invention also provides a matrix addressing circuit for alternately driving pixels arranged in matrix, wherein: a plurality of row electrodes extending in a horizontal direction of a display screen are made to be selectively active for each horizontal scanning period of images to be displayed; a plurality of column electrodes extending in a vertical direction of the display screen are supplied with respective pixel voltages that are responsive to the image and correspond to the horizontal scanning period while the pixel voltages have polarities alternating for each frame period of the images; and the pixel voltages have polarities alternating in the vertical direction spatially in a display area within the frame period, the matrix addressing circuit comprising: control means for forming the frame period of the images by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block and a second half block, the first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity; and row driving means for making the corresponding row electrode to be active in synchronization with each of the application timings of the pixel voltages for the row electrodes, wherein ones of even-numbered row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block; the others spatially adjoining the ones are selected in the second half block; a row electrode selecting order in the first half block and a row electrode selecting order in the second half block during one frame period are made differed from orders in the corresponding half blocks during the other frame period, respectively, so as to mitigate block-period-base visual artefact.
The invention further provides a matrix addressing circuit for alternately driving pixels arranged in matrix, wherein: a plurality of row electrodes extending in a horizontal direction of a display screen are made to be selectively active for each horizontal scanning period of images to be displayed; a plurality of column electrodes extending in a vertical direction of the display screen are supplied with respective pixel voltages that are responsive to the image and correspond to the horizontal scanning period while the pixel voltages have polarities alternating for each frame period of the images; the pixel voltages have polarities alternating in the vertical direction spatially in a display area within the frame period, the matrix addressing circuit comprising: control means for forming the frame period of the images by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block and a second half block, the first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity; and row driving means for making the corresponding row electrode to be active in synchronization with each of the application timings of the pixel voltages for the row electrodes, wherein ones of even-numbered and row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block; the others spatially adjoining the ones are selected in the second half block; row electrode selecting orders in the first and second half blocks are changed between ascending order and descending order for each block period in a frame period, so as to mitigate block-period-base visual artefact.
In the above each addressing circuit, the row driving means may comprise a shift-register which is composed of a plurality of unit registers cascaded from a front end unit register to a tail end unit register and in which a significant output of a unit register to the side of the front end unit register is sequentially shifted to a unit register to the side of the tail end unit register for each horizontal scanning period and at the same time the significant output causes the row electrode to be active; and the outputs of the unit registers are connected to the row electrodes, respectively in such a manner that the sequential shifting operation leads to the realization of the row electrode selecting order. In this way, just simply doing the sequentially shifting operation of the shift-register conventionally from its one end side to the other end side can preferably make the row electrodes to be active in the desired order. Such a configuration can offer advantages of preventing complication of an inner structure of the row driving means, and more.
The above-mentioned aspects and implementations of the invention will be described in more detail below by way of embodiment with reference to accompanying drawings.
In this figure, a matrix addressing circuit 10 is configured to drive a display panel 20 of an active matrix type liquid crystal display (LCD) device in which, for example, field-effect thin-film transistors (TFTs) 21 as pixel-driving active elements are arranged in a predetermined display area in correspondence with individual pixels.
In the display panel 20, the TFTs 21 are arranged in the form of a Y rows and X columns matrix. The gate electrode of the TFT 21 is connected to a gate bus line (hereinafter, simply referred to as a gate line) extending in parallel laterally, i.e. in a horizontal direction over the display area for each row. The source electrode of the TFT 21 is connected to a source bus line (hereinafter, simply referred to as a source line) extending in parallel longitudinally, i.e. in a vertical direction over the display area for each column. The drain electrodes of TFTs 21 are connected to pixel electrodes 23 individually.
The display panel 20 is further provided with a common electrode 25 which is opposed to the pixel electrodes 23 and disposed with a clearance. The clearance is filled with a liquid crystal medium not shown. Herein, the common electrode 25 extends across the entire display area. The TFT 21 is switched on selectively for each row by a gate signal as a row electrode signal supplied through the gate line, and set to a driven state according to pixel information to be displayed, by a level of a source signal as a column electrode signal supplied through the source line to each TFT having been switched on. The pixel electrode 23 is given an electric potential corresponding to the driven state by the drain electrode. By an electric field of a strength determined by a difference between the pixel electrode potential and a voltage level given to the common electrode 25, the orientation of the liquid crystal medium is controlled for each pixel electrode. Thus, the liquid crystal medium can to modulate the backlight from a backlight system not shown and the external light from the front side for each pixel in accordance with the pixel information. Details of the basic structure of the liquid crystal display panel are well known in various documents, and so further descriptions thereof are omitted herein.
The addressing circuit 10 comprises a basic configuration having a timing control and voltage producing circuit 30 as a previous stage circuit thereof, a memory 40 for image data storage, a source driver 50 as column driving means, and a gate driver 60 as row driving means.
The timing control and voltage producing circuit 30 receives an image data signal ‘data’ for each of red (R), green (G) and blue (B), a dot clock signal CLK, and a synchronization signal Sync including horizontal and vertical sync signals from signal supplying means not shown, transfers the image data signal to the memory 40, and based on the clock signal CLK and synchronization signal Sync, generates a memory control signal Mc to control the memory 40, a latch signal St to sync-operate the source driver 50, and a control signal Gc to control the gate driver 60. The circuit 30 further generates a voltage signal Vcom to be supplied to the common electrode 25 in the display panel 20. Besides, the circuit 30 generates and supplies a reference voltage and more used in the source driver 50 and gate driver 60, but descriptions thereof are omitted in this embodiment for the sake of simplicity.
The memory 40 receives image data signals of R, G and B from the circuit 30 and sequentially stores the signals for each color for each horizontal scanning period, while performing data processing (time-series operation processing) specific to the invention, described later, on the stored signals based on the memory control signal from the circuit 30. The image data signal ‘data’ having subjected to the data processing is transferred to the source driver 50.
The source driver 50 has a digital-analogue converter for each of image data signals of R, G and B, wherein the image data signal of each color is converted to an analogue signal for each horizontal scanning period, and pixel signals carrying pieces of pixel information to be displayed in one horizontal scanning period (i.e. pixel information for one line) are generated. The pixel signals are held as source signals until a next horizontal scanning period comes, and supplied to the corresponding source lines. It is noted that the latch signal St supplied to the source driver 50 serves as a reference of necessary timings including the horizontal scanning period and more in the display operation such as analogue conversion, voltage supply to the source line.
The gate driver 60 selectively supplies, for example, a predetermined high voltage to the bus line to selectively activate the gate line in the display panel 20 in a mode responsive to the control signal Gc from the circuit 30. The activated gate bus line renders the corresponding TFTs at on-state, and enables concurrent driving of the TFTs for one line by the source signal supplied to the TFTs. By this means, pixels of a row corresponding to the activated gate line are concurrently optically modulated in accordance with the pixel information of that one line. Details will be described later on the control of the gate driver 60 by the control signal Gc from the circuit 30.
While the operation of the addressing circuit 10 will be described below, described first is an example of the operation according to fundamental technique for this embodiment, prior to descriptions of the operation specific to this embodiment.
The memory 40 reads out the thus stored image data signals, while performing the time-series operation processing on the signals, based on the control signal Mc from the circuit 30. The fundamental technique as well as various embodiments of the invention described later are aimed at the so-called inter-row alternate driving as shown in
In the embodiments and fundamental technique according to the invention, instead of selecting each row sequentially from top to bottom in the screen, rows of pixels to be in the same polarity are successively selected on the time series, and the source driver 50 converts the corresponding pixel data into analogue source signals in compliance with the selected row and a polarity given to the row. The voltage generating circuit 30 generates the voltage Vcom applied to the common electrode 25 with a polarity suitable for the given polarity. As can be seen from
By performing such replacement or rearrangement of pixel data on the time series, as a result, the image data sequence ‘data’ are obtained with the line order of the second (+), fourth (+), sixth n (+), first (−), third (−), fifth n (−), . . . from the beginning of the frame period. To perform this operation, the memory 40 is subjected to readout control so that the image data of the lines are rearranged on the time series as described above. Based on the latch signal St, i.e. in this example, a timing signal having a level becoming significant in cycles of the horizontal scanning period, the source driver 50 updates and outputs the pixel data for one line from the memory 40 in response to a change to the significant level.
The source signal Ssig shown in
The gate driver 60 performs scanning operation to activate a gate line corresponding to the line selected as in the above description. In other words, based on the control signal Gc from the timing control circuit 30, the gate driver 60 generates a gate control signal to activate gate lines in line order of the second (+), fourth (+), sixth (+), first (−), third (−), fifth (−), . . . from the beginning of the frame period.
In the next, second frame, in order to achieve a spatial polarity distribution of
According to the aforementioned operation, since the time-series operation processing is performed to make a time-axis succession of processes for pixel information supply and scanning for lines to be in the same polarity, it is possible to increase an inversion period of the source signal Ssig and voltage Vcom to be applied to the common electrode, and therefore, to lower the frequency. It is thereby possible to reduce driving energy or power consumption, while keeping the polarity inversion distributions for driving pixels within the screen as shown in
However, the inventors of the invention found out that problems may occur in quality of a displayed image in the aforementioned fundamental technique, and implemented embodiments described below by adding improvements to the fundamental so as to overcome the problems. The first problem is artefact (inter-line artefact) such that in a remarkable example where uniform gray is displayed on the entire screen, a brightness difference arises between pixels of odd-numbered rows and pixels of even-numbered rows, and relatively bright and dark horizontal stripes alternately appear repeatedly on the entire screen. The second problem is artefact (intra-block artefact) such that in the same example as described above, the brightness gradually decreases or increases in the vertical direction (perpendicularly to lines) in a block on the screen for each block (block of 6H shown in
Either artefact is generally caused generally by fluctuations in intended potential to be applied to the pixel electrode due to some effects, and this is considered to significantly rely on potential fluctuations via especially capacitances and parasitic capacitances formed on the periphery of the pixel electrode. Then, the inventors performed following analysis.
In the display area, a plurality of gate lines extending in the horizontal direction of the display area and a plurality of source lines extending in the vertical direction of the display area are arranged to intersect each other on the plan view. The pixel electrode is provided for each pixel, and the TFT 21 is provided for each pixel electrode to apply the potential corresponding to the pixel information to be displayed, individually to the pixel electrode. The gate line is connected to the gate electrode of the TFT 21, and the source line is connected to the source electrode of the TFT 21. The drain electrode of the TFT 21 is connected to the pixel electrode. The pixel electrodes P1 and P2 shown in the figure are formed in two regions defined by gate lines Gy, Gy+1 and Gy+2 and source lines Sx and Sx+1, or in association with the two regions. Further, in the display area, a storage capacitance Ccs used for display with a principal capacitance (CLC) formed by each pixel electrode is formed for each pixel, and the storage capacitances are connected in common by a bus line (hereinafter, referred to as a Cs line) extending in the horizontal direction of the display area.
In the aforementioned structure, the following capacitances are considered to be primarily formed on the periphery of the pixel electrode.
CLC: capacitance formed between the pixel electrode and the common electrode (the electrode 25 shown in
Cgbnext: capacitance formed between the pixel electrode and a gate line disposed before another gate line to drive the pixel electrode
Ccs: the above-mentioned storage capacitance (capacitance formed between the pixel electrode and the Cs line)
Cs-pixelL: capacitance formed between the pixel electrode and a source line (source line on the left side of the pixel electrode in
Cs-pixelR: capacitance formed between the pixel electrode and an adjacent source line (source line on the right side of the pixel electrode in
CsdTFT: capacitance formed between the source electrode and the drain electrode of the TFT
Cg-pixel: capacitance formed between the pixel electrode and a gate line (gate line on the lower side of the pixel electrode in
CgdTFT: capacitance formed between the gate electrode and the drain electrode of the TFT
Cdd: capacitance formed between the pixel electrode and another (upper or lower) electrode driven by a gate line disposed before or after the gate line to drive the pixel electrode
It is noted in
According to the example as described above, as can be seen from
[View on Potential Fluctuation in Pixel Electrodes]
Q1=CLC(V1−VLC)+Cgbnext(V1−Vgbnext)+Ccs(V1−Vcs)+ . . . +Cdd(V1−Vdd) (1)
When Vdd changes to Vdd′, assuming that the total charge of the pixel electrode P1 at that time is Q1′, and due to such change of Vdd, the potential of the pixel electrode P1 changes to V1′, the following determines Q1′:
Q1′=CLC(V1′−VLC)+Cgbnext(V1′−Vgbnext)+Ccs(V1′−Vcs)+ . . . +Cdd(V1′−Vdd′) (2)
From the charge conservation law, Q1′=Q1 and Q1′−Q1=0. Accordingly, from above two equations, the following equation is derived:
(CLC+Cgbnext+Ccs+ . . . +Cdd)(V1′−V1)+Cdd(Vdd−Vdd′)=0 (3)
Therefore, potential fluctuation V1′−V1 in the pixel electrode P1 when the end potential Vdd of Cdd changes to Vdd′ is as follows:
V1′−V1={Cdd/(CLC+Cgbnext+Ccs+ . . . +Cdd)}×(Vdd′−Vdd) (4)
Herein, assuming Ctotal=CLC+Cgbnext+Ccs+ . . . +Cdd, the voltage loss is Vloss and V1′=V1−Vloss, where V1′−V1 is a fluctuation with respect to a desired voltage V1 in the pixel electrode P1 due to a change from Vdd to Vdd′,
Vloss=−(V1′−V1)=(Cdd/Ctotal)×(Vdd−Vdd′) (5)
Therefore, the voltage loss the pixel electrode P1 suffers based on Vdd−Vdd′ corresponding to the disturbance potential fluctuation is obtained by multiplying Vdd−Vdd′ by a ratio (Cdd/Ctotal) of a value of the capacitance (Cdd) having the disturbance potential fluctuation to a total value (Ctotal) of the capacitances coupled to the pixel electrode P1. Any voltage losses on the pixel electrode about other capacitances which may have disturbance potential fluctuation can be obtained in the same way.
It is noted that since upper and lower two adjacent pixel electrodes actually exist for one pixel electrode, Cdd's of both the adjacent pixel electrodes, i.e. 2Cdd should be taken into account when considering how the one pixel electrode is affected by potential fluctuation under the adjacent pixel electrodes. Accordingly, the above equation (5) is rewritten as follows:
Vloss=−(V1′−V1)=(2Cdd/Ctotal)×(Vdd−Vdd′) (6)
[Consideration of Effects of Cdd]
In the example of the fundamental technique in
Therefore, according to above equation (6), the voltage loss Vloss_Cdd_F incurred in the pixel electrode of the first written line is:
Meanwhile, the latter written lines (the first, third, fifth lines, etc.) hold their intended states with which the latter written lines have been written until the first written lines (the second, fourth and sixth lines, etc.) are newly written in the next frame, i.e. for almost one frame. The latter written lines undergo effects of potential fluctuations at an end of Cdd due to writing of the first written lines when the first written lines adjacent in the block are written in the first half of the block in the next frame, but new pixel information is immediately written in the latter written lines in the latter half of the block, and therefore, such effects are negligible.
Accordingly, the voltage loss Vloss_Cdd_L incurred in the pixel electrode of the latter written line is as follows:
Vloss_Cdd_L=0 (8)
[Consideration of Effects of CsbpixelL/R and CsdTFT]
As shown in
Considered first is the effect of potential fluctuations of the source line on the pixel electrode of the first written line. The first written line is an even-numbered line in this example. Referring to
Such calculation is to obtain the number of inverse polarity driving times on a half-block basis during a period Qf from immediately after the half block of the first frame to immediately before the same half block of the second frame as shown in
Thereafter, as shown in
Accordingly, as shown in
According to the aforementioned consideration, the voltage loss Vloss_Csb_F incurred in the pixel electrodes of the first written line is as follows:
In addition, Csbpixel=Cs-pixelL+Cs-pixelR+CsdTFT holds, and the reason why 1/N is multiplied in the equation is that the number of inverse polarity driving times are handled as a probability of being put under a condition of inverse polarity driving.
Considered next is the effect of potential fluctuations of the source line on the pixel electrode of the latter written line. The latter written line is an odd-numbered line in this example. Referring to
Then, in the same way as described above, considered to obtain the accurate number of times is differences in the number of inverse polarity driving times among three lines during an update period of the half block in the second frame. With respect to the differences, L is similarly used to represent the turn of a line to be selected in the half block.
According to the aforementioned consideration, the voltage loss Vloss_Csb_L incurred in the pixel electrode of the latter written line is estimated as follows:
[Consideration of Effects of Cgb-pixel, CgdTFT and Cgbnext]
The potential of the gate line basically varies between a level to turn the TFT off and another level to turn the TFT on. As is suggested from
This number of times is the same as the number of inverse polarity driving times described above, and considering other respects in the same way, voltage losses Vloss_Csb_F and Vloss_Csb_L incurred in pixel electrodes of the first and latter written lines by potential fluctuations of the gate line are respectively:
where, Vc multiplied in each equation is a result of Vc/2−(−Vc/2).
From the considerations described above, voltages Vactual_F and Vactual_L respectively to which eventually the pixel electrodes of the first written line and the pixel electrode of the latter written line converge after fluctuating from the desired voltage Vc are as follows:
[Causes of Artefacts]
1. Inter-line Artefact
Aforementioned equations (13) and (14) respectively represent actual voltages of pixel electrodes of the first written line and latter written line, and when their values have a difference therebetween, the difference shows a difference in brightness between lines, i.e. inter-line artefact. When the difference is Vloss(LbyL), the following equation holds:
As can be seen from the above-described equations (7) and (8), the potential fluctuation of the pixel electrode of the first written line is larger than the potential fluctuation of the pixel electrode of the latter written line. Accordingly, even in an attempt to display in the same brightness level, a difference arises in displayed brightness level between pixels of the first written line and pixels of the latter written line, and in the case of displaying gray on the whole of the screen, the pixels of the first written line would be brighter than the pixels of the latter write line. Such a fact that the potential fluctuation of the pixel electrodes of the first written line is relatively large is understood also from relationship between equations (9) and (10) and relationship between equations (11) and (12). This is because a value of the factor Int. (N/2−M) in equations (10) and (12) is obviously smaller than a value of the corresponding factor in equations (9) and (11), and values obtained by equations (10) and (12) are smaller than values obtained by equations (9) and (11), respectively.
Thus, in the alternate driving according to the fundamental technique, such a pattern appears that a brightness difference arises for each line even in an attempt to display in the same brightness level on the entire area of the screen. The characteristics depicted by a solid line in
2. Intra-block Artefact
The intra-block artefact is caused by a factor for generating brightness variations in a displayed image of lines corresponding to a block and generating such brightness variations for each block. This factor is recognized to be (L−1) in the above equations (13) and (14). In other words, L represents the turn of a line selected in a block, and as a number of L increases (i.e. as a line is written later), the voltage deviates more from the desired voltage Vd in both the equations.
More specifically, a component representing a brightness variation amount in a block corresponds to a voltage fluctuation corresponding to a factor relating to (L−1) in equations (13) and (14), and is assumed as Vloss(Block). Vloss(Block) is as follows:
Thus, in the alternate driving according to the fundamental technique (
The technique to resolve the inter-line artefact is described in Japanese Patent Application Laid-Open No. 2001-108964 per se. In this conventional technique, source lines are beforehand supplied with, for example, bias voltages corresponding to the pattern of high-low alternating levels as shown in
It is noted that the inter-line artefact and intra-block artefact are combined and the combination artefact appears, and the invention intends cancellation of the combined artefact, as well as each artefact. Embodiments 1-3 provide measures against the inter-line artefact without relying on the technique described in Japanese Patent Application Laid-Open No. 2001-108964, and Embodiments 4-9 provide measures against the intra-block artefact using features of Embodiments 1-3. Embodiments 4-9 concurrently provide measures against the inter-line artefact of Embodiments 1-3, but such measures may be replaced by anti-inter-line artefact measures as described in Japanese Patent Application Laid-Open No. 2001-108964. Further, techniques specific to Embodiments 4-9 themselves can be implemented irrespective of the presence or absence of anti-inter-line artefact measures. The embodiments according to the invention implemented based on the aforementioned considerations will specifically be described below.
An embodiment of measures against the inter-line artefact will be described with reference to
By this means, the first written lines causing relatively large voltage losses in the first frame are handled as latter written lines with relatively small voltage losses in the second frame, so that such a relationship is provided between the first frame and the second frame that a brightness difference caused by a difference in voltage loss of each line is canceled, and it is thus possible to reduce visual failures caused by the difference in total voltage loss. For latter written lines in the first frame, there is inverse relationship, visual failures caused by the difference in voltage loss are similarly cancelled.
Thus, in displaying gray, the first frame has generally an image of the brightness pattern as shown in
This embodiment is to improve Embodiment 1. In Embodiment 1, first written lines and latter written lines are exchanged whenever the frame is switched. However, it has been proved that the effect of reducing the voltage loss is insufficient in some part from the review of contents shown in
Focusing attention on the sixth and seventh lines in the second frame, the sixth line is driven as a latter written line, and the seventh line is subsequently driven as a first written line. At this point, since the sixth line adjoins to the seventh line, the sixth line is affected at the time the seventh line is written. In other words, since the pixel electrodes of the seventh line are coupled with the pixel electrodes of the sixth line via Cdd, the desired voltages applied to the pixel electrodes of the sixth line are varied by the writing of the seventh line. The reason why the sixth line is handled as a latter written line is that handling the sixth line as a first written line in the first frame causes a large voltage loss, and so the sixth line should be handled as a latter written line with a small voltage loss in the second frame. Nevertheless, the sixth line suffers a large voltage loss also in the second frame due to the writing of the adjacent seventh line. Accordingly, the pixel electrodes of the sixth line causes a large voltage loss in either frames, and there is a risk that pixels corresponding to the sixth line locally make display extremely different brightness. The same respect applies to the 12th and 13th lines, the 18th and 19th lines, the 24th and 25th lines and the 30th and 31st lines.
This embodiment is to take measures against such a respect, and
In this way, all the lines handled as first written lines in the first frame are handled as latter written lines under conditions or circumstances with relatively small voltage loss, and therefore, it is possible to solve the problem that the voltage loss is locally doubled as described above.
As means for solving the same problem, the example in
Alternatively, a time interval for one line is simply provided between selection timing of the fifth line and selection timing of the second line, whereby the operation equivalent to that using the auxiliary line is provided.
This embodiment is to further improve Embodiments 1 and 2, and such an improvement will be first described with reference to
Except for the hatched fields or states in which polarity inversion occurs, the number of line periods (H) with the positive polarity and the number of line periods (H) with the negative polarity in the first and second frames are checked for each line, and the resultant values are obtained at the right end of
It is understood from the values shown at the right side of
In this embodiment, third and fourth frames are added to the driving manner to resolve such a problem, and
(Other Forms)
In this form, for example, the sixth line has a specific derivation value Δ=12 in the first and second frames, while having a value Δ=−12 in the third and fourth frames. Therefore, all sums are also just zero when the values of Δ in
It is noted that it is apparent, in the same import, to be able to make a constitution having the third and fourth frames based on the example shown in
Thus, by providing additional frames with deviations to cancel deviations in driving polarity in the first and second frames for each line, it is possible to implement driving without voltage offset and to avoid the problems as described above.
One of embodiments for anti-intra-block artefact measures is to perform driving to provide a brightness variation as shown in
More specifically, as shown in
Although in this embodiment the line selecting order in a block is either the ascending order or descending order, it may be possible that a preceding half block in a block is provided with one of the ascending order and descending order, while the following half block is provided with the other one.
It is noted that also in this embodiment, it is possible to add suitable third and fourth frames or any necessary additional frame(s) to take measures against the voltage offset as described previously, and such a case leads to a more effective form. This respect likewise applies to embodiments described below.
Another embodiment of anti-intra-block artefact measures is to perform driving to provide brightness variations as shown in
A further embodiment of anti-intra-block artefact measures is to perform driving to provide brightness variations as shown in
Still another embodiment is to perform driving to provide brightness variations as shown in
Furthermore, an embodiment may be possible to perform driving to provide brightness variations as shown in
Furthermore, an embodiment may be possible to perform driving to provide brightness variations as shown in
To clarify the relationship in inclination of the brightness variation pattern between the first and second frames that is less clarified in the example of
It should be noted that the aforementioned embodiments and modifications are capable of being further changed and/or modified. For example, the alternate driving pattern shown in
Besides, when implementing the above embodiments, a connection manner between the gate driver 60 as row driving means and the liquid crystal display panel 20 are preferably designed as follows.
In the shift-register 61, a significant output (e.g. a high voltage output) of a unit register to the side of the front end unit register 611 is sequentially shifted to a unit register to the side of the tail end unit register 6132 for each horizontal scanning period while the significant output causes the row electrode of the display panel 20 to be active.
By means of a switching section 62, the outputs of the unit registers are connected to the row electrodes of the display panel 20, respectively in such a manner that the sequential shifting operation leads to the realization of the row electrode selecting order as in the above-mentioned embodiments. In the embodiment of
By so doing, it is possible to make the gate lines to be active in the desired order according to the above embodiments only by doing the sequentially shifting operation of the shift-register conventionally from its one end side to the other end side. This can prevent necessary complication of an inner structure of the gate driver 60 to mitigate the artifact.
It is noted that the switching section 62 can be implemented by a well-known analog switch array. Alternatively, when the row selecting pattern is not switched for each frame, the switching section 62 is not necessary, and it suffices to connect the outputs of the shift-register 61 directly to the row electrodes with wirings adapted to the desired selecting order.
In addition, although the above example is intended to provide the switching section 62 to switch a connection manner of the outputs of the shift-register 61 and the gate lines between the first and second frames, there may instead be adopted such a configuration that a shift-register for the first frame and another shift-register for the second frame are provided, and each of the shift-registers is fixedly connected to the gate lines in the corresponding manner, wherein any one of the shift-registers is acted but the other one is out of action during a frame associated with the one.
Moreover, in each of the above-mentioned embodiments the matrix addressing circuit used in the liquid crystal display device has been described, but the invention is not limited thereto, and applicable as appropriate to any display devices as far as they use the matrix addressing circuit as described herein.
Representative embodiments according to the invention have been described above, but the invention is not limited to them, and various modifications can be found by those skilled in the art within the scope of the appended claims.
Number | Date | Country | Kind |
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2004-236138 | Aug 2004 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/IB2005/052665 | 8/11/2005 | WO | 00 | 2/8/2007 |
Publishing Document | Publishing Date | Country | Kind |
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WO2006/018800 | 2/23/2006 | WO | A |
Number | Name | Date | Kind |
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6496172 | Hirakata | Dec 2002 | B1 |
6717563 | Kim | Apr 2004 | B2 |
6724362 | Min | Apr 2004 | B2 |
Number | Date | Country |
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10-59332 | Mar 1989 | JP |
2000-250496 | Sep 2000 | JP |
2002-244623 | Aug 2002 | JP |
2004-004857 | Jan 2004 | JP |
WO 03030137 | Apr 2003 | WO |
WO 03030137 | Apr 2003 | WO |
Number | Date | Country | |
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20070247478 A1 | Oct 2007 | US |