Claims
- 1. A matrix-connected driver in combination with and for controlling multiple multi-phase motors, comprising:a logic circuit separately engaged to control a set of buffers; each buffer being separately controllable to either source a power source to a connecting line or to sink said connecting line to ground; said buffer connecting lines being divided into rows and columns electrically connected to phases of multi-phase motors; a first of said buffers being electrically engaged to a first row; a second of said buffers being electrically engaged to a second row; a third of said buffers being electrically engaged to a first column; a fourth of said buffers being electrically engaged to a second column; at least two multi-phase motors, a first motor and a second motor, each having at least two phases, an A phase and a B phase; said A phase of said first motor being engaged between said first row and said first column; said B phase of said first motor being engaged between said second row and said first column; said A phase of said second motor being engaged between said first row and said second column; said B phase of said second motor being engaged between said second row and said second column; and said logic circuit programmed to sequentially operate pairs of buffers, either one of said first or second buffers and one of said third or fourth buffers to either source or sink said columns and rows to individually power phases of a selected of one of said motors to cause said selected motor to rotate.
- 2. The matrix-connected driver motor combination of claim 1, wherein:said buffers being electronic transistors.
- 3. The matrix-connected driver motor combination of claim 1, wherein:said buffers being amplifier circuits.
- 4. The matrix-connected driver motor combination of claim 1, wherein:said logic circuit being a micro-controller.
- 5. A matrix-connected driver in combination with and for controlling multiple multi-phase motors, comprising:a logic circuit separately engaged to control a set of buffers; each buffer being separately controllable to either source a power source to a connecting line or to sink said connecting line to ground; said buffer connecting lines being divided into rows and columns electrically connected to phases of multi-phase motors; wherein each row being electrically engaged to more than one phase of different motors; wherein each column being electrically engaged to more than one phase of a different motor; multiple multi-phase motors, each having multiple phases with each phase being connected to one row and one column, and each phase having a unique combination of row and column and associated unique operating buffer pairs; and said logic circuit programmed to operate individual motors by sequentially operating individual phases through controlling unique combinations of pairs of buffers to operate individual motors in a single phase ON mode.
- 6. The matrix-connected driver motor combination of claim 5, wherein:said buffers being electronic transistors.
- 7. The matrix-connected driver motor combination of claim 5, wherein:said buffers being amplifier circuits.
- 8. The matrix-connected driver motor combination of claim 5, wherein:said logic circuit being a micro-controller.
- 9. A matrix-connected driver for controlling multiple multi-phase motors, there being at least two multi-phase motors, a first motor and a second motor, each having at least two phases, an A phase and a B phase, comprising:a logic circuit separately engaged to control a set of buffers; each buffer being separately controllable to either source a power source to a connecting line or to sink said connecting line to ground; said buffer connecting lines being divided into rows and columns electrically connected to phases of multi-phase motors; a first of said buffers being electrically engaged to a first row; a second of said buffers being electrically engaged to a second row; a third of said buffers being electrically engaged to a first column; a fourth of said buffers being electrically engaged to a second column; a first connector within said first row and a second connector within said first column, said first and second connectors for engagement to the A phase of the first motor; a third connector within said second row and a fourth connector within said first column, said third and fourth connectors for engagement to the B phase of the first motor; a fifth connector within said first row and a sixth connector within said second column, said fifth and sixth columns for engagement to the A phase of the second motor; a seventh connector within said second row and an eighth connector within said second column, said seventh and eighth connector for engagement to the B phase of the second motor; and said logic circuit programmed to sequentially operate pairs of buffers, either one of said first or second buffers and one of said third or fourth buffers to either source or sink said columns and rows to sequentially and individually power phases of a selected of one of the motors to cause the selected motor to rotate.
- 10. The matrix-connected driver of claim 9, wherein:said buffers being electronic transistors.
- 11. The matrix-connected driver of claim 9, wherein:said buffers being amplifier circuits.
- 12. The matrix-connected driver of claim 9, wherein:said logic circuit being a micro-controller.
- 13. A matrix-connected driver for controlling multiple multi-phase motors in combination with an isolated system with remote multi-purpose motors, comprising:an isolated system enclosed by a barrier; a logic circuit separately engaged to control a set of buffers; said logic circuit and said buffers external to said barrier; each buffer being separately controllable to either source a power source to a connecting line or to sink said connecting line to ground; said buffer connecting lines being divided into rows and columns electrically connected to phases of multi-phase motors; wherein each row being electrically engaged to more than one phase of different motors; wherein each column being electrically engaged to more than one phase of a different motor; wherein said motors being within said barrier and said connecting lines electrically passing through a connector within said barrier; multiple multi-phase motors, each having multiple phases with each phase being connected to one row and one column, and each phase having a unique combination of row and column and associated unique operating buffer pairs; and said logic circuit programmed to operate individual motors by sequentially operating individual phases through controlling unique combinations of pairs of buffers to operate individual motors in a single phase ON mode.
- 14. The matrix-connected driver isolated system combination of claim 13, wherein:said buffers being electronic transistors.
- 15. The matrix-connected driver isolated system combination of claim 13, wherein:said buffers being amplifier circuits.
- 16. The matrix-connected driver isolated system combination of claim 13, wherein:said logic circuit being a micro-controller.
- 17. The matrix-connected driver isolated system combination of claim 13, wherein:said barrier being for containing extreme temperatures.
- 18. The matrix-connected driver isolated system combination of claim 13, wherein:said barrier being for containing radiation.
- 19. The matrix-connected driver isolated system combination of claim 13, wherein:said barrier being for containing near vacuum.
- 20. A matrix-connected driver in combination with and for controlling multiple multi-phase motors, comprising:a logic circuit separately engaged to control a set of buffers; each buffer being separately controllable to either source a power source to a connecting line or to sink said connecting line to ground; said buffer connecting lines being divided into rows and columns electrically connected to phases of multi-phase motors; a first of said buffers being electrically engaged to a first row; a second of said buffers being electrically engaged to a second row; a third of said buffers being electrically engaged to a first column; a fourth of said buffers being electrically engaged to a second column; a fifth of said buffers being electrically engaged to a third row; a sixth of said buffers being electrically engaged to a fourth row; a seventh of said buffers being electrically engaged to a third column; an eighth of said buffers being electrically engaged to a fourth column; at least four multi-phase motors, a first motor, a second motor, a third motor, and a fourth motor, each having at least two phases, an A phase and a B phase; said A phase of said first motor being engaged between said first row and said first column; said B phase of said first motor being engaged between said third row and said third column; said A phase of said second motor being engaged between said second row and said first column; said B phase of said second motor being engaged between said fourth row and third column; said A phase of said third motor being engaged between said first row and said second column; said B phase of said third motor being engaged between said third row and said fourth column; said A phase of said fourth motor being engaged between said second row and said second column; said B phase of said fourth motor being engaged between said fourth row and fourth column; said logic circuit programmed to sequentially operate two pairs of buffers, either one of said first or second buffers and one of said third or fourth buffers for a first buffer pair, and one of said fifth or sixth buffers and one of said seventh or eighth buffers for a second buffer pair, to either source or sink said columns and rows to individually power two phases of a selected of one of said motors to cause said selected motor to rotate.
- 21. The matrix-connected driver motor combination of claim 20, wherein:said buffers being electronic transistors.
- 22. The matrix-connected driver motor combination of claim 20, wherein:said buffers being amplifier circuits.
- 23. The matrix-connected driver motor combination of claim 20, wherein:said logic circuit being a micro-controller.
Parent Case Info
This is a non-provisional patent application claiming the priority of provisional patent application Serial No. 60/338,580, filed Nov. 5, 2001.
US Referenced Citations (7)
Provisional Applications (1)
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Number |
Date |
Country |
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60/338580 |
Nov 2001 |
US |