Matrix display device and process for controlling said device

Abstract

A matrix display device applicable to liquid crystal displays comprises a display material having an optical property inserted between two insulating walls. On the inner face of one of the walls (1) are arranged n row conductors, m column conductors, p resistive conductors and p.k electrodes grouped into p=m.(n-1) packets of k electrodes each, the electrodes E.sub.1 . . . E.sub.k of one packet P.sub.ii'j being connected by switches I.sub.1 . . . I.sub.k to a column conductor C.sub.j and to a resistive conductor R.sub.ii'j, itself connected between two row conductors L.sub.i and L.sub.i', with i, i' and j being integers such that i.noteq.i', l.ltoreq.i<n, l<i.ltoreq.n and l.ltoreq.i.ltoreq.m. On the inner face of the other wall is placed a counterelectrode. A process for controlling the display device is also disclosed. The invention more particularly applies to liquid crystal display devices.

Description

The present invention relates to a matrix display device and to a process for controlling said device.

BACKGROUND OF THE INVENTION

The invention is used in optoelectronics and mainly in liquid crystal display devices, particularly used as converters of electrical information into optical information, in the real time processing of optical images and in analog displays.

More specifically, the invention relates to an active matrix display device incorporating a display material having an optical property. The optical property of the display material is e.g. opacity, a refractive index, transparency, absorption, diffusion, diffraction, convergence, etc. Moreover, said material can be an amorphous or crystalline, liquid or solid body.

FIGS. 1a and 1b respectively diagrammatically show a perspective of an embodiment of a known active matrix display device and the inner face of one of the walls of said device.

FIG. 1a shows a first and a second insulating walls 1,3 facing one another and which are kept spaced and sealed by a joint 5. Between said walls is placed a display material layer 7 having an optical property, said material e.g. being a liquid crystal film.

Over the inner face of one of the walls 1 (FIGS. 1a and 1b) are distributed n parallel row conductors, designated L.sub.i and m parallel column conductors designated C.sub.j, which intersect the row conductors, i and j being integers such that 1.ltoreq.i.ltoreq.n and 1.ltoreq.j.ltoreq.m, said row and column conductors carrying electric signals appropriate for exciting the display material 7 and generated by not shown addressing means.

At the intersection of each row conductor L.sub.i and each column conductor C.sub.j is provided a switch I.sub.ij, such as a field effect transistor connected by its gate to the row conductor L.sub.i and arbitrarily by its source and drain to the column conductor C.sub.j and to an electrode E.sub.ij.

Moreover, the inner face of the other wall 3 is covered by a conductive material serving as a counterelectrode 13, which is raised to a reference potential.

An image point A.sub.ij is defined by a capacitor formed by electrode E.sub.ij and counterelectrode 13, the material 7 inserted between these two electrodes forming the dielectric of the capacitor.

In order to select an image point A.sub.ij, onto the row conductor L.sub.i is passed an electric signal, which selects the on state of the group of transistors connected to said row conductor and in particular the on state of transistor I.sub.ij associated with said image point. This transistor then transmits to the electrode E.sub.ij to which it is connected, the electric signal coming from the column conductor C.sub.j. Between electrode E.sub.ij and counterelectrode 13 appears an electric field, which will bring about the excitation and collective orientation of the molecules of the display material placed between electrode E.sub.ij and counterelectrode 13, when the signal from column C.sub.j is equal to or greater than a threshold potential V.sub.S corresponding to the minimum value necessary for exciting material 7. This collective orientation will modify the optical property of the material at image point A.sub.ij.

By using the punctiform excitation of the liquid crystal, an image appears on the complete display device whilst defining it point by point.

Other types of active matrix display devices are known. Thus, e.g. FR-A-No. 2 553 218 describes an active matrix display device having on the inner face of one of its walls, a matrix of electrodes connected by switches to row conductors and on the inner face of the other wall, column electrodes facing the matrix of electrodes and connected to column conductors, the switches also being connected to a reference potential.

The number of image points of the known display devices is equal to the number of row conductors multiplied by the number of column conductors, or in other words n.m. Moreover, any increase in the number of image points in a known display device leads to an increase in the number of row and/or column conductors and therefore to an increase in the constructional complexity of the display device and to an increase in its inactive surface. The inactive surface corresponds to a surface not occupied by the matrix of electrodes of the device, each electrode of said matrix corresponding to an image point.

SUMMARY OF THE INVENTION

The invention therefore aims at obviating these disadvantages and in particular at providing an active matrix display device with a number of image points exceeding the product of the number of row conductors and the number of column conductors. The invention particularly applies to all active matrix display devices and especially to those described hereinbefore.

More specifically, the present invention relates to a matrix display device having a display material with an optical property inserted between a first and a second insulating wall, characterized in that it comprises a matrix of p.k elements, each constituted by a switch and an image point defined by a capacitor formed from two electrodes arranged on two walls, n row conductors, m column conductors and p resistive conductors, each resistive conductor R.sub.ii'j being connected between two row conductors L.sub.i, L.sub.i' with p, k, n, m, i, i', and j integers such that i.noteq.i', 1.ltoreq.i&lt;n, 1&lt;i.ltoreq.n, 1.ltoreq.j.ltoreq.m and p=m. (n-1), the p.k elements being grouped into p packets of k elements each, the elements of each packet being connected to a column conductor and to a resistive conductor, signals appropriate for the excitation of the display material being applied to the row conductors and to the column conductors.

The display device according to the invention makes it possible to have k.p=k.m. (n-1) image points with n row conductors and m column conductors instead of m.n image points with the known display device.

According to an embodiment of the display device according to the invention, on the inner face of the first wall are arranged n row conductors, m column conductors, p resistive conductors and p.k electrodes grouped into p packets of k electrodes each, with p, k, m and n being integers and p=m(n-1), the electrodes E.sub.1 . . . E.sub.k of a packet P.sub.ii'j being respectively connected by switches I.sub.1 . . . I.sub.k to a column conductor C.sub.j and to a resistive conductor R.sub.ii'j, itself connected between two row conductors L.sub.i and L.sub.i', with i, i' and j such that i.noteq.i', 1.ltoreq.i&lt;n, 1.ltoreq.i.ltoreq.n and 1.ltoreq.j.ltoreq.m and on the inner face of the second wall is disposed a counterelectrode formed from a continuous layer of a conductive material raised to a reference potential.

In this device, an image point is defined by a capacitor formed by an electrode and the facing part of the counterelectrode.

Moreover, the row conductors and column conductors e.g. intersect on the inner face of one of the walls of the device and the resistive conductors connected to the row conductors are parallel to the column conductors. However, it is obvious that any other arrangement of the row conductors, column conductors and resistive conductors on one of the walls of the device can be envisaged.

Each packet P.sub.ii'j of electrodes relative to a packet of elements is e.g. inserted between the row conductor L.sub.i and the row conductor L.sub.i', to the left or right of the column conductor C.sub.j and the resistive conductor R.sub.ii'j, i' is advantageously equal to i+1++1.ltoreq.i&lt;n, 1&lt;i'.ltoreq.n+.

According to a preferred embodiment of the display device, the display material is a liquid crystal film, the exciting signals being voltages.

Advantageously, the switches are field effect transistors, each transistor I.sub.l associated with an electrode E.sub.l of a packet P.sub.ii'j being connected by its gate to the corresponding resistive conductor R.sub.ii'j, by a second terminal to the corresponding column conductor C.sub.j and by a third terminal to said electrode E.sub.l with L being an integer such that 1.ltoreq.l.ltoreq.k. The second and third terminals of a transistor are arbitrarily the source and drain of the transistor.

According to another preferred embodiment of the invention, the resistive conductors comprise resistors in series. The resistive value of each resistive conductor R.sub.ii'j is preferably identical.

Moreover, the resistive value of a resistive conductor R.sub.ii'j connected by k switches I.sub.1 . . . I.sub.k to the image points A.sub.ii'j1 . . . A.sub.ii'jk of a packet of elements, between the row conductor L.sub.i and switch I.sub.1, between the row conductor L.sub.i, and switch I.sub.k and between the different switches I.sub.1 and I.sub.2, I.sub.2 and I.sub.3 . . . I.sub.k-1 and I.sub.k to which it is connected is identical.

The invention also relates to a process for controlling a display device, which is characterized in that for controlling the optical property of the display material at image points A.sub.ii'j1 . . . A.sub.ii'jk, corresponding to a packet of elements, with i, i', j and k being integers such that i.noteq.i, 1.ltoreq.i&lt;n, 1&lt;i.ltoreq.n and 1.ltoreq.j.ltoreq.m, during a time T.sub.s =T/(n-1) divided into k time fractions t.sub.l are applied to the row conductors L.sub.i and L.sub.i', respectively exciting signals V.sub.i and V.sub.i', so that for each time fraction t.sub.l at least one of the switches I.sub.1 . . . I.sub.k associated with said points is closed, so that each of said switches is closed over at least one time fraction t.sub.l, with L being an integer such that 1&lt;l&lt;k, said switches being connected to the resistive conductors R.sub.ii'j and to the other row conductors, exciting signals bringing about the opening of the switches associated with said other row conductors, T being the addressing period of an image point.

The exciting signals supplied on the column conductors are dependent on the desired display.

In order to obtain an excited state, or in other words a displayed state at image point A.sub.ii'jl, to the corresponding column conductor C.sub.j is supplied an exciting signal of value equal to or greater than the threshold potential V.sub.S, at least during the final time fraction t.sub.l during which the corresponding switch I.sub.l is closed, said time t.sub.l corresponding to a fraction of the addressing time T.sub.s of the packet of image points A.sub.ii'j1 . . . A.sub.ii'jk.

As a function of the value of said exciting signal during said time fraction t.sub.l, different grey levels can be displayed at image point A.sub.ii'jl, obviously provided that said value is equal to or exceeds the threshold potential V.sub.S.

Conversely, to obtain a non-excited state, or in other words a non-displayed state at image point A.sub.ii'jl, to the column conductor C.sub.j is supplied an exciting signal having a value below the threshold potential V.sub.S at least during said final time fraction t.sub.l during which the corresponding switch I.sub.l is closed.

The different states assumed by the image point A.sub.ii'jl during the different time fractions of the corresponding time T.sub.s prior to the final time fraction t.sub.l and during which the switch I.sub.l of said image point is closed, cannot be seen by an observer as a result of their short duration. Only the state assumed by the image point during said time t.sub.l and retained for the remainder of time T can be seen by an observer.

According to an embodiment of the control process, to the row conductors L.sub.i and L.sub.i' are respectively applied exciting signals V.sub.i and V.sub.i', so that at each time fraction t.sub.l of the addressing time T.sub.s of image points A.sub.ii'j1 . . . A.sub.ii'jk, with l being an integer such that 1.ltoreq.l.ltoreq.k, one of the switches associated with said image points and closed during time t.sub.l-1 is opened, the other switches retaining their state, all the switches associated with said image points being closed at time t.sub.1.

Numerous exciting signals of this type can be applied to the row conductors.

Thus, advantageously, to the row conductors L.sub.i and L.sub.i' are respectively applied exciting signals V.sub.i and V.sub.i', so that at each time fraction t.sub.l of the addressing time T.sub.s of the image points A.sub.ii'j1 . . . A.sub.ii'jk, the switches I.sub.1 . . . I.sub.u associated with said image points are closed, with u being an integer such that u=k-(l-1) and the other switches associated with said image points are opened.

According to a variant, to the row conductors L.sub.i and L.sub.i' are respectively applied exciting signals V.sub.i and V.sub.i', so that at each time fraction t.sub.l of the addressing time T.sub.s of the image points A.sub.ii'j1 . . . A.sub.ii'jk, the switches I.sub.l . . . I.sub.k associated with said image points are closed and the other switches associated with said image points are opened.

In the particular case where k=3, as in the case of the three-colour method, another embodiment of this process can be used. This consists of applying to the row conductor L.sub.i and L.sub.i', respectively exciting signals V.sub.i and V.sub.i', so that at time t.sub.1, switches I.sub.1, I.sub.2 and I.sub.3 are closed, at time t.sub.2 switch I.sub.1 is closed and switches I.sub.2 and I.sub.3 are opened and at time t.sub.3 switch I.sub.3 is closed and switches I.sub.1, I.sub.2 are opened, times t.sub.1, t.sub.2 and t.sub.3 being three time fractions of the addressing time T.sub.s of the image points A.sub.ii'j1, A.sub.ii'j2, A.sub.ii'j3.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the invention can be gathered from the following non-limitative description with reference to the attached drawings, wherein show:

FIGS. 1a and 1b, already described, show diagrammatically and respectively a known display device in perspective and the inner face of the wall of said device on which is arranged a matrix of electrodes;

FIG. 2 show diagrammatically the inner face of the wall of an embodiment of the display device according to the invention on which is arranged a matrix of electrodes;

FIG. 3 is timing diagram of an example of signals applied to the row conductors L.sub.i and L.sub.i' and to the column conductor C.sub.j for exciting the display material placed between the counterelectrode and one or more electrodes of the corresponding packet or group P.sub.ii'j ;

FIG. 4 is a timing diagram of another example of signals applied to the row conductors L.sub.i and L.sub.i' and to the column conductor C.sub.j for exciting the display material placed between the counterelectrode and one or more electrodes of the corresponding packet P.sub.ii'j ;

FIG. 5 is a timing diagram of another example of signals applied to the row conductors L.sub.i and L.sub.i' and to the column conductor C.sub.j in the particular case where k=3, and

FIG. 6 is a timing diagram of an example of signals applied to the row conductors L.sub.i and L.sub.i' and to the column conductor C.sub.j in the case where k=3 making it possible to display different grey levels.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The display device according to the invention comprises two facing insulating walls between which is placed a display material.

According to an embodiment, on the inner face of one of the walls 3 is disposed, as in the display device described relative to FIG. 1a, a counterelectrode formed by a continuous layer of a conductive material raised to a reference potential.

On the inner face of the other wall 1 (FIG. 2) are arranged n parallel row conductors, designated L.sub.i, m parallel column conductors, designated C.sub.j intersecting with the row conductors and p=(n-1).m resistive conductors, designated R.sub.ii'j, which are parallel to the column conductors and respectively connected between two row conductors L.sub.i and L.sub.i', with i, i' and j being integers such that i.noteq.i', ++1.ltoreq.i&lt;n, 1&lt;i'.ltoreq.n and 1.ltoreq.j.ltoreq.m; whereby i' is here equal to i+1.

Moreover, on the inner face of the wall are arranged p.k electrodes grouped into p packets, designated P.sub.ii'j of k electrodes each, designated E.sub.l, with l being an integer such that 1.ltoreq.l.ltoreq.k. Each packet P.sub.ii'j of electrodes is inserted between two row conductors L.sub.i, L.sub.i', e.g. to the left of the column conductor C.sub.j and the resistive conductor R.sub.ii'j.

The electrodes of a packet of electrodes can be parallel to one another, as shown in FIG. 2, or can be differently arranged, e.g. in staggered manner.

Each electrode E.sub.l of a packet P.sub.ii'j is connected to the resistive conductor R.sub.ii'j and to the column conductor C.sub.j by means of a switch I.sub.l, said resistive conductor also being connected between two row conductors L.sub.i and L.sub.i'.

In this device, an image point A.sub.ii'jl is defined by the capacitor formed by the electrode E.sub.l of packet P.sub.ii'j and the counterelectrode. Thus, this device has p packets of k image points each, each image point and the switch associated therewith constituting one of the elements of the matrix of elements of the display device. The switches of the display device according to the invention are advantageously field effect transistors.

Thus, each electrode E.sub.l of a packet P.sub.ii'j is connected to the source or drain of a transistor I.sub.l, the gate of said transistor is connected to the resistive conductor R.sub.ii'j and its drain or source to the column conductor C.sub.j. It is possible to connect either the source or the drain of transistor I.sub.l to the corresponding column conductor and to the electrode E.sub.l.

Each resistive conductor R.sub.ii'j associated with a packet P.sub.ii'j of electrodes E.sub.1 . . . E.sub.k and connected between row conductors L.sub.i and L.sub.i', e.g., comprises in the manner shown in FIG. 2 resistors in series. Thus, a resistor r.sub.1 is inserted between row conductor L.sub.i and switch I.sub.1, a resistor r.sub.2 is inserted between switches I.sub.1 and I.sub.2 and so on up to resistor r.sub.k+1 inserted between switch I.sub.k and row conductor L.sub.i'. When k is equal to 4, the resistive conductor R.sub.ii'j comprises five resistors in series r.sub.1, r.sub.2, r.sub.3, r.sub.4 and r.sub.5.

Advantageously, each resistive conductor R.sub.ii'j of the display device has the same resistors in series r.sub.1, r.sub.2 . . . r.sub.l . . . r.sub.k+1, said resistors can have the same resistive values.

The gate of a transistor I.sub.l connected to a resistive conductor R.sub.ii'j is at a potential which is in the widest sense between the potential of the row conductor L.sub.i and the potential of the row conductor L.sub.i'. For transistor I.sub.l to be conductive or on, the potential applied to its gate must be equal to or greater than the threshold potential V.sub.t. In the opposite case the transistor is non-conductive or off.

By appropriately choosing the exciting signals applied to the row conductors, it is possible to selectively make conductive the transistors associated with these row conductors via resistive conductors. When a transistor I.sub.l connected to an electrode E.sub.l of a packet P.sub.ii'j is conductive, it transmits to electrode E.sub.l the exciting signal carried by the corresponding column conductor C.sub.j.

The display device according to the invention is compatible with all field effect transistor construction technologies, such as that which consists of producing the transistor source and drain and then its gate and that consisting of firstly producing the transistor gate and using the latter as a mask for defining the transistor drain and source, so that the latter are auto-positioned with respect to the gate.

Moreover, each resistive conductor is constituted by a resistive material deposit, whose dimensions are a function of the values of resistors r.sub.1 . . . r.sub.k+1. Moreover, the gates of the transistor are not traversed by currents, so that the latter can be defined in the resistive material deposit constituting resistive conductors. Thus, for example, a resistive conductor, whose resistors r.sub.1 . . . r.sub.k+1 are of the same value, is constituted by a resistive material deposit having k+1 parts of the same length, the same width and the same thickness, each part corresponding to a resistor and k fractions inserted between these k+1 parts constituting the gates of the transistors connected to said resistive conductor. The width of said fractions is generally less than the width of said parts.

Advantageously, the row conductors and optionally part of the column conductors are produced at the same time as the resistive conductors and the gates of the transistors, by the deposition of a resistive material, such as type n.sup.+ hydrogenated amorphous silicon, silicide or indium and tin oxide through an appropriately patterned mask. Advantageously, this is followed in known manner by a doubling of the row and column conductors, which makes it possible to reduce the resistivity thereof.

When the display device according to the invention is considered by transmission, the two walls 1,3 of the device are transparent, as are the electrodes and counterelectrode. However, when the device is considered by reflection, it is sufficient for the wall nearest to the observer to be transparent, together with the electrodes or counterelectrode associated with said wall. Obviously the two walls, the electrodes and the counterelectrode of the display device can also be transparent.

FIGS. 3 to 6 give examples of signals applied to the row and column conductors for controlling the optical property of the display material at the image points associated with a packet of electrodes.

FIG. 3 shows a first example of exciting signals making it possible to control the optical property of the display material at the image points associated with a packet P.sub.ii'j of electrodes. For reasons of clarity of the description, one has chosen packets respectively of 4 electrodes (k=4), it being understood that k can assume any random integral value starting from 1.

The exciting signals V.sub.i and V.sub.i' are respectively applied to the row conductors L.sub.i and L.sub.i'. The exciting signals V.sub.j1, V.sub.j2, V.sub.j3 and V.sub.j4 are applied to the column conductor C.sub.j for controlling a displayed state respectively at the image points corresponding to electrodes E.sub.1, E.sub.2, E.sub.3 and E.sub.4 and the exciting signals V.sub.j1,2,3 and V.sub.j1, 2,3,4 are applied to the column conductor C.sub.j for controlling a displayed state at the image points corresponding respectively to electrodes E.sub.1, E.sub.2 and E.sub.3 and to electrodes E.sub.1, E.sub.2, E.sub.3 and E.sub.4.

For addressing a packet P.sub.ii'j of electrodes, during a time T.sub.s =T/(n-1) exciting signals V.sub.i and V.sub.i' are supplied to the corresponding row conductors L.sub.i and L.sub.i', selecting either the conductive state or the non-conductive state of the transistors associated with these row conductors via resistive conductors and exciting signals are applied to the other row conductors differing from L.sub.i and L.sub.i', which block the transistors associated with said other row conductors, T being the addressing period of an image point. At the following time T.sub.s, exciting signals are supplied to two other row conductors such as conductors L.sub.i' and L.sub.i" with e.g. i'=i+1 and i"=i+2, which select the on or off state of the transistors associated therewith, whilst two other row conductors are applied signals blocking the transistors associated with said other row conductors and so on until all the packets of electrodes have been addressed. Moreover, the exciting signals carried by the column conductors are trasmitted to the electrodes connected to closed switches.

Each time T.sub.s is divided into k time fractions t.sub.l, each time fraction t.sub.l, with l being an integer such that 1.ltoreq.l.ltoreq.k, makes it possible to select the conductive state of at least one of the transistors associated with a packet of electrodes.

The following description is given for the addressing of four electrodes E.sub.1,E.sub.2,E.sub.3,E.sub.4 of a packet P.sub.ii'j (k=4). Moreover, the resistors r.sub.1, r.sub.2, r.sub.3, r.sub.4, r.sub.5 respectively inserted between conductor L.sub.i and transistor I.sub.1, between transistors I.sub.1 and I.sub.2, between transistors I.sub.2 and I.sub.3, between transistors I.sub.3 and I.sub.4 and between transistors I.sub.4 and row conductor L.sub.i' are given the same resistive value.

At time t.sub.1, signals V.sub.i and V.sub.i' respectively applied to the row conductors L.sub.i and L.sub.i' have the same value equal to V.sub.a, such that V.sub.a is equal to or greater than V.sub.t. The gates of transistors I.sub.1, I.sub.2, I.sub.3, I.sub.4 associated with electrodes E.sub.1, E.sub.2, E.sub.3, E.sub.4 are consequently at potential V.sub.a, transistors I.sub.1, I.sub.2, I.sub.3, I.sub.4 being conductive.

At time t.sub.2, signal V.sub.i is equal to V.sub.a -V.sub.1 and signal V.sub.i' is equal to V.sub.a. The gates of transistors I.sub.1, I.sub.2, I.sub.3 and I.sub.4 are respectively at potentials V.sub.a -4V.sub.1 /5, V.sub.a -3V.sub.1 /5, V.sub.a -2V.sub.1 /5 and V.sub.a -V.sub.1 /5. The value of V.sub.1 is chosen so as to verify the following inequation:

V.sub.a -kV.sub.1 /(k+1)&lt;V.sub.t .ltoreq.V.sub.a -(k-1)V.sub.1 /(k+1), in other words for k=4, V.sub.1 is such that: V.sub.a -4V.sub.1 /5&lt;V.sub.t .ltoreq.V.sub.a -3V.sub.1 /5 Thus, at time t.sub.2, the transistor I.sub.1 is blocked and transistors I.sub.2, I.sub.3 and I.sub.4 are conductive.

At time t.sub.3, signal V.sub.i is equal to V.sub.a -(V.sub.1 +V.sub.2) and signal V.sub.i' is equal to V.sub.a. The gates of transistors I.sub.1, I.sub.2, I.sub.3 and I.sub.4 are respectively at potentials V.sub.a -4(V.sub.1 +V.sub.2)/5, V.sub.a -3(V.sub.1 +V.sub.2)/5, V.sub.a -2(V.sub.1 +V.sub.2)/5 and V.sub.a -(V.sub.1 +V.sub.2)/5 with V.sub.2 such that:

V.sub.a -3(V.sub.1 +V.sub.2)/5&lt;V.sub.t .ltoreq.V.sub.a -2(V.sub.1 +V.sub.2)/5 At time t.sub.3, transistors I.sub.1 and I.sub.2 are blocked and transistors I.sub.3 and I.sub.4 are conductive.

At time.sub.4, signal V.sub.i is equal to V.sub.a -(V.sub.1 +V.sub.2 +V.sub.3) and signal V.sub.i' is equal to V.sub.a. The gates of transistors I.sub.1, I.sub.2, I.sub.3 and I.sub.4 are respectively at potentials V.sub.a -4(V.sub.1 +V.sub.2 +V.sub.3)/5, V.sub.a -3(V.sub.1 +V.sub.2 +V.sub.3)/5, V.sub.a -2 (V.sub.1 +V.sub.2 +V.sub.3)/5 and V.sub.a -(V.sub.1 +V.sub.2 +V.sub.3)/5 with V.sub.3 such that:

V.sub.a -2(V.sub.1 +V.sub.2 +V.sub.3)/5&lt;V.sub.t .ltoreq.V.sub.a -(V.sub.1 +V.sub.2 +V.sub.3)/5 Thus, at time t.sub.4, transistors I.sub.1, I.sub.2, I.sub.3 are blocked and transistor I.sub.4 is conductive.

Potentials V.sub.1, V.sub.2, V.sub.3 can be chosen equal or different. Moreover, potential V.sub.a can be equal to the sum of potentials V.sub.1, V.sub.2 and V.sub.3, as shown in FIG. 3, but it can obviously also exceed this sum.

For controlling a displayed state at image point A.sub.iij'1, or in other words for exciting the display material inserted between electrode E.sub.1 of packet P.sub.ii'j and the counterelectrode, to column conductor C.sub.j is supplied a signal V.sub.j1 of value V.sub.e during time t.sub.1 when all the switches are conductive and of zero value at times t.sub.2, t.sub.3, t.sub.4 during which transistor I.sub.1 is non-conductive. The value of V.sub.e is such that V.sub.e .gtoreq.V.sub.S.

Thus, at time t.sub.1, transistors I.sub.1, I.sub.2, I.sub.3 and I.sub.4 will transmit to the corresponding electrodes the potential V.sub.e.

At time t.sub.2, the transistor I.sub.1 is blocked, electrode E.sub.1 consequently retaining the potential V.sub.e, except for the voltage drop. Conversely, transistors I.sub.2, I.sub.3 and I.sub.4 are conductive and as signal V.sub.j1 is zero, the potentials of electrodes E.sub.2, E.sub.3 and E.sub.4 are also zero.

At times t.sub.3 and t.sub.4, during which respectively transistor I.sub.2 and transistor I.sub.3 are in turn blocked, signal V.sub.j1 remaining zero, so that the potentials of electrodes E.sub.2, E.sub.3 and E.sub.4 remain unchanged. Thus, signal V.sub.j1 makes it possible to excite the display material solely between electrode E.sub.1 and the counterelectrode.

For controlling a displayed state solely at image point A.sub.ii'j2, in other words for exciting the display material inserted between the corresponding electrode E.sub.2 and the counterelectrode, to column C.sub.j is supplied a zero signal V.sub.j2 at time t.sub.1, t.sub.3, t.sub.4 and equal to V.sub.e at time t.sub.2.

Thus, at time t.sub.1 transistors I.sub.1, I.sub.2, I.sub.3 and I.sub.4 are conductive and signal V.sub.j2 is zero, so that no potential is applied to the corresponding electrodes. At time t.sub.2, transistor I.sub.1 is non-conductive, the non-zero signal V.sub.e applied to the column C.sub.j being transmitted solely by the conductive transistors I.sub.2, I.sub.3, I.sub.4 to the corresponding electrodes E.sub.2, E.sub.3, E.sub.4. At time t.sub.3, switch I.sub.2 is blocked, so that electrode E.sub.2 retains the potential V.sub.e and conversely transistors I.sub.3 and I.sub.4 are conductive, a zero potential being applied to the corresponding electrodes. At time t.sub.4, transistor I.sub.3 is in turn blocked, the potential of electrode E.sub.3 consequently remaining zero and the transistor I.sub.4 is conductive, but as signal V.sub.j2 is zero, the potential of electrode E.sub.4 is also zero.

In the same way, for controlling a displayed state solely at image point A.sub.ii'j3, to the corresponding column conductor is supplied a signal V.sub.j3 equal to V.sub.e solely during time t.sub.3 corresponding to the final time fraction of time T.sub.s during which transistor I.sub.3 is conductive. For controlling a displayed state solely at image point A.sub.ii'j4, to the corresponding column conductor is supplied a signal V.sub.j4 equal to V.sub.e solely during the time t.sub.4 corresponding to the final time fraction of the time T.sub.s during which the transistor I.sub.4 is conductive.

When it is wished to control a displayed state at two image points corresponding to two electrodes of an electrode packet, to the corresponding column electrode C.sub.j is supplied an electric signal equal to the sum of the signals making it possible to control a displayed state at each of the image points alone. Thus, for controlling a displayed state at image points A.sub.ii'j1 and A.sub.ii'j2, to the corresponding column conductor C.sub.j is supplied a signal V.sub.j1,2 equal to the sum of signals V.sub.j1 and V.sub.j2.

For controlling a displayed state at three image points corresponding to three electrodes of an electrode packet, in the same way combination takes place of the exciting signals making it possible to control a displayed state at each of the image points alone. Thus, when it is wished to control a displayed state at image points A.sub.ii'j1, A.sub.ii'j2 and A.sub.ii'j3, to the column conductor C.sub.j is supplied a signal V.sub.j1,2,3 corresponding to the sum of the signals V.sub.j1, V.sub.j2, V.sub.j3.

In the same way, for controlling a displayed state for all the image points corresponding to an electrode packet, to the corresponding column conductor C.sub.j is supplied a signal equal to the sum of the signals making it possible to control a displayed state at each of the image points alone. Thus, for controlling a displayed state at image points A.sub.ii'j1, A.sub.ii'j2, A.sub.ii'j3 and A.sub.ii'j4, to the column conductor C.sub.j is supplied a signal V.sub.j1,2,3,4 corresponding to the sum of the signals V.sub.j1, V.sub.j2, V.sub.j3 and V.sub.j4.

This example of the control of the display device according to the invention consequently comprises applying to the row conductors L.sub.i and L.sub.i', exciting signals V.sub.i and V.sub.i' bringing about for each time fraction t.sub.l of the addressing time T.sub.s of electrodes of a packet, the passing state of transistors I.sub.l . . . I.sub.k associated with said electrodes and the block state of the other transistors associated with said electrodes. The signals supplied to the column conductors are dependent on the desired display.

FIG. 4 gives a variant of the signals making it possible to control the optical property of the material at the image points corresponding to the electrode packets, no matter what the value of k. For reasons of clarity, k has been chosen equal to 4.

To row conductor L.sub.i is applied a signal V.sub.i and to row conductor L.sub.i' a signal V.sub.i'. At time t.sub.1, signals V.sub.i and V.sub.i' have the same value V.sub.a. The gates of the transistors I.sub.1, I.sub.2, I.sub.3 and I.sub.4 associated with electrodes E.sub.1, E.sub.2, E.sub.3 and E.sub.4 are at potential V.sub.a. Thus, transistors I.sub.1, I.sub.2, I.sub.3 and I.sub.4 are conductive.

At time t.sub.2 signal V.sub.i is equal to V.sub.a and signal V.sub.i is equal to V.sub.a -V.sub.1. The gates of transistors I.sub.1, I.sub.2, I.sub.3, I.sub.4 are respectively at potentials V.sub.a -V.sub.1 /5, V.sub.a -2V.sub.1 /5, V.sub.a -3V.sub.1 /5, V.sub.a -4V.sub.1 /5. The value V.sub.1 is chosen so as to verify the same condition as for FIG. 3. Thus, at time t.sub.2 transistor I.sub.4 is blocked and transistors I.sub.1, I.sub.2 and I.sub.3 are conductive.

At time t.sub.3, signal V.sub.i is equal to V.sub.a and signal V.sub.i' is equal to V.sub.a -(V.sub.1 +V.sub.2). The gates of transistors I.sub.1, I.sub.2, I.sub.3 and I.sub.4 are respectively at potentials V.sub.a -(V.sub.1 +V.sub.2)/5, V.sub.a -2(V.sub.1 +V.sub.2)/5, V.sub.a -3(V.sub.1 +V.sub.2)/5, V.sub.a -4(V.sub.1 +V.sub.2)/5 with V.sub.2 verifying the same condition as for FIG. 3. Thus, at time t.sub.3, the transistors I.sub.3 and I.sub.4 are non-conductive and transistors I.sub.1 and I.sub.2 are conductive.

At time t.sub.4, signal V.sub.i is equal to V.sub.a and signal V.sub.i' is equal to V.sub.a -(V.sub.1 +V.sub.2 +V.sub.3). The gates of transistors I.sub.1, I.sub.2, I.sub.3, I.sub.4 are respectively at potentials V.sub.a -(V.sub.1 +V.sub.2 +V.sub.3)/5, V.sub.a -2(V.sub.1 +V.sub.2 +V.sub.3)/5, V.sub.a -3(V.sub.1 +V.sub.2 +V.sub.3)/5 and V.sub.a -4(V.sub.1 +V.sub.2 +V.sub.3)/5 with V.sub.3 verifying the same condition as for FIG. 3. Thus, at time t.sub.4 transistors I.sub.2, I.sub.3 and I.sub.4 are non-conductive and transistor I.sub.1 is conductive.

Moreover, for controlling a displayed state at image point A.sub.ii'j1, to the corresponding column conductor C.sub.j is supplied a zero signal V.sub.j1 at times t.sub.1, t.sub.2, t.sub.3 and equal to V.sub.e at time t.sub.4. For controlling a displayed state at image point A.sub.ii'j2, to the corresponding column conductor C.sub.j is supplied a zero signal V.sub.j2 at time t.sub.1, t.sub.2 and t.sub.4 and equal to V.sub.e at time t.sub.3. For controlling a displayed state at image point A.sub.ii'j3 to column conductor C.sub.j is supplied a zero signal V.sub.j3 at times t.sub.1, t.sub.3, t.sub.4 and equal to V.sub.e at time t.sub.2. Finally, for controlling a displayed state at image point A.sub.ii'j4, to the corresponding column conductor C.sub.j is supplied a zero signal V.sub.j4 at times t.sub.2, t.sub.3 and t.sub.4 and equal to V.sub.e at time t.sub.1.

As a function of the image points of a packet of electrodes for which it is wished to control a displayed state, the signals V.sub.j1, V.sub.j2, V.sub.j3 and V.sub.j4 are combined for controlling said displayed state in two, three or even four image points.

Thus, signal V.sub.j1,2 supplied to the column conductor C.sub.j corresponding to the sum of the signals V.sub.j1, V.sub.j2 makes it possible to control a displayed state at image points A.sub.ii'j1 and A.sub.ii'j2. Signal V.sub.j1,2,3 supplied to column conductor C.sub.j corresponding to the sum of the signals V.sub.j1, J.sub.j2 and V.sub.j3 makes it possible to control a displayed state at image points A.sub.ii'j1, A.sub.ii'j2, A.sub.ii'j3. Signal V.sub.j1,2,3,4 applied to the column conductor C.sub.j corresponding to the sum of V.sub.j1, V.sub.j2, V.sub.j3 and V.sub.j4 makes it possible to control a displayed state at image points A.sub.ii'j1, A.sub.ii'j2, A.sub.ii'j3, A.sub.ii'j4.

For controlling the display device according to the invention, thus e.g. to the row conductors L.sub.i and L.sub.i' are supplied exciting signals V.sub.i and V.sub.i', so that for each time fraction t.sub.l of the addressing time T.sub.s of the electrodes of an electrode packet the transistors I.sub.1 . . . I.sub.u associated with these electrodes are closed, u being an integer such that u=k-(l-1) and the other transistors associated with these electrodes are opened. The signals supplied to the column conductors are dependent on the desired display.

FIG. 5 gives an example of signals making it possible to control the display device in the particular case where each packet comprises three electrodes, such as in the case of a three-colour display.

Thus, for controlling the optical property of the material at image points A.sub.ii'j1, A.sub.ii'j2, A.sub.ii'j3 corresponding to the packet P.sub.ii'j of electrodes E.sub.1, E.sub.2, E.sub.3, to the row conductor L.sub.i is applied potential V.sub.i and to row conductor L.sub.i' potential V.sub.i'. The addressing time T.sub.s of the packet P.sub.ii'j of electrodes is divided into three time fractions t.sub.1, t.sub.2 and t.sub.3. At time t.sub.1 signals V.sub.i and V.sub.i' have the same value V.sub.a. The gates of transistors I.sub.1, I.sub.2, I.sub.3 associated with electrodes E.sub.1, E.sub.2, E.sub.3 of packet P.sub.ii'j are at potential V.sub.a. Thus, transistors I.sub.1, I.sub.2, I.sub.3 are conductive. At time t.sub.2, signal V.sub.i is equal to V.sub.a and signal V.sub.i' is zero. The gates of transistors I.sub.1, I.sub.2, I.sub.3 are respectively at potentials V.sub.a /2, V.sub.a /3, V.sub.a /4 so that transistor I.sub.1 is conductive and transistors I.sub.2 and I.sub.3 non-conductive. At time t.sub.3, signal V.sub.i is zero and signal V.sub.i' is equal to V.sub.a. The gates of transistors I.sub.1, I.sub.2, I.sub.3 are respectively at potentials V.sub.a /4, V.sub.a /3, V.sub.a /2, so that transistors I.sub.1 and I.sub.2 are non-conductive and transistor I.sub.3 is conductive.

To control a displayed state at image point A.sub.ii'j1, to the corresponding column conductor C.sub.j is supplied a zero signal V.sub.j1 at times t.sub.1 and t.sub.3 and equal to V.sub.e at time t.sub.2 during which only transistor I.sub.1 is conductive. For controlling a displayed state at image point A.sub.ii'j2, to column conductor C.sub.j is supplied a signal V.sub.j2 equal to V.sub.e at time t.sub.1 during which transistor I.sub.2 is conductive and zero at the following times t.sub.2 and t.sub.3. For controlling a displayed state at image point A.sub.ii'j3, to the corresponding column conductor C.sub.j is supplied a signal V.sub.j3 zero at times t.sub.1 and t.sub.2 and equal to V.sub.e at time t.sub.3 during which only transistor I.sub.3 is conductive. For controlling a displayed state at image points A.sub.ii'j1 and A.sub.ii'j2, to the corresponding column conductor C.sub.j is supplied a signal V.sub.j1,2 corresponding to the sum of the signals V.sub.j1 and V.sub.j2. For controlling a displayed state at image points A.sub.ii'j1 and A.sub.ii'j3 to the corresponding column conductor C.sub.j is supplied a signal V.sub.j1,3 corresponding to the sum of the signals V.sub.j1 and V.sub.j3. For controlling a displayed state at images points A.sub.ii'j2 and A.sub.ii'j3, to the corresponding column conductor C.sub.j is supplied a signal V.sub.j2,3 corresponding to the sum of the signals V.sub.j2 and V.sub.j3. Finally, for controlling a displayed state at image points A.sub.ii'j1, A.sub.ii'j2 and A.sub.ii'j3 to the column conductor C.sub.j is supplied a signal V.sub.j1,2,3 equal to the sum of the signals V.sub.j1, V.sub.j2 and V.sub.j3.

It is obvious that for display devices having packets of three electrodes, the control proccesses described relative to FIGS. 3 and 4 are also applicable.

For displaying grey levels, the signals applied to the column conductors must assume variable voltage levels.

In the case of a packet of three electrodes, FIG. 6 shows in exemplified manner the signal applied to the column conductor C.sub.j making it possible to display grey levels at the corresponding image points.

Signals V.sub.i and V.sub.i' applied to the row conductor L.sub.i and L.sub.i' are e.g. identical to those described relative to FIG. 5. However, the signal V.sub.i applied to the column conductor C.sub.j assumes different values V', V", V'", all three of said values being equal to or higher than the threshold potential V.sub.S and such that V' V" V'".

Thus, at time t.sub.1 during which transistors I.sub.1, I.sub.2 and I.sub.3 are conductive, the signal applied to the column conductor C.sub.j is equal to V' and the potentials V.sub.E1, V.sub.E2 and V.sub.E3 respectively of electrodes E.sub.1, E.sub.2 and E.sub.3 are equal to V'.

At time t.sub.2 during which the transistor I.sub.1 is conductive, transistors I.sub.2 and I.sub.3 are blocked, the signal V.sub.j applied to the column conductor C.sub.j assuming the value V". Furthermore, the potentials V.sub.E1, V.sub.E2, V.sub.E3 of electrodes E.sub.1, E.sub.2, E.sub.3 are respectively equal to V", V' and V'.

At time t.sub.3 during which transistors I.sub.1 and I.sub.2 are blocked and transistor I.sub.3 conductive, signal V.sub.j supplied to the column conductor C.sub.j assumes the valve V'", the potentials V.sub.E1, V.sub.E2 and V.sub.E3 respectively of electrodes E.sub.1, E.sub.2, E.sub.3 are consequently equal to V", V' and V'".

The potentials retained by electrodes E.sub.1, E.sub.2 and E.sub.3 during the remainder of the period correspond to potentials V", V' and V'", except for the load leaks. These different potential values consequently make it possible to display different grey levels at each image point associated with a group of electrodes of the display device.

FIGS. 3 to 6 illustrate examples of control processes, whereof the signals applied to the row conductors vary from the value V.sub.a to a zero value and the signals applied to the column conductors vary from V.sub.e or V' to a zero value, but obviously the signals applied to the row conductors varying from value V.sub.a to a non-zero value below V.sub.t make it possible to select in the same way the conductive or non-conductive state of the transistors and the signals applied to the column conductors varying from V.sub.e or V' to a non-zero value below V.sub.S are also possible.

Moreover, the examples of the control process described hereinbefore are not limitative and numerous variants are possible thereto without passing beyond the scope of the invention.

Thus, for example, with the control processes described relative to FIGS. 3 and 4 by applying exciting signals to the column conductors assuming different values, as described relative to FIG. 6, it is also possible to display different grey levels.

Moreover, FIGS. 3 and 4 show signals V.sub.i and V.sub.i', applied to the row conductors L.sub.i and L.sub.i', whereof one has a fixed value and another a variable value during time T.sub.s, but obviously it is possible to apply to said row conductors signals V.sub.i and V.sub.i' respectively assuming different values during time T.sub.s so as to select for each time fraction t.sub.l of time T.sub.s, the closure of at least one of the switches associated with an electrode packet.

The above description relates to a display device having a matrix of electrodes and a counterelectrode, but it is obvious that the invention also applies to other display devices, such as that described in FR-A-No. 2 553 218.

Thus, for example, a display device according to the invention of the type described in FR-A-No. 2 553 218 has a display material inserted between two walls. On one of the walls are arranged m column conductors, each connected to a column electrode and on the other wall n row conductors, p=(n-1).m resistive conductors and p.k electrodes, each resistive conductor R.sub.ii'j being connected between two row conductors L.sub.i and L.sub.i' with i.noteq.i', 1.ltoreq.i&lt;n, 1&lt;i.ltoreq.n, and 1.ltoreq.j.ltoreq.m. The p.k electrodes are grouped into p packets of k electrodes each, all the electrodes of a packet facing the same column electrode. Moreover, the electrodes E.sub.1 . . . E.sub.k of a packet P.sub.ii'j are respectively connected by transistors I.sub.1 . . . I.sub.k to the resistive conductor R.sub.ii'j, itself being connected between the row conductors L.sub.i and L.sub.i', said transistors also being connected to a reference potential.

Claims

1. A matrix device having a liquid crystal material with an optical property inserted between a first and a second insulating wall, said device comprising a matrix of p packets of k elements each, each of said elements being constituted by a switch and an image point defined by a capacitor formed of two opposed electrodes on said first and second insulating walls,

n row conductors,

m column conductors,

p resistive conductors, each resistive conductor Rii'j being connected between two row conductors Li, Li', with p, k, n, m, i, i' and j being integers such that 1.ltoreq.i&lt;n, 1&lt;i'.ltoreq.n and i'=i+1, 1.ltoreq.j.ltoreq.m and p=m. (n-1), and said elements of each of said packets being connected to a column conductor and to a resistive conductor, and means for conducting signals appropriate for the excitation of said display material to said row conductors and to said column conductors.

2. Matrix display according to claim 1, characterized in that on the inner face of the first wall there are n row conductors, m column conductors, p resistive conductors and electrodes grouped into p packets of k electrodes each, with p, k, m and n being integers and p=m(n-1), the electrodes E.sub.1 . . . E.sub.k of a packet P.sub.ii'j being respectively connected by switches I.sub.1 . . . I.sub.k to a column conductor C.sub.j and to a resistive conductor Rii'j, itself connected between two row conductors L.sub.i and L.sub.i', with i, i' and j such that 1.ltoreq.i&lt;n, 1&lt;i'.ltoreq.n, i'=i+1 and 1.ltoreq.j.ltoreq.m and on the inner face of the second wall is disposed a counterelectrode formed from a continuous layer of a conductive material raised to a reference potential.

3. Display device according to claim 2, characterized in that the switches are field effect transistors, each transistor I.sub.l associated with an electrode E.sub.l of a packet P.sub.ii'j being connected by its gate to the corresponding resistive conductor R.sub.ii'j, by a second terminal to the corresponding column conductor C.sub.j and by a third terminal to the electrode E.sub.l, with L being integer such that 1.ltoreq.l.ltoreq.k.

4. Display device according to claim 1, characterized in that the resistive conductors comprise resistors connected one to the other in series.

5. Display device according to claim 1, characterized in that the resistive value of each resistive conductor of the device is identical.

6. Display device according to claim 1, characterized in that the resistive value of a resistive conductor R.sub.ii'j that is connected by k switches I.sub.1 . . . I.sub.k to the image points A.sub.ii'j1 . . . A.sub.ii'jk of a packet of elements, between the row conductor L.sub.i and switch I.sub.1, between the row conductor L.sub.i ' and switch I.sub.k and between the different switches I.sub.1 and I.sub.2, I.sub.2 and I.sub.3 . . . I.sub.i-1 and I.sub.k to which it is connected, is identical with i, i', j and k being integers such that i.noteq.i', 1.ltoreq.i&lt;n, 1&lt;i.ltoreq.n and 1.ltoreq.j.ltoreq.m.

7. A process for the control of a liquid crystal display device characterized in that for controlling the optical property of the display material at image points A.sub.ii'j1 . . . A.sub.ii'jk corresponding to a packet of elements, with i, i', j and k being integers such that 1.ltoreq.i&lt;n, 1&lt;i'.ltoreq.n, i'=i+1 and 1.ltoreq.j.ltoreq.m, during a time T.sub.s =T/(n-1) divided into k time fractions t.sub.l are applied to the row conductors L.sub.i and L.sub.i', respectively exciting signals V.sub.i and V.sub.i', so that for each time fraction t.sub.l at least one of the switches I.sub.1 . . . I.sub.k associated with said points is closed, so that each of said switches is closed over at least one time fraction t.sub.l, with l being an integer such that 1.ltoreq.l.ltoreq.k, said switches being connected to the resistive conductor R.sub.ii'j and to the other row conductors, exciting signals bringing about the opening of the switches associated with said other row conductors, T being the addressing period of an image point, and in that, at each time T.sub.s, a signal corresponding to an information to display on the image points is applied on the column conductors.

8. Control process according to claim 7, characterized in that to the row conductors L.sub.i and L.sub.i' are respectively applied exciting signals V.sub.i and V.sub.i', so that at each time fraction t.sub.l of the addressing time T.sub.s of image points A.sub.ii'j1 . . . A.sub.ii'jk, with l being an integer such that 1.ltoreq.l.ltoreq.k, one of the switches associated with said image points and closed during time t.sub.l-1 is opened, the other switches remaining in their state, all the switches associated with said image points being closed at time t.sub.1.

9. Control process according to claim 7, characterized in that to the row conductors L.sub.i and L.sub.i', are respectively applied exciting signals V.sub.i and V.sub.i', so that at each time fraction t.sub.l of the addressing time T.sub.s of the image points A.sub.ii'j1 . . . A.sub.ii'jk, the switches I.sub.1 . . . I.sub.u associated with said image points are closed, with u being an integer such that u=k-(l-1) and the other switches associated with said image points are opened.

10. Control process according to claim 7, characterized in that to the row conductors L.sub.i and L.sub.i' are respectively applied exciting signals V.sub.i and V.sub.i', so that at each time fraction t.sub.l of the addressing time T.sub.s of the image points A.sub.ii'j1 . . . A.sub.ii'jk the switches I.sub.l . . . I.sub.k associated with said image points are closed and the other switches associated with said image points are opened.

11. Control process according to claim 7, characterized in that k is equal to three, so that to the row conductors L.sub.i and L.sub.i' are respectively applied exciting signals V.sub.i and V.sub.i', so that at time t.sub.1 switches I.sub.1, I.sub.2 and I.sub.3 are closed, at time t.sub.2 switch I.sub.1 is closed and switches I.sub.2, I.sub.3 are opened and at time t.sub.3 switch I.sub.3 is closed and switches I.sub.1 and I.sub.2 are opened, times t.sub.1, t.sub.2, t.sub.3 being three time fractions of the addressing time T.sub.s of the image points A.sub.ii'j1, A.sub.ii'j2, A.sub.ii'j3.