Patent Application
20220358184
The present application claims priority to Chinese Patent Application No. 202110497293.9, titled “MATRIX MULTIPLICATION CIRCUIT MODULE AND MATRIX MULTIPLICATION METHOD”, filed on May 7, 2021 with the Chinese Patent Office, which is incorporated herein by reference in its entirety.
The present disclosure relates to the technical field of neural network, and in particular to a matrix multiplication circuit module implemented by hardware, and a matrix multiplication method.
With the development of technology, a large amount of computational operations are required, including matrix multiplication.
The matrix multiplication may be implemented by a software program. To increase the computational speed, the matrix multiplication may be implemented by hardware.
This summary is provided to introduce the idea in a simplified form. The idea will be described in detail in the following description. This summary is neither intended to identify key features or essential features of the claimed technical solution, nor intended to be used to limit the scope of the claimed technical solution.
A matrix multiplication circuit module and a matrix multiplication method are provided according to embodiments of the present disclosure.
In a first aspect, a matrix multiplication circuit module is provided according to embodiments of the present disclosure, which includes one or more row-column calculation units for realizing row-column multiplication calculation. Each of the row-column calculation units comprises one or more multiplying units and an adding unit. Each of the one or more multiplying unit has an output end connected to an input end of the adding unit. Each of the multiplying units comprises an electrical signal regulating subunit and a load. The electrical signal regulating subunit is configured to regulate a magnitude of an input electrical signal. A multiplication operation is performed by the electrical signal regulating subunit and the load in response to an electrical signal inputted to the multiplying unit. The load has a fixed load value.
In a second aspect, a matrix multiplication method is provided according to embodiments of the present disclosure, which is applied to the circuit module described in the first aspect. The method includes: obtaining a row matrix element of a row of a first matrix and a column matrix element of a column of a second matrix, wherein the column of the second matrix corresponds to the row of the first matrix, and the row matrix element is represented by an electrical signal; inputting the electrical signal representing the row matrix element to the row-column calculation unit, and regulating the electrical signal by the electrical signal regulating subunit based on a value of the column matrix element, wherein the row-column calculation unit comprises one or more multiplying unit and an adding unit, the multiplication unit comprises an electrical signal regulating subunit and a load; and determining a sum of response signals of all the multiplication units as a calculation result of the row-column calculation unit, wherein for each of the multiplication units, a response signal of the multiplication unit is obtained by applying an electric signal regulated by the electric signal regulating subunit of the multiplication unit to the load of the multiplying unit.
In a third aspect, an integrated circuit is provided according to embodiments of the present disclosure, which includes the matrix multiplication circuit module described in the first aspect.
The above and other features, advantages and aspects of various embodiments of the present disclosure will become more clear when taken in conjunction with the accompanying drawings and with reference to the following detailed description. Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. It should be understood that the drawings are schematic and that the units and elements are not necessarily drawn to scale.
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. The embodiments are provided for a more thorough and complete understanding. It should be understood that the drawings and embodiments of the present disclosure are only provided as examples, and are not intended to limit the protection scope of the present disclosure.
It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and/or in parallel. Furthermore, method embodiments may include additional steps and/or omit an illustrated step. The scope of the present disclosure is not limited in this regard.
As used herein, the terms “including” and “comprising” and variations thereof are non-exclusive, i.e., meaning “including but not limited to”. The term “based on” means “at least partially based on”. The term “an embodiment” means “at least one embodiment”, the term “another embodiment” means “at least one another embodiment”, and the term “some embodiments” means “at least some embodiments”. Relevant definitions of other terms will be given in the description below.
It should be noted that concepts such as “first” and “second” mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of functions performed by these devices, modules or units.
It should be noted that the modifications of “a” and “a plurality” mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless clearly indicated otherwise, they should be understood as “one or more”.
The names of messages or information exchanged between multiple devices in the embodiments of the present disclosure are only for illustrative purposes, and are not intended to limit the scope of these messages or information.
The row-column calculation unit 11 includes at least one multiplying unit 110 and an adding unit 111. As shown in
An output of the at least one multiplying unit 110 is connected to an input of the adding unit 111.
The load value of the load 1102 is fixed. That is, the magnitude of the load value of the load 1102 cannot be regulated.
In this embodiment, the electrical signals inputted to a same row-column calculation units 11 may be different from each other.
In some application scenarios, the above-mentioned matrix multiplication realizes the multiplication of the feature matrix outputted by neurons in a neural network and a weight matrix, and the above-mentioned electrical signals may represent the matrix elements in the feature matrix outputted by the neurons. Different electrical signals in the same row-column calculation unit may represent different matrix elements in the feature matrix. The above feature matrix can be represented as an electrical signal matrix.
The above-mentioned electrical signal regulating unit may regulate the magnitude of the electrical signal. Taking a voltage signal as an example, the electrical signal regulating unit can regulate the magnitude of the voltage signal inputted to the row-column calculation unit.
In some optional embodiments, the electrical signal is a voltage signal, or a current signal. The present disclosure is provided by using an example that the electrical signal is a voltage signal. The above-mentioned electrical signal regulating unit may include a voltage signal duty cycle regulating unit.
In some optional embodiments, the above-mentioned electrical signal may be a pulse signal. The period of the pulse signal may be T. The duty cycle of the pulse signal is regulated by regulating the duration of an effective working level (e.g., a high level) in the pulse signal in the period T. In this example, the regulating of the magnitude of the voltage signal is achieved by regulating the duty cycle of the pulse signal.
In the present disclosure, the electrical signal regulating subunit and the load are used to implement the weight in the above-mentioned matrix multiplication. While keeping the parameter of the load unchanged, the electric signal regulating subunit regulates the duty cycle of the electric signal according to the change of the weight. The response signal obtained by applying the regulated electrical signal to the load is the same as the response signal obtained by regulating the load value of the load according to the weight. That is, the weight value is changed by regulating the duty cycle of the electrical signal according to the weight value and applying the regulated electrical signal to the load.
In the related art, in order to realize the multiplication of the feature matrix outputted by the neurons and the weight matrix, a load with an adjustable load value (such as a resistor) is used to realize the weight in the weight matrix. For different weights, the load is regulated to different load values. For each row-column calculation unit, in order to regulate the load values of the loads in the row-column calculation unit, it is necessary to arrange multiple loads with fixed load values, connect these loads according to a preset connection method, and use logic circuits, switch circuits and other circuits to control the load values of the loads. Therefore, this circuit that realizes different weights by regulating the load values has a complicated structure.
The matrix multiplication circuit module provided in this embodiment uses a load with a fixed load value and regulate the magnitude of the electrical signal by regulating the duty cycle of the electrical signal according to the matrix elements (weights) in the weight matrix. By applying the regulated electric signal to the load, the effect of multiplying the weight value and the electric signal can be realized,which is convenient to adapt to the change of the weight value. Therefore, the structure of the circuit module for realizing matrix multiplication is simplified, and the complexity of the matrix multiplication circuit module for realizing matrix multiplication is reduced.
In an embodiment, the duty cycle of the voltage signal may be regulated through the electronically controlled pulse width modulation (pulse width modulation, PWM) technique.
In the electronically controlled pulse width modulation technique, a phase locked loop based phase interposer (PLL based phase interposer) may be used to generate the control signal. The control signal is applied to the switch circuit, to cotnrol the switch circuit to be switched on or off, so as to realize the regulation of the duty cycle of the electrical signal.
The control signal generating circuit can regulate the duration of the effective working signal of the control signal in the period Ti of the control signal according to the change of the value of a matrix element in the weight matrix. The effective working signal can switch the switching device on, so that the electrical signal is applied to the load. During the inactive working signal in the period T1, the switching device is switched off, so that the electrical signal is not applied to the load. For example, when the control signal is at a high level, the switch circuit is switched on, and when the control signal is at a low level, the switch circuit is switched off. The duration that the switch circuit is switched on is positively related to the duty cycle of the control signal. In this way, the duty cycle of the electrical signal applied to the load is regulated, thereby regulating the magnitude of the electrical signal.
Taking the amplitude of the electrical signal being 12V as an example, when the duty cycle is 1, the electrical signal applied the above-mentioned load is 12V. The duty cycle of the electrical signal applied to the load can be controled to ½ by the control signal, so that the electrical signal applied to the load is 6V.
Further, the same control signal generating circuit 1103 (e.g., the DLL based phase interposer) can be used to generate the control signals Cin corresponding to multiple row-column calculation units. The multiple control signals generated by the same DLL based phase interposer can be respectively inputted to the corresponding row-column calculation units through a multiplexer. The input terminal of the switch circuit in the row-column calculation unit is inputted with the electrical signal outputted by the multiplexer, and the output terminal of the switch circuit is connected to the load. After the electrical signal regulating subunit outputs the control signal Cin of the preset duty ratio through the multiplexer, the switch circuit is switched on or off under the action of the pulse signal.
Using the same control signal generating circuit 1103 to generate the control signals Cin corresponding to the multiple row-column calculation units can further simplify the structure of the circuit module for realizing matrix multiplication.
In some optional implementations, the one or more multiplication units 110 included in the same row-column calculation unit 11 have the loads 1102 with the same parameter. The multiplication units use the loads of the same parameter, which means that the parameter values of the loads in the multiplication units are the same. For example, if the loads are resistors, the resistance values (or conductance values) of the resistors in the row-column calculation unit are the same.
In these optional implementations, multiplication units of the row-column calculation unit may include the loads 1102 with the same parameter. The weights corresponding to each multiplication unit of the row-column calculation unit may be jointly realized by the electrical signal regulating subunit and the load of the multiplication unit.
In these optional implementations, since the same load is used in the same row-column calculation unit, the process of manufacturing the load can be simplified compared to the method of fabricating different loads in a same row-column calculation unit, thereby reducing complexity of the structure and the manufacturing process of the circuit module for realizing matrix multiplication.
Further, for one or more row-column calculation unit that implements the row-column multiplication calculation, the multiplication units in the row-column calculation units may have loads with the same parameter. The row-column calculation units use the loads of the same parameter, which means that the parameter values of the loads used by the row-column calculation units are the same. For example, if the loads are resistors, the resistance values (or conductance values) of the resistors used by the row-column calculation units are the same. The process of manufacturing the load can be further simplified, thereby further reducing the complexity of the manufacturing process of the circuit module for realizing matrix multiplication.
In some application scenarios,
In the row-column calculation unit shown in
For the input signal Vin1, through the multiplication unit 110, the resistor 1102 (R) responds to the input Vin1, and the response signal outputted by the resistor 1102 is the current signal I1:
For the input signal Vin2, through the multiplication unit 110′, the resistor 1102′ (R) responds to the input Vin2, and the response signal outputted by the resistor 1102′ is the current signal I2:
The above adding unit 111 is realized by connecting the multiplying unit 110 and the multiplying unit 110′ in parallel. The multiplying unit 110 and the multiplying unit 110′ are connected in parallel so that the output “out” of the row-column calculation unit is the sum of the current signal I1 and current signal I2. That is:
The row-column calculation unit shown in
A row of the above electrical signal matrix includes two matrix elements Vin1 and Vin2. A column of the above weight matrix includes two matrix elements D11*C and D21*C. Here, D11 is a voltage signal regulation ratio realized by the duty cycle of the voltage signal Vin1 regulated by the electrical signal regulating subunit 1101, and D12 is the voltage signal regulation ratio realized by the duty cycle of the voltage signal Vin2 regulated by the electrical signal regulating subunit 1101′.
For the input signal Vin1, through the multiplying unit 110, the capacitor 1102 (C) responds to the input Vin1, and the response signal outputted by the capacitor 1102 is the charge signal Q1:
Q1=Vin1×D11×C (4).
For the input signal Vin2, through the multiplication unit 110′, the capacitor 1102′ (R) responds to the input Vin2, and the response signal outputted by the resistor 1102′ is the charge signal Q2:
Q2=Vin2×D12×C (5).
The above adding unit 111 is realized by connecting the multiplying unit 110 and the multiplying unit 110′ in parallel. The multiplying unit 110 and the multiplying unit 110′ are connected in parallel so that the output “out” of the row-column calculation unit is the sum of the above-mentioned charge signal Q1 and charge signal Q2. That is:
out=Q1+Q2=Vin1×D11×C+Vin2×D12×C (6).
The row-column calculation unit shown in
An integrated circuit is provided according to some embodiments of the present disclosure. The integrated circuit includes the matrix multiplication circuit module in the above embodiments as shown in
As shown in
In step 501, a row matrix element of a row of a first matrix and a column matrix element of a column of a second matrix are obtained, where the column of the second matrix corresponds to the row of the first matrix, and the row matrix element is represented by an electrical signal.
The matrix multiplication includes performing a row-column multiplication calculation on each row matrix element of the first matrix and a corresponding column matrix element in the second matrix. In this embodiment, the realization of matrix multiplication is described by taking the realization of row-column multiplication as an example.
The first matrix here may include n*m matrix elements. That is, it includes n rows and m columns of matrix elements, where n and m are integers greater than or equal to 1.
The second matrix may include m*p matrix elements, that is, it includes m rows and p columns of matrix elements, where m and p are integers greater than or equal to 1.
The matrix elements in the first matrix may be represented by electrical signals. That is, the magnitude of the electrical signal may be used to repserent the values of the matrix elements. The electrical signal here may be a voltage signal or a current signal. An example that the electrical signal is a voltage signal is used for description.
In some application scenarios, the above-mentioned first matrix is a feature matrix outputted by neurons of a neural network. In these application scenarios, a matrix element in the first matrix can be regarded as a feature value outputted by a neuron. The second matrix may be a weight matrix. The weights in the weight matrix correspond to the feature values in the one-to-one correspondance.
In step 502, the electrical signal corresponding to the row matrix element is inputted to the row-column calculation unit, and the electrical signal regulating subunit is used to regulate the electrical signal based on a value of a column matrix element. The row-column calculation unit includes at least one multiplication unit and an adding unit. The multiplication unit includes an electrical signal regulating subunit and a load, and a load value of the load is fixed.
The number of multiplication units included in the row-column calculation unit may match the number of matrix elements included in a row of the first matrix.
The above multiplication unit is configured to realize the multiplication of a row matrix element in a row in the first matrix and a column matrix element in a corresponding column of second matrix.
In this embodiment, the load value of the load is fixed.
The load may be a resistor or a capacitor.
The electrical signal includes a voltage signal, and the electrical signal regulating subunit includes a voltage signal duty ratio regulating unit. The voltage signal duty ratio regulating unit includes a control signal generating circuit and a switch circuit. The above step 502 includes the following substeps.
First, a control signal matching the value of the column matrix element is generated by the control signal generating circuit.
Then, the control signal is applied to the switch circuit to control the switch circuit to be switched on or off, to regulate the magnitude of the voltage signal applied to the load to match the column matrix element. For a specific description, reference may be made to the description of the electrical signal regulating subunit shown in
For each multiplication unit implementing the multiplication of a row matrix element and a column matrix element, the electrical signal regulating subunit may be used to regulate the magnitude of the electrical signal representing the row matrix element according to the value of the column matrix element. The function of the regulation ratio of the electrical signal in combination with the load matches the value of the column matrix element.
For a neural network, a same neural network unit may correspond to multiple matrix multiplications. The matrix elements in the weight matrix corresponding to different matrix multiplications may be different from each other. In order to adapt to the situation that weights corresponding to multiple matrix multiplications are different, the matrix multiplication circuit module for implementing matrix multiplication provided by the present disclosure and the matrix multiplication method provided in this embodiment can be used to complete matrix multiplication. By regulating the input electrical signal, the complexity of the circuit structure for realizing matrix multiplication can be reduced.
In step 503, the sum of the response signals of the multiplication units is used as the calculation result obtained by the row-column calculation unit. The response signal of the multiplication unit is obtained by applying the electrical signal regulated by the electrical signal regulating subunit of the multiplication unit to the load of the multiplication unit.
If the above load is a resistor, the response signal outputted by the multiplication unit is a current signal. If the load is a capacitor, the response signal outputted by the multiplication unit is a charge signal.
With the matrix multiplication circuit module and the matrix multiplication method provided by the embodiments of the present disclosure, by using a load with a fixed load value and regulating the electrical signal by the electrical signal regulating subunit of the multiplication unit, the column matrix element is achieved by the regulation ratio and the load. By applying the regulated electric signal to the load, the effect of multiplying electrical sigal representing the row matrix element and the corresponding cloumn martix element can be realized, which is convenient to adapt to the change of the cloumn martix element. Therefore, the structure of the circuit module for realizing matrix multiplication is simplified, and the complexity of the circuit module is reduced.
The above merely describes preferred embodiments of the present disclosure and illustrates the technical principles. Those skilled in the art should understand that the scope of the disclosure is not limited to the technical solutions formed by the specific combination of the technical features, and should also cover, without departing from the above disclosed concept, the technical solutions formed by any combination of the technical features or other equivalent features. For example, a technical solution may be formed by replacing a feature with another feature having similar function disclosed in the present disclosure (but not limited to).
Additionally, although operations are illustrated in a particular order, this should not be construed as requiring the operations to be performed in the particular shown order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarily, although the above discussion contains severalspecific details, these should not be construed as limitations on the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be combined into a same embodiment. Conversely, various features that are described in the context of a same embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or logical method steps, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or steps described above. Rather, the specific features and steps described above are merely examples of implementing the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202110497293.9 | May 2021 | CN | national |
