The invention will now be described with reference to the accompanying drawing, in which
In the figures, the same reference numerals refer to the same parts.
A first embodiment of the invention is explained in connection with
Both the microprocessor 5 and the microprocessor 11 comprise functionality either in hardware or software components to carry out their respective functions as described in more detail below. Skilled persons will appreciate that the functionality of the present invention may also be accomplished by a combination of hardware and software components. As known by persons skilled in the art, hardware components, either analogue or digital, may be present within the microprocessor 5, 11 or may be present as separate circuits which are interfaced with the microprocessor 5, 11. Further it will be appreciated by persons skilled in the art that software components may be present in a memory region of the microprocessor 5, 11.
The memory 20 may comprise a plurality of memory components, including a hard disk. Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), and Random Access Memory (RAM). Not all of these memory types need necessarily be provided. Moreover, these memory components need not be located physically close to the processor 18 but may be located remote from the processor 18.
The processor 18 may also be connected to devices for inputting instructions, data, etc. by a user, like a keyboard, and a mouse. Other input devices, such as a touch screen, a track ball and/or a voice converter, known to persons skilled in the art may be provided too.
Reading units may be connected to the processor 18. Such reading units are arranged to read data from the possibly write data on a data carrier like a floppy disk or a CDROM. Other data carriers may be tapes, DVD, memory sticks, etc., as is known to persons skilled in the art. The processor 18 may also be connected to a printer for printing output data on paper, as well as to a display, for instance, a CRT (Cathode Ray Tube) monitor or LCD (Liquid Cystal Display) screen, or any other type of display known to persons skilled in the art.
It will be appreciated by persons skilled in the art that the microprocessor 18 may be or may comprise a digital signal processor.
The system 19 functions in the following way. The microprocessor 5 uses a send function to send a video signal via link 15 to the microprocessor 11. This video signal is equal to some kind of predetermined reference signal that is present in the memory 9 of the processor 11. As the video signal is sent by the microprocessor 5 simultaneously the microprocessor 5 starts the timer 3 by a start function. The functionality of the send function for sending the signal via link 15 is symbolically depicted by a module region 5a in the microprocessor 5, the start function for starting of the timer 3 is depicted by arrow ST. After the complete reference video signal has been received by the microprocessor 11 which uses a receive function, as depicted by module region 11a in the microprocessor 11,—the microprocessor 11 takes care of this monitoring process by comparing the predetermined reference signal stored in the memory 9 with the received reference signal—the microprocessor 11 uses a send function to send an acknowledgment signal to the processor 5. The compare function or comparator is symbolically depicted by module region 11b. The send function for sending of the acknowledgment signal is symbolically depicted by module 11c. This acknowledgement signal is a short and simple signal that will almost substantially immediately be received by the microprocessor 5. The receive function for receiving of the acknowledgement signal is symbolically depicted by module 5b in microprocessor 5. In comparison to the reference signal sent from the microprocessor 5 to the microprocessor 11, the acknowledgement signal that is sent from microprocessor 11 to the microprocessor 5 is received substantially without delay by the microprocessor 5. Typically, the acknowledgement signal is sent in 1 μsec from the microprocessor 11 to the microprocessor 5, whereas the reference signal is sent from the from the microprocessor 5 to the microprocessor 11 in 500 μsec. However, these times may vary more widely and the acknowledgement signal may be sent up to 106 times faster than the reference signal. Upon receipt of the acknowledgement signal, the microprocessor 5 stops the timer 3, which stop function is depicted by module 5c. The acknowledgement signal may be sent via the link 15 to the microprocessor 5 or alternatively via a different and/or separate return transmission path. Subsequently, the microprocessor 5 supplies the amount of time registered (Tdelay) by the timer 3 to the delay unit 7. The function of supplying the amount of time registered (Tdelay) by the timer 3 to the delay unit 7 is depicted by arrow TD.
Any signal input via input 1 is split in an audio signal Ain and a video signal Vin. The audio signal Ain is delayed by Tdelay with reference to the video signal Vin which however will mean that at the output 13 both these signals will again be synchronized. The purpose of the invention is to calculate the sum of the delays that the video signal experiences while being transmitted over path 14 and to delay the audio signal transmitted over path 16 by a corresponding amount of time. The reference signal is stored (the storage function is symbolically indicated by module 11d) in the memory 9 by the microprocessor 11. Here, the reference signal is a video picture. The reference signal will be processed by the microprocessor 5, be transmitted over the link 15 and be processed by the microprocessor 11. This will cause the reference signal to be delayed with reference to, for instance an audio signal transmitted over path 16.
One way to transfer the predetermined reference signal to the memory 9 may be as follows. The predetermined reference signal, which may be a quite arbitrary reference signal or test signal, is transmitted by the microprocessor 5 to the memory 9 over the transmission path 14 before the system 19 is really operational as described in connection with embodiment 1 above. The signal will be received by the microprocessor 11 using the receive function 11a and stored in the memory 9 using the storage function 11d. Then, the microprocessor 5 waits using a wait function (depicted by module 5d) for a predetermined period selected long enough so as to enable the complete reference signal to be received by the microprocessor 11. This predetermined period is referred to as the period of time Twait. The time Twait must be chosen long enough to allow the complete reference signal to be stored in the memory 9 by the microprocessor 11 using the storage function 11d. Typically, Twait is 0.5 sec. In principle, however, it is not necessary to wait for a period Twait, until the timer 3 can be started. It is possible to have the process of storing the reference signal in the memory by the microprocessor 11 run partly or completely simultaneously with the second transmission of the reference signal.
Alternatively to embodiment 2 described above, the predetermined reference signal may be a signal that is already stored in the memory 9 beforehand. The reference signal thus may for instance be a signal that is stored in the memory 9 during fabrication of the receiver. This has the advantage of a readily available “standard” signal.
In a further embodiment of the invention, the system 19 is arranged to determine the time Tdelay only during particular periods in the operation of the system 19. E.g., the system 19 uses a calculation function for determining the difference in the transmission time between the audio and video signals at start up of the system 19 or, additionally and alternatively at regular intervals in time. This is an advantage as in general the transmission path 14 may require an adaptation of the time Tdelay during operation of the system 19.
The transmission path 14 may partly comprise a link that is wireless. E.g. a satellite link. Other links are also to be considered to be within the scope of this invention.
The previously described systems may be used in a process as further elaborated in
When the predetermined reference signal is already present in the memory of the processor 9 see embodiment 3, the actions 23 to 31 (and 49 to 53) may be omitted. Also, the actions 21 to 61 are numbered for purposes of easy reference and not to describe a particular chronological order.
Number | Date | Country | Kind |
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04103386.1 | Jul 2004 | EP | regional |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/IB05/52292 | 7/11/2005 | WO | 00 | 1/12/2007 |