Patent Application
20240106401
This application claims the priority benefit of Italian Application for Patent No. 102022000019113, filed on Sep. 19, 2022, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.
The embodiments of the present description refer measurement systems, such as capacitive sensors.
Capacitive sensors are commonly used. For example, such capacitive sensor may have a high resolution, low complexity and low temperature-dependency. For example, such capacitive sensors may be used in microelectromechanical systems (MEMS) based sensors, such as accelerometers, position sensors, pressure sensors, and moisture sensors. Recently, such capacitive sensors have also been used for Laboratory on a Chip (LoC) applications, e.g., for DNA protein interaction quantification, cellular monitoring, bio-particle detection, organic solvent monitoring, sensing of droplet parameters, bacteria detection, etc.
In general, a capacitive sensor comprises at least one pair of sensing electrodes that are connected to an interface readout circuit.
For example,
Accordingly, in case the physical, biological and/or chemical properties of a sample 104 in the vicinity of the electrodes 100 and 102 influence the capacitance of the capacitor formed by the electrodes 100 and 102, a processing circuit, e.g., implemented within the integrated circuit 20, may be configured to provide an estimate of the physical, biological and/or chemical properties of the sample 104 as a function of the measured capacitance value.
In this respect Complementary Metal-Oxide-Semiconductor (CMOS) technology offers great advantages for the development of capacitive sensors, e.g., because it permits implementing of highly integrated circuits with low costs. This also permits achievement of a higher sensitivity and a rapid detection, and integration of the electrical readout circuit and/or the sensing electrodes on a single chip 20. Those of skill in the art will appreciate that various CMOS capacitive sensing techniques have been proposed in literature for different LoC applications. One of the most commonly used techniques is the charge-based capacitance measurement (CBCM). For example, the CBCM technique is described in document Chen, et al., “An On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement (CBCM) Technique”, International Electron Devices Meeting (IEDM) 1996, or United States Patent Publication No. 2003/0218473), the contents of each of which are incorporated herein by reference.
As mentioned before, the electrodes 100 and 102 form a sense capacitance/capacitor Cs, wherein the capacitance value of the sense capacitance Cs is usually indicative of the physical, biological and/or chemical properties of a sample 104 in the vicinity of the electrodes 100 and 102.
Specifically, in the example considered, the current path of a first electronic switch M4, such as a transistor, such as an n-channel Field-effect transistor (FET), such as an n-channel Metal-Oxide-Semiconductor (MOS) FET, is connected (e.g., directly) in parallel with the sense capacitance CS, i.e., the electronic switch M4 is connected between the electrodes 100 and 102, and is thus configured to selectively short-circuit the sense capacitance CS as a function of a control signal Φ2 received at a control terminal of the electronic switch M4, e.g., the gate terminal of a corresponding FET.
Moreover, the interface circuit comprises a second electronic switch M2, such as a transistor, such as an p-channel Field-effect transistor (FET), such as an p-channel MOSFET, configured to selectively connect the sense capacitance CS to a supply voltage VDD as a function of a control signal Φ1 received at a control terminal of the electronic switch M2, e.g., the gate terminal of a corresponding FET. For example, in the example considered, the electrode 102 of the capacitance CS is connected to a first reference voltage, e.g., ground GND, and the electrode 100 is connected via the electronic switch M2 to a second reference voltage, e.g., a supply voltage VDD of the integrated circuit 20. Accordingly, when the electronic switch M4 is opened, the electronic switch M2 may be used to selectively charge the sense capacitance CS. Accordingly, a control circuit (CC) 36 may be configured to generate the control signals Φ1 and Φ2 in order to selectively charge and discharge the sense capacitance CS.
For example, as shown in
Accordingly, the phase Δt2 is used to reset the charge of the capacitance CS and the phase Δt4 is used to charge the capacitance CS. Generally, the phases Δt1 and Δt3 are purely optional and are used to avoid the electronic switches M2 and M4 generating a short-circuit by connecting the supply voltage VDD to ground.
Accordingly, as shown in
Typically, the CBCM technique uses also a second branch, which comprises a reference capacitance CR. Typically, the reference capacitance CR has the same physical structure as the sense capacitance CS, but is not exposed to the sample 104. For example, in the absence of a sample 104, the capacitance values CS and CR typically correspond, i.e., CS=CR. Conversely, in the presence of a sample 104, the capacitance value of the sense capacitance CS varies and usually increases, i.e., CS>CR.
Accordingly, in this case, the second branch comprises: a first electronic switch M3, such as an n-channel FET, such as a n-channel MOSFET, configured to selectively short-circuit the reference capacitance CR, and a second electronic switch M1, such as a p-channel FET, such as a p-channel MOSFET, configured to selectively connect the reference capacitance CR to the supply voltage VDD.
Typically, the electronic switch M3 is driven via the control signal (2 and the electronic switch M1 is driven via the control signal Φ1. In fact, as shown in
Accordingly, in the example considered, the interface circuit 30 comprises a first half-bridge implemented with the electronic switches M2 and M4, wherein the first half-bridge is configured to selectively apply a first reference voltage (usually the supply voltage VDD) or a second reference voltage (usually ground GND) to a first terminal/electrode 100 of the sense capacitance CS, wherein the second terminal/electrode 102 of the sense capacitance CS is connected to the second reference voltage (usually ground GND). Moreover, the interface circuit 30 comprises a second half-bridge implemented with the electronic switches M1 and M3, wherein the second half-bridge is configured to selectively apply the first reference voltage (usually the supply voltage VDD) or the second reference voltage (usually ground GND) to a first terminal/electrode of the reference capacitance CR wherein the second terminal/electrode of the reference capacitance CR is connected to the second reference voltage (usually ground GND). The two half-bridges are identified as a CBCM cell 32.
For example, when using the CMOS technology, the electronic switches M3 and M4 are usually implemented with n-channel MOSFETs and the electronic switches M1 and M2 are usually implemented with p-channel MOSFETs. In this case, the source terminals of the n-channel FETs M3 and M4 are connected to the second reference voltage (e.g., ground GND), the source terminals of the p-channel FETs M1 and M2 are connected to the first reference voltage (e.g., VDD), the drain terminals of the n-channel FET M4 and the p-channel FET M2 are connected to the first terminal/electrode of the sense capacitance CS, and the drain terminals of the n-channel FET M3 and the p-channel FET M1 are connected to the first terminal/electrode of the reference capacitance CR.
Accordingly, in the CBMS technique, the properties of the sample 104 are usually evaluated based on the capacitive difference ΔC between the capacitances CS and CR, i.e., ΔC=CS−CR. For example, for this purpose, the measurement circuit 32 should be configured to generate a signal indicative of the difference Δi between the (charge or discharge) currents iS and iR, i.e., Δi=iS−iR.
In this respect, the previously cited document by Chen, et al., affirms that this technique has an intrinsic estimated sensitivity of about 10 aF. Accordingly, a major technical problem resides in the design and implementation of the measurement/readout circuit of the CBCM cell 32 that does not degrade or has only a minor impact on this performance.
Specifically, in the example considered, the measurement circuit of the CBCM cell 32 comprises a first current mirror 3400, e.g., implemented with two p-channel FETs, configured to generate a current iS′ by mirroring the (charge) current iS provided to the CBCM cell 32. This mirrored current iS′ is used to charge a first capacitance Cint+, which essentially operates as an integrator configured to convert the current iS′(t) into a voltage. Similarly, the measurement circuit of the CBCM cell 32 comprises a second current mirror 3410, e.g., implemented with two p-channel FETs, configured to generate a current iR′ by mirroring the (charge) current iR provided to the CBCM cell 32. This mirrored current iR′ is used to charge a second capacitance Cint−, which essentially operates as an integrator configured to convert the current iR′(t) into a voltage.
Accordingly, in the example considered, a differential amplifier 3420 may be used to generate a signal, e.g., a voltage Vout, by amplifying the difference between the voltage at the capacitance Cint+ and the voltage at the capacitance Cint−. For example, in the example considered, the voltage at the capacitance Cint+ is connected to the positive input terminal of the differential amplifier 3420 and the voltage at the capacitance Cint− is connected to the negative input terminal of the differential amplifier 3420. The capacitances Cint+ and Cint− have the same capacitance value.
In this case, the measurement circuit 34 may also comprise electronic switches 3402 and 3412 in order to selectively discharge the capacitances Cint+ and Cint−, e.g., as a function of a reset signal RST. In fact, the circuit of
Accordingly, in the example considered, the capacitances CS and CR are not charged directly with voltage VDD, but rather with a voltage (VDD−Vthp), where Vthp corresponds to the threshold of the input FETs of the current mirrors 3400 and 3410, i.e., the voltage ΔV at the input of the differential amplifier 3420 may be approximated with the following equation after a given number N of switching cycles:
Accordingly, a first drawback relates to the fact the output Vout is also a function of the threshold Vthp, which depends on temperature and process spread variations. Moreover, in this approach, to achieve a higher sensitivity, high voltages across the integrating capacitors Cint+ and Cint− are required. However, this situation may push the differential amplifier 3420 to a nonlinear region, and thus limits the resolution of the sensor circuit. To mitigate this second problem, the previously cited article by Forouhi, et al., also discloses an alternative approach, which is shown in
Specifically, in the example shown in
However, in this case a further current mirror 3430, e.g., implemented with n-channel FETs, is used to generate a further mirrored current iR″ by mirroring the current iR′. Specifically, in the example considered, the output of the current mirror 3400 is connected in series with a capacitance Cint. Conversely, the output of the current mirror 3430 is connected in parallel with the capacitance Cint. Accordingly, in the example considered, the capacitance Cint is indeed charged with a current ix corresponding to the difference between the currents iS′ and iR″, i.e., iX=iS′−iR″.
Accordingly, also the circuit of
Generally, the previously cited document also discloses a respective differential version of the circuit shown in
Unfortunately, the approach shown in
According to one or more embodiments, a measurement system is provided. Embodiments moreover concern a related integrated circuit and method.
As mentioned before, various embodiments of the present disclosure relate to a measurement system. In various embodiments, the measurement system includes a first capacitance and a second capacitance. The measurement system includes moreover a switching circuit configured to receive a first and a second control signal. In response to determining that the first control signal is asserted, the switching circuit connects a first terminal of the first capacitance to a first voltage and a first terminal of the second capacitance to a second voltage. Moreover, in response to determining that the second control signal is asserted, the switching circuit connects the first terminal of the first capacitance and the first terminal of the second capacitance to a reference voltage, e.g., ground.
In various embodiments, a control circuit is configured to generate the first and second control signals according to switching cycles comprising four intervals. Specifically, for a first interval, the control circuit de-asserts the first and second control signals. For a following second interval, the control circuit de-asserts the first control signal and asserts the second control signal, thereby connecting the first capacitance to the first voltage and the second capacitance to the second voltage. For a following third interval, the control circuit de-asserts the first and the second control signal. Finally, for a following fourth interval, the control circuit asserts the first control signal and de-asserts the second control signal, thereby connecting the first capacitance and the second capacitance to the reference voltage.
In various embodiments, the measurement system also includes a measurement circuit, which in turn includes a differential integrator and a comparator with hysteresis.
In various embodiments, the differential integrator includes a differential operational amplifier, a first integration capacitance and a second integration capacitance. Specifically, in various embodiments, an inverting input of the differential operational amplifier is connected to a second terminal of the first capacitance and a non-inverting input of the differential operational amplifier is connected to a second terminal of the second capacitance. A first terminal of the first integration capacitance is connected to the inverting input of the differential operational amplifier and a second terminal of the first integration capacitance is connected via a first electronic switch to a positive output terminal of the differential operational amplifier, wherein the second terminal of the first integration capacitance represents a first output node of the differential integrator. Similarly, a first terminal of the second integration capacitance is connected to the non-inverting input of the differential operational amplifier and a second terminal of the second integration capacitance is connected via a second electronic switch to a negative output terminal of the differential operational amplifier, wherein the second terminal of the second integration capacitance represents a second output node of the differential integrator. In various embodiments, the differential integrator also includes a third electronic switch connected between the inverting input of the differential operational amplifier and the positive output terminal of the operational amplifier, and a fourth electronic switch connected between the non-inverting input of the differential operational amplifier and the negative output terminal of the operational amplifier.
In various embodiments, the comparator with hysteresis is configured to, in response to determining that a voltage applied to a negative input terminal of the comparator with hysteresis exceeds a voltage applied to a positive input terminal of the comparator with hysteresis plus a hysteresis threshold, set a first output terminal of the comparator with hysteresis to high and a second output terminal of the comparator with hysteresis to low. Moreover, in various embodiments the comparator with hysteresis includes a fifth electronic switch connected between the negative input of the comparator with hysteresis and the second output terminal of the comparator with hysteresis, and a sixth electronic switch connected between the positive input of the comparator with hysteresis and the first output terminal of the comparator with hysteresis.
In various embodiments, a first decoupling capacitance is connected between the negative input of the comparator with hysteresis and the first output node of the differential integrator, and a second decoupling capacitance connected between the positive input of the comparator with hysteresis and the second output node of the differential integrator.
Specifically, the measurement system is configured to manage a normal operation phase and a reset phase.
Specifically, during the normal operation phase, the measurement system is configured to close the first electronic switch and the second electronic switch, in response to determining that the second control signal is asserted. Conversely, the measurement system is configured to open the first electronic switch and the second electronic switch in response to determining that the second control signal is de-asserted. Moreover, the measurement system is configured to close the third electronic switch and the fourth electronic switch in response to determining that the first control signal is asserted, and open the third electronic switch and the fourth electronic switch in response to determining that the first control signal is de-asserted. Thus, when the first control signal is de-asserted and the second control signal is asserted, the first integration capacitance and the second integration capacitance are connected into the feedback paths of the differential operational amplifier, thereby permitting a charge transfer from the first and second capacitances to the first and second integration capacitances. For example, the first and second capacitances have a different charge when the first voltage and the second voltage correspond to a common voltage, but the first capacitance corresponds to a sense capacitance and the second capacitance corresponds to a reference capacitance. In fact, in this case, the voltage between the first and second output nodes of the differential integrator is indicative of the difference between the capacitances of the sense capacitance and the reference capacitance. Conversely, when the first capacitance and the second capacitance have the same capacitance value, the voltage between the first and second output nodes of the differential integrator is indicative of the difference between the first voltage and the second voltage. During the normal operation phase, the comparator with hysteresis is thus operative, i.e., the fifth electronic switch and the sixth electronic switch are opened.
In various embodiments, the measurement system also monitors a reset request signal during the normal operation phase and, in response to determining that the reset request signal indicates a reset request, the measurement system starts the reset phase. For example, in various embodiments, the measurement system is configured to assert the reset request signal after a given maximum number of the switching cycles, and/or in response to determining that the first output terminal of the comparator with hysteresis is set to high and/or the second output terminal of the comparator with hysteresis is set to low.
In various embodiments, during the reset phase, the measurement system executes at least two sub-phases. Specifically, for a first reset interval, the measurement system closes the first, second, third, fourth, fifth and sixth electronic switches. Conversely, for a following second reset interval, the measurement system opens the third and fourth electronic switches and keeps closed the first, second, fifth and sixth electronic switches. Finally, at the end of second phase, the measurement system starts again the normal operation phase. Specifically, as will be described in greater detail in the following, in various embodiments, apart from resetting the integration capacitances and the comparator with hysteresis, the offsets and most of the flicker noise of the differential operational amplifier and the comparator with hysteresis may be stored to the decoupling capacitance during the first reset interval. Moreover, during the second reset interval, also the charge-injection and clock-feedthrough of the third and fourth electronic switches may be stored to the decoupling capacitance.
For example, in order to implement the described reset phase, the differential integrator may receive a first reset signal, and the third electronic switch and fourth electronic switch may be configured to be closed in response to determining that the first control signal is asserted or the first reset signal is asserted. Moreover, the comparator with hysteresis may be configured to receive a second reset signal, wherein the fifth electronic switch and the sixth electronic switch are configured to be closed in response to determining that the second reset signal is asserted. Accordingly, in this case, the measurement system may be configured to, while the control circuit asserts the second control signal, assert the first reset signal and the second reset signal for the first reset interval, and de-assert the first reset signal and assert the second reset signal for the second reset interval. For example, for this purpose the measurement system may include a delay circuit configured to generate the second reset signal by delaying the first reset signal.
The embodiments of the present disclosure will now be described with reference to the annexed plates of drawings, which are provided purely to way of non-limiting example and in which:
In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.
Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
The references used herein are provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.
In
As mentioned before, various embodiments of the present disclosure relate to a measurement system.
As will be described in greater detail in the following, in various embodiments, the voltages V1 and V2 may also correspond to the same voltage, indicated in the following as voltage VA. For example, in various embodiments, the measurement system may comprise a voltage generator (VG) 42 configured to receive a supply voltage VDD, e.g., via a pad/pin of the integrated circuit 40, and generate the voltage VA based on this supply voltage VDD.
In the embodiment considered, the measurement system has two associated capacitances C1 and C2. These capacitances are integrated in the measurement system for best matching. In general, the capacitance has two terminals T1 and T2, and the capacitance has two terminals T3 and T4.
Specifically, in various embodiments, the switching circuit 32a receives a first control signal Φ1 and a second control signal Φ2. For example, the control signal Φ1 and Φ2 may be generated by a control circuit 36a of the measurement system. Specifically, similar to the previous description, the control circuit 36a may be configured to generate the control signals Φ1 and Φ2 according to switching cycles having a duration/period TS, wherein each switching cycle TS comprises a sequence of the following four phases: a phase Δt1, wherein the signals Φ1 and Φ2 are de-asserted; a phase Δt2, wherein the signal Φ1 is de-asserted and the signal Φ2 is asserted; a phase Δt3, wherein the signals Φ1 and Φ2 are de-asserted; and a phase Δt4, wherein the signal Φ1 is asserted and the signal Φ2 is de-asserted.
For example, in various embodiments, the switching circuit 32a is configured to:
Accordingly, in various embodiments, the switching circuit 32a is configured to apply the reference voltage Vref, or the voltages V1 and V2, to the terminals T1 and T3 of the capacitances C1 and C2, respectively.
Accordingly, in various embodiments, a measurement circuit 34a is configured to monitor a current i1 flowing through the capacitance C1 and a current i2 flowing through the capacitance C2.
Specifically, in the embodiment considered, the measurement circuit 34a is implemented with a switched capacitor (SC) differential integrator. Specifically, in the embodiment considered, the differential integrator comprises a differential operational amplifier 3440, wherein the inverting/negative input terminal of the operational amplifier 3440 is connected (e.g., directly) to the terminal T2 of the capacitance C1, and the non-inverting/positive input terminal of the operational amplifier 3440 is connected (e.g., directly) to the terminal T4 of the capacitance C2. Specifically, in order to implement a differential integrator configured to integrate the difference Δi between the currents i1 and i2 during the discharge phase, i.e., when the signal Φ2 is asserted, the differential integrator comprises:
Specifically, the electronic switches 3448 and 3450 are driven by the signal Φ2, and are closed when the signal Φ2 is asserted. Accordingly, in the embodiment considered, the electronic switches 3448 and 3450 are closed when the signal Φ2 is asserted, i.e., during the discharge phase, thereby connecting the integration capacitances CI1 and CI2 into the feedback paths of the operation amplifier 3440. In various embodiments, the first and second integration capacitance CI1 and CI2 have the same capacitance CI. For example, the capacitances CI1 and CI2 may be implemented with internal capacitors for best matching with the capacitances C1 and C2.
Moreover, in the embodiment considered, the current path of an electronic switch 3452 is connected (e.g., directly) between the inverting/negative input terminal of the operational amplifier 3440 and the positive output terminal of the operational amplifier 3440, and the current path of an electronic switch 3454 is connected (e.g., directly) between the non-inverting/positive input terminal of the operational amplifier 3440 and the negative output terminal of the operational amplifier 3440. Specifically, the electronic switches 3452 and 3454 are driven by the signal Φ1, and are closed when the signal Φ1 is asserted. Accordingly, the electronic switches 3452 and 3454 are closed when the signal Φ1 is asserted, i.e., during the charge phase, thereby short-circuiting the feedback paths of the operation amplifier 3440.
As schematically shown in
Accordingly, when the signal Φ1 is asserted, the input terminals of the operational amplifier 3440 are set to the common mode voltage VCM, which permits charging of the capacitances C1 and C2 via the voltages V1 and V2. Conversely, when the signal Φ2 is asserted, the integration capacitances CI1 and CI2 are connected to the operational amplifier 3440 and the previously charged capacitances C1 and C2 discharge to the reference voltage Vref/ground GND. Specifically, the charge applied to the capacitances C1 and C2 is different, e.g., when: the voltages V1 and V2 have the same value, e.g., VA, but the capacitances C1 and C2 are different, which thus permits monitoring of the difference between the capacitances C1 and C2, or the capacitances C1 and C2 have the same value, but the voltages V1 and V2 are different, which thus permits monitoring of the difference between the voltages V1 and V2.
For example,
Specifically, in
For example, the switching circuit 32a of
For example, when the electronic switches M1 and M2 are implemented with p-channel FETs, the switches M1 and M2 are indeed closed when the signal Φ1 is set to low. Thus, when the control circuit 36a is configured to assert the signal Φ1 by setting signal Φ1 to high, the inverted signal
Accordingly, in the embodiment shown in
Conversely, in
Accordingly, also in this case two half-bridges may be used. For example, in the embodiment considered, the current path of a first electronic switch M4, such as a transistor, such as an n-channel FET, such as an n-channel MOSFET, is connected (e.g., directly) between the terminal T1 and the reference voltage Vref/ground GND. Moreover, the current path of a second electronic switch M2, such as a transistor, such as an p-channel Field-effect transistor (FET), such as an p-channel MOSFET, is connected (e.g., directly) between the terminal T1 and the voltage Vin+. Similarly, the current path of a third electronic switch M3, such as a transistor, such as an n-channel FET, such as an n-channel MOSFET, is connected (e.g., directly) between the terminal T3 and the reference voltage Vref/ground GND. Moreover, the current path of a fourth electronic switch M1, such as a transistor, such as an p-channel Field-effect transistor (FET), such as an p-channel MOSFET, is connected (e.g., directly) between the terminal T3 and the voltage Vin−.
Accordingly, the embodiments shown in
For example, when using the measurement circuit 34a of
ΔQ=(CS−CR)VA=ΔC VA (3)
Accordingly, assuming that the capacitances CI1 and CI2 have the same value CI and when repeating a given number N of switching cycles TS, the differential output voltage VO,AMP of the operational amplifier 3440 during the intervals when the signal Φ2 is asserted is given by:
Conversely, when using the measurement circuit 34a of
ΔQ=(Vin+−Vin−)CS=ΔVinCS (5)
Accordingly, assuming that the capacitances CI1 and CI2 have the same value CI and when repeating a given number N of switching cycles TS, the differential output voltage VO,AMP of the operational amplifier 3440 during the intervals when the signal Φ2 is asserted is given by:
Specifically, when opening the electronic switches 3448 and 3450 once the signal Φ2 is de-asserted, the differential voltage VO,AMP is maintained and stored at the intermediate nodes between the integration capacitances (CI1 or CI2) and the electronic switch (3448 or 3450). Accordingly, in the embodiment considered, the second terminal of the integration capacitance CI1, i.e., the intermediate node between the capacitance CI1 and the electronic switch 3448, represents a first output terminal OUT+ of the integrator circuit, and the second terminal of the integration capacitance CI2, i.e., the intermediate node between the capacitance CI2 and the electronic switch 3450, represents a second output terminal OUT− of the integrator circuit, wherein the output terminals OUT+ and OUT− provide a differential voltage VO, e.g., corresponding to the previously indicated voltages VO,AMP.
In various embodiments, the measurement circuit 34a may be configured to assert a signal S when the voltage VO exceeds a reference threshold within a given monitoring interval, which comprises a given number N of switching/integration cycles TS, thereby indicating that current difference Δi=i1−i2 exceeds a given threshold value, which in turn may indicate that the capacitance difference ΔC (e.g.,
Specifically, in various embodiments, the signal S is generated via a differential comparator with hysteresis 3446 configured to assert the signal S when the voltage VO exceeds the hysteresis threshold of the comparator 3446.
In general, such a comparator with hysteresis 3446 comprises two input terminals for receiving a differential voltage ΔVCMP and two output terminals form providing signals OUT and OUTN, wherein the comparator 3446 is configured to set the signal OUT to high and the signal OUTN to low in response to determining that the voltage at the negative input terminal exceeds the voltage at the positive input terminal plus a first hysteresis voltage VH1 of the comparator. Similarly, the comparator 3446 is configured to set the signal OUT to low and the signal OUTN to high in response to determining that the voltage at the negative input terminal falls below the voltage at the positive input terminal minus a second hysteresis voltage VH2. In various embodiments, the first hysteresis voltage VH1 and the second hysteresis voltage VH2 have the same absolute value VH.
Accordingly, in the embodiment considered, the signal S may correspond, e.g., to the signal OUT. Conversely, in the embodiment considered, the measurement circuit 34a comprises a first inverter 3460 configured to generate the signal S by inverting the signal OUTN. In this case, the measurement circuit 34a also comprises a second inverter 3462 configured to generate a signal SN by inverting the signal OUT. Specifically, these inverters 3460 and 3462 are useful in case the signals S and/or SN are used to drive other circuits, and may also be useful in order to balance the output terminals of the comparator with hysteresis 3446. In general, the inverters 3460 and 3462 may also be replaced with a more complex driver stage, e.g., comprising a cascade of inverters and/or other logic gates.
In the embodiment considered, the input terminals of the comparator 3446 are not connected directly to the nodes OUT+ and OUT−, but one of the input terminals of the comparator 3446, e.g., the negative input terminal, is connected (e.g., directly) via a first capacitance/capacitor CDEC1 to the node OUT+ and the other input terminal of the comparator 3446, e.g., the positive input terminal, is connected (e.g., directly) via a second capacitance/capacitor CDEC2 to the node OUT−. These capacitances CDEC1 and CDEC2 have the same capacitance value CDEC.
On the one hand, these capacitances CDEC1 and CDEC2 represent decoupling capacitances between the integrator and the comparator, which thus transfer the variations of the voltages at the nodes OUT+ and OUT− to the input terminals of the comparator. However, in various embodiments, the offsets and most of the flicker noise of the operational amplifier 3440 and the comparator with hysteresis 3446 may be also stored to the capacitances CDEC1 and CDEC2 during a reset phase whereby these voltages are then cancelled during the subsequent sensing operation.
Specifically, in various embodiments, to order to start a new measurement cycle, an asynchronous reset is performed once the signal S is asserted, i.e., the signal S corresponds to a reset signal Reset1.
In general, the integrator 3440 may be reset by short-circuiting the integration capacitances CI1 and CI2. For example, in
Accordingly, as shown in
In various embodiments, the comparator with hysteresis 3446 is also reset during the reset phase. For example, in various embodiments, the comparator 3446 is reset by closing an electronic switch 3464 configured to short-circuit the output terminal OUTN and the negative input terminal of the comparator 3446 and an electronic switch 3466 configured to short-circuit the output terminal OUT and the positive input terminal of the comparator 3446.
In various embodiments, the electronic switches 3464 and 3466 are closed when the signal Reset1 is asserted. Conversely, in the embodiment shown in
Accordingly, as shown in
Accordingly, in the embodiment considered, the offsets and most of the flicker noise of the operational amplifier 3440 and the comparator with hysteresis 3446 are stored to the capacitances CDEC1 and CDEC2 during the interval between the instants t1 and t2. Conversely, when using the optional delay tD, the charge-injection and clock-feedthrough of the switches 3452 and 3454 may also be stored to the capacitances CDEC1 and CDEC2.
In this respect, it has been observed that the remaining error may in this way be reduced to the mismatch of the charge-injection and clock-feedthrough of the switches 3464 and 3466 driven by the reset signal Reset2, i.e., Verror=ΔQSW/CDEC, wherein the voltage Verror is usually in the micro-Volt range, and usually can be neglected or anyway absorbed by the comparator hysteresis.
In this respect, it has been observed that a smaller threshold voltage VH1 permits a faster detection, e.g., of the sample passing over the electrodes 100 and 102 forming the capacitance CS. However, such a smaller threshold voltage VH1 may imply thermal noise and the charge injection/clock feedthrough mismatch of the switches 3464 and 3466 driven by the signal Reset2 on the measurement.
Additionally, or alternatively, to the asynchronous reset triggered by the signal S, the reset of the measurement circuit 34a may also be managed based on a timeout, which is used to trigger similar reset phases of the integrator and the comparator. In fact, in line with the previous description, in various embodiments, the measurement system comprises a reset circuit configured to execute, in response to a reset request signal indicating a reset request, such as a rising edge of the signal S, a signal indicating that a given maximum number N of switching cycles have been executed, etc., the following steps in sequence:
In various embodiments, in order to absorb the differential charge injection of the feedback switches 3448 and 3450 driven by Φ2 in presence of a differential signal at the output terminals of the operational amplifier 3440, these switches may be equipped with dummy switches and/or capacitor CX is added.
For example, in the embodiment shown in
Conversely,
Specifically, in the embodiment considered, a first terminal of a respective integration capacitance CI1 or CI2, indicated generically as CI in
Specifically, in the embodiment considered, each electronic switch 3448/3450 is implemented with a series connection of two FETs Q1 and Q2, such as n-channel FETs. Specifically, the first FET Q1 is driven via the signal Φ2. Conversely, the second FET Q2 is a dummy switch, wherein the source and drain terminals of the FET Q2 are short-circuited. Moreover, the gate terminal of the FET Q2 is driven via a signal being asserted when the signal Φ2 is de-asserted, such as the inverted version of the signal Φ2 or preferably the signal Φ1. Preferably, the FET Q1 has a given size ratio W1/L1 (channel width/length), and the FET has a ratio W2/L2 corresponding to 0.5 W1/L1. Generally, such dummy switches Q2 for reducing the charge injection are well-known.
Accordingly the solutions described in the foregoing have the advantage that the voltage VO,AMP and similarly VO is not sensitive to process parameters, such as the MOS voltage threshold of the current mirrors of the prior-art solution. Moreover, the voltages V1 and V2 may be external or internal voltages. For example, the voltage VA may correspond to a supply voltage VDD of the integrated circuit 40 or a reference voltage provided by the voltage reference 42. Specifically, when using an internal voltage reference 42 configured to generate the voltage VA, the threshold value VH1 (and optionally VH2) may also be proportional the voltage VA, thereby permitting a tracking of variation of the voltage VA variations. Conversely, a higher sensitivity can be achieved when using the (greater) supply voltage VDD.
For example, in various embodiment, the integration capacitances CI1 and CI2 have a capacitance value of 0.1 pF, the period of a switching cycle TS is 1 μs, the voltage VA has a value of 2.5 V, and the comparison threshold VH1 (and optionally VH2) is 5 mV. For example, assuming a capacitance difference ΔC of 10 aF, the voltage VO reaches the comparison threshold VH1 after N=20 switching cycles TS. Thus, in this example, the measurement system is able to detect the presence or absence of a sample, such as a sample with small radius crossing the plates of capacitor CS, producing a change ΔC of 10 aF in approximately 20 μs. Conversely, assuming a capacitance difference ΔC of 40 aF, the voltage VO reaches the comparison threshold VH1 after N=5 switching cycles TS, i.e., the measurement system is able to detect the presence or absence of a sample producing a change ΔC of 40 aF in approximately 5 μs.
In general, the measurement circuit 34a disclosed in the foregoing may also be used with a plurality of capacitive sensors. For example, such capacitive sensors may form part of a capacitive touch sensor, such as a touch screen.
For example,
Specifically, similar to
Specifically, in order to select a given channel CH, the control terminal of the electronic switches M21, M41, . . . , M2M, M4M are selectively connected to the control signals Φ1 and Φ2. For example, assuming that the high-side electronic switches M21, . . . , M2M are p-channel FETs and the low-side electronic switches M41, . . . , M4M are n-channel FETs, a given channel CH may be:
For example, for this purpose, each high-side electronic switch M21, . . . , M2M has an associated respective electronic switch SW11, SW12, . . . , SW1M configured to connect the respective gate terminal to the high logic level or the signal
While this embodiment permits use of a single reference capacitance CR, a large loading is applied to the node T2 (e.g., the negative input terminal of the operational amplifier 3440), and a strong capacitive asymmetry is generated between the nodes T2 and T4 (the input terminals of the amplifier 3440).
In the embodiment considered, similar to
Specifically, in the embodiment considered, the various half-bridges are configured to connect the respective intermediate node to the voltage VA when the signal
Specifically, similar to
In the embodiment considered, similar to
Thus, compared to
Specifically, a reference capacitance CR and a sense capacitance CS are again connected to a respective half-bridge. Specifically, a first terminal of each sense capacitance CS1, CS2, . . . , CSM is connected (e.g., directly) to the intermediate node of the respective half-bridge formed by two electronic switches, i.e., half-bridges formed by two electronic switches M21 and M41, two electronic switches M22 and M42, etc., and the second terminal of each sense capacitance CS1, CS2, . . . , CSM is connected (e.g., directly) via a respective electronic switch SW11, SW12, . . . , SW1M to the node T2. Moreover, a first terminal of each reference capacitance CR1, CR2, . . . , CRM is connected (e.g., directly) to the intermediate node of the respective half-bridge and the second terminal of each reference capacitance CR1, CR2, . . . , CRM is connected (e.g., directly) via a respective electronic switch SW21, SW22, . . . , SW2M to the node T2.
Thus, the electronic switches SW11, SW12, . . . , SW1M and SW21, SW22, . . . , SW2M may be driven via respective control signals in order to connect a single sense capacitance CS1, CS2, . . . , CSM and a single reference capacitance CR1, CR2, . . . , CRM to the respective half-bridge. For example, the control signals may be generated by the control circuit 36a or the processing circuit 44 (not shown in
In general, the embodiments shown in
Accordingly, the measurement system 34a disclosed herein may be used to monitor a different charge injected into two capacitances C1 and C2, which in turn may be indicative of a different capacitance value of the two capacitances C1 and C2 or a different voltage V1 and V2 used to charge the capacitances C1 and C2.
For example, in the context of a capacitive sensor, the measurement system may be used to detect the presence of a sample material across an integrated capacitor in a very accurate way. In this case, the sensitivity of the measurement system is mainly determined by the mismatch between the reference and the sensing capacitors.
Compared to the prior art solutions, the detection is very fast. In this respect, the asynchronous detection based on an asynchronous reset via the signal S permits further increase of the speed of the system.
Finally, several simple and low-cost multiplexing solutions available.
Of course, without prejudice to the principle of this disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102022000019113 | Sep 2022 | IT | national |
