1. Technical Field
The disclosure relates to an apparatus. Particularly, the disclosure relates to a measuring apparatus.
2. Description of Related Art
As electronic system products are gradually miniaturized, various devices originally crowded on a circuit board are gradually packaged in a single package structure, and are further integrated to a single chip of heterogeneous integration. Though, during the integration process, a multi-function and heterogeneous single chip structure requires different manufacturing processes in accordance with different materials. However, considerable time and investment have to be spent with respect to such situation. Facing to a current market pattern of short product cycles and low-cost requirements, development of the system integration heterogeneous chip is rather uneconomic. Therefore, to integrate chips of different functions in a same package structure becomes a worthy development direction.
Current techniques for integrating different chips into the same package structure include a system on chip (SoC) technique and a system in package (SiP) technique, etc. In these techniques, a plurality of chips is generally packaged as a package device, in which the chips can be evenly distributed on a substrate, or the chips can be directly stacked. Moreover, another solution is to stack different chips into a whole group of chips according to a bump stacking method (which is usually performed in collaboration with wafer thinning).
In the bump stacking structure, since multiple layers of the chips are stacked through bump bonding, the complexity of the structure is increased. After the chips are stacked through the bump bonding, to observe a thermal stress/strain state of each chip and each bump caused by thermal expansion coefficient differences of different chips, or mechanical stress/strain caused by external force or gravity, new measurement methods have to be developed to effectively and promptly obtain the stress/strain states of the chips, so as to use such real-time information to accelerate design and process improvement to enhance competitiveness.
The disclosure is directed to a measuring apparatus, which can measure stresses of chips under various temperatures.
The disclosure provides a measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater is disposed on the first surface and is electrically connected to the first circuit layer. The first stress sensor is disposed on the first surface and is electrically connected to the first circuit layer. The second circuit layer is disposed on the second surface.
According to the above descriptions, the measuring apparatus can use the heater to simulate various operating temperatures, so as to measure thermal resistances of the chip under various operating temperatures.
In order to make the aforementioned and other features and advantages of the disclosure comprehensible, several exemplary embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
The analysis module 104 can be a hardware measurement device or an analysis software, or can even be a single chip, which is not limited by the disclosure. The analysis module 104 may analyse the internal stress/strain variation of the IC device 102 according to a following principal.
The disclosure provides a testing apparatus for measuring a thermal resistance and a stress/strain value of a three-dimensional stacked chip structure containing through silicon vias, by which not only a strain value of a chip of each layer can be directly measured, a stress distribution of the chip of each layer can also be indirectly obtained. Generally, a basic principle of strain gauge measurement is to use a length variation of a conductor or a semiconductor material to produce a tiny variation of a resistance thereof. As shown in
Where, R is a resistance of the internal chip of the IC device 102, and ΔR is a variation amount of the resistance. Moreover, A′ij is a transition matrix, A′ij=A′ij(πkl,φ,[akl]), α1,α2 are thermal expansion coefficients of the material, πkl is a piezoresistive constant of the material, [akl] is a coordinate axis transition matrix, and φ is an angle between the piezoresistive measuring device and the coordinate axis, as that shown in
According to the above equation (1), it is known that as long as the resistance and the variation amount of the resistance of the internal chip of the IC device 102 of
Regarding the piezoresistive measuring device made of an isotropic homogeneous piezoresistive material (for example, metal), if the piezoresistive measuring device is parallel to the coordinate axis (φ=0°), the equation (1) can be simplified as:
According to the equation (2), it is known that if the piezoresistive constant of the material is 1000×10−12 (1/Pa), the thermal expansion coefficient of the material is 1000×10−6 (1/° C.), and in case of a constant temperature (ΔT=0), if the piezoresistive variation amount is 0.1%, the stress value is about 106 Pa (i.e. 1 MPa) according to a reverse calculation.
Moreover, the testing apparatus of the disclosure may use a heater to simulate the temperature of the chip, so that the principle that the temperature variation of the material causes a tiny variation of the resistance of the material can be used to first obtain a temperature coefficient of resistance (TCR) of the testing apparatus itself before the stress/strain is actually measured, so as to obtain a correct resistance of the apparatus.
The temperature dependence of conductors can be described by the approximation below.
ρ0 just corresponds to the specific resistance temperature coefficient at a specified reference value (normally T=0° C.).
A positive temperature coefficient refers to materials that experience an increase in electrical resistance when their temperature is raised. Materials which have useful engineering applications usually show a relatively rapid increase with temperature, i.e. a higher coefficient. The higher the coefficient, the greater an increase in electrical resistance for a given temperature increase.
Several exemplary embodiments are provided below to describe an internal structure of the measuring apparatus of the disclosure.
By using the heater 1210, the measuring apparatus 1000 can measure a temperature coefficient of resistance (TCR) curve of the chip 1100 under various temperatures, and a basic principle thereof is to vary a temperature of a conductor or a semiconductor material, so that a resistance thereof is slightly varied, and a TCR of the conductor is first calibrated before an actual measurement, so as to facilitate measuring the temperature of the chip and converting it to a thermal resistance of the chip.
Here, the circuit layer 1200 is a general term of all circuits disposed on the surface 1120, and the circuit layer 1200 may include a plurality of independent circuits. The heater 1210 obtains an operation power through the circuit layer 1200, and the stress sensor 1220 outputs a sensing signal through the circuit layer 1200. The circuit layer 1230 is a general term of all circuits disposed on the surface 1130, and the circuit layer 1230 may include a plurality of independent circuits. The heater 1210 is, for example, formed by a circuit, which may provide a heating effect due to its own resistance. The stress sensor 1220 can be a commonly used strain gauge or other types of stress sensors in the market, and the commonly used strain gauge in the market is also formed by a circuit with a special layout pattern, so as to facilitate obtaining stress information of various directions.
The measuring apparatus 1000 of the present exemplary embodiment may further include a plurality of conductor devices 1240 disposed in the through silicon vias 1110. A number of the conductor devices 1240 is determined according to a number of the through silicon vias 1110. The conductor devices 1240 can be only connected to the circuit layer 1200, or can be only connected to the circuit layer 1230, or can be simultaneously connected to both of the circuit layers 1200 and 1230, electrically. When the upper and lower surfaces of the chip 1100 have other devices disposed thereon, the conductor devices 1240 can be used to only connect the other devices on the upper and lower surfaces of the chip 1100 without connecting the circuit layers 1200 and 1230. The measuring apparatus 1000 of the present exemplary embodiment may further include a heater 1250, which is disposed on the surface 1130 and is electrically connected to the circuit layer 1230, and a function of the heater 1250 is similar to that of the heater 1210. The measuring apparatus 1000 of the present exemplary embodiment may further include a stress sensor 1260, which is disposed on the surface 1130 and is electrically connected to the circuit layer 1230, and a function of the stress sensor 1260 is similar to that of the stress sensor 1220.
The stress sensors 1220 and 1260 may sense resistances of the upper surface 1120 of the chip 1100, and generate corresponding sensing signals, for example, the sensing signals S1 in
In the present exemplary embodiment, since the stress sensors 1220 and 1260 can be respectively disposed at corresponding positions on the upper and lower surfaces 1120 and 1130 of the chip 1100, not only stresses/strains of the upper surface 1120 and the lower surface 1130 of the chip 1100 can be sensed, stresses/strains of the chip 1100 in three-dimensional directions can also be analysed.
A Pythagorean theorem can be used to obtain a length of z2, and a mathematic equation thereof is as follows:
z2=√{square root over (z12+(u1−u2)2)} (2)
An equivalent geometric figure thereof is as that shown in
A material of the conductor device 1240 can be a piezoelectric material, and the material of the conductor devices 1240 can also be a polysilicon material or silicon doped with phosphorus. As described above, the stress sensor 1220 can measure stresses/strains of the chip 1100 in two-dimensional directions. By using the stress sensors 1220 and 1260, stresses/strains of the chip 1100 in three-dimensional directions can be further measured. Moreover, by measuring a resistance variation of the conductor device 1240, a stress/strain of the chip 1100 in a thickness direction can be obtained. Since the conductor device 1240 directly passes through the internal of the chip 1100, the stress/strain of the chip 1100 in the thickness direction can be accurately measured. In addition, when the conductor device 1240 is used for measuring the stress/strain, even if the stress sensor 1220 is not used, the stresses/strains of the chip 1100 in the three-dimensional directions can still be measured.
In summary, in the aforementioned exemplary embodiments, the sensors are used to measure resistances of the chip when the chip is deformed, and accordingly generate the sensing signals. The sensing signals can be transmitted to the output terminal of the substrate through the conductor devices and the bumps. In this way, the stresses/strains of the chip can be analysed and calculated according to the sensing signals.
Moreover, since the sensing signals are transmitted through the conductor devices and the bumps, it is unnecessary to transmit the sensing signals through an additional wire bonding approach, so that allocation of the sensors can be more flexible. Further, since allocation of the sensors is more flexible, the stresses/strains of the chip in the three-dimensional directions can be measured.
Moreover, the measuring apparatus of the disclosure may use heaters to simulate various operating temperatures, and a TCR of the conductor is first calibrated before an actual measurement, so as to facilitate measuring the temperature of the chip and converting it to a thermal resistance of the chip.
Since the measuring apparatus of the disclosure has the through silicon vias, when a temperature and a stress/strain variation of the upper surface of the chip are required to be measured, the corresponding signals can be directly transmitted to the pads on the substrate through the through silicon vias without using a wire bonding process to transmit the signals of the upper surface of the chip to the substrate. Therefore, not only the temperatures and stress/strain variations of the upper and lower surfaces of any layer of the chip can be obtained, the signal variation in internal of each chip can also be directly obtain. The through silicon vias of the disclosure can also be used to measure a stress/strain of the chip in a thickness direction, so as to measure the stresses/strains of the chip in the three-dimensional directions in collaboration with the sensor 1220.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.
This application claims the priority benefit of U.S. provisional application Ser. No. 61/356,047, filed on Jun. 18, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
Number | Name | Date | Kind |
---|---|---|---|
6184773 | Bonne et al. | Feb 2001 | B1 |
6825539 | Tai et al. | Nov 2004 | B2 |
6877385 | Fang et al. | Apr 2005 | B2 |
6910384 | Tomka et al. | Jun 2005 | B2 |
7066031 | Zdeblick et al. | Jun 2006 | B2 |
7357035 | Liu et al. | Apr 2008 | B2 |
7553681 | Raravikar et al. | Jun 2009 | B2 |
7674638 | Okudo et al. | Mar 2010 | B2 |
20040201095 | Palmer et al. | Oct 2004 | A1 |
20090152656 | Okudo et al. | Jun 2009 | A1 |
20090267165 | Okudo et al. | Oct 2009 | A1 |
20100078753 | Mehregany et al. | Apr 2010 | A1 |
20100230807 | Bronner et al. | Sep 2010 | A1 |
Number | Date | Country |
---|---|---|
2000174416 | Jun 2000 | JP |
201017850 | May 2010 | TW |
Entry |
---|
Xiaowu Zhang et al., “Application of piezoresistive stress sensors in ultra thin device handling and characterization”, Sensors and Actuators A: Physical, Nov. 2009, p. 2-7. |
Jeffrey C. Suhling et al., “Measurement of backside flip chip die stress using Piezoresistive test die”, International Symposium on Microelectronics, Oct. 1999, p. 298-303. |
Jeffrey C. Suhling et al., “Silicon piezoresistive stress sensors and their application in electronic packaging”, IEEE Sensors Journal, Jun. 2001, p. 14-29. |
“First Office Action of China Counterpart Application”, issued on Feb. 17, 2013, p. 1-5. |
Number | Date | Country | |
---|---|---|---|
20110309357 A1 | Dec 2011 | US |
Number | Date | Country | |
---|---|---|---|
61356047 | Jun 2010 | US |