1. Field
The disclosed concept pertains generally to power electronic devices, such as multilevel power converters and, more particularly, to multilevel inverters and multilevel drives.
2. Background Information
A multilevel power inverter is a power electronic device that is structured to produce alternating current (AC) waveforms from a direct current (DC) input voltage. Multilevel power inverters are used in a wide variety of applications, such as, without limitation, variable speed motor drives and as an interface between a high voltage DC transmission line and an AC transmission line.
The general concept behind a multilevel power inverter is to use a number of power semiconductor switches coupled to a number of lower level DC voltage sources to perform power conversion by synthesizing a staircase voltage waveform. A number of different topologies for implementing a multilevel power inverter are well known, including, but not limited to, a neutral point clamped (NPC) topology, a flying capacitor (FC) topology, and an H-bridge topology. There is also a neutral point piloted (NPP) topology as disclosed herein.
As is conventional, a bank of capacitors (a “DC link”) coupled to one or more DC voltage inputs is often used to provide multiple DC voltage sources employed for operation of a multilevel power inverter. For example, it is known to use such a DC link comprising a bank of capacitors in the NPC and FC topologies.
A conventional layout for a multilevel NPC power converter or a multilevel NPP power converter leads to a relatively large number of crossing electrical connections and, thus, a relatively very complicated electrical bus structure. A complicated layered buswork can be cost prohibitive in medium voltage equipment. In low voltage power converters, circuit layout complexity also adds cost.
It is known to employ relatively simpler topologies or relatively costly laminated buswork containing relatively many layers of insulators and conductors. In low voltage equipment, for example, a relatively highly complex interconnected circuit often leads to multilayer printed circuit boards (PCBs).
Embodiments of the disclosed concept are spatial (e.g., split) mechanical arrangements of a multilevel power converter circuit (e.g., without limitation, a diode-clamped multilevel inverter (DCMLI); a multilevel neutral point clamp (MLNPC) inverter; a three-level neutral point clamp inverter; a four-level neutral point clamp inverter (e.g., a four-level NPC); a five-level neutral point clamp inverter (e.g., a five-level NPC); a multilevel neutral point piloted (NPP) anti-parallel inverter; a multilevel neutral point piloted inverter; a three-level neutral point piloted inverter; a four-level neutral point piloted inverter; a five-level neutral point piloted inverter) to enable a relatively low cost single plane construction of each half or both halves of a single phase-leg.
In accordance with one aspect of the disclosed concept, a mechanical arrangement of a multilevel power converter circuit comprises: a power converter comprising: a first portion comprising a plurality of first control inputs, at least three direct current voltage inputs, and an alternating current voltage output; and a second portion comprising a plurality of second control inputs, the at least three direct current voltage inputs and the alternating current voltage output, the second portion being split apart from the first portion, wherein the power converter has at least three levels corresponding to the at least three direct current voltage inputs.
In accordance with another aspect of the disclosed concept, a mechanical arrangement of a multilevel power converter circuit comprises: a power converter comprising: an alternating current voltage output; a first portion comprising at least three direct current voltage inputs and an output to the alternating current voltage output providing a positive direction of current flow to the alternating current voltage output; and a second portion comprising the at least three direct current voltage inputs and an output to the alternating current voltage output providing an opposite negative direction of current flow from the alternating current voltage output, wherein the power converter has at least three levels corresponding to the at least three direct current voltage inputs.
A full understanding of the disclosed concept can be gained from the following description of the preferred embodiments when read in conjunction with the accompanying drawings in which:
As employed herein, the term “number” shall mean one or an integer greater than one (i.e., a plurality).
As employed herein, the term “low voltage” shall mean any voltage that is less than about 600 VRMS.
As employed herein, the term “medium voltage” shall mean any voltage greater than a low voltage and in the range from about 600 VRMS to about 38 kVRMS.
As employed herein, the term “high voltage” shall mean any voltage greater than a medium voltage.
As employed herein, the term “inverter” shall mean an electrical device that converts direct current (DC) to alternating current (AC). The converted AC may be at any suitable voltage and frequency.
For example and without limitation, in a conventional two-level inverter for three AC phases, a two-level DC bus voltage is applied across a six-switch inverter bridge which produces a two-level PWM voltage output. The two levels of the DC bus constitute a positive bus and a negative bus. The six switches are divided into three branches with two switches each. A controller controls each switch via the control terminals of the switch. The top switch of each branch is connected to the positive bus and the bottom switch of each branch is tied to the negative bus.
As another non-limiting example, an inverter may optionally include an active front end where, for example, a three-phase AC to DC rectifier rectifies AC to DC for subsequent DC to AC conversion by the inverter. With an active front end, generally all of the DC input voltage points of the inverter are typically shared by multiple inverters, not just the outer two DC input voltage points, although that is a possible alternative.
In comparison to the two-level inverter, in a three-level inverter for three-phases, the DC bus has three voltage levels (relatively labeled positive, neutral and negative), and the inverter bridge has, for example and without limitation, twelve or eighteen switches.
As employed herein, the term “multilevel” (e.g., without limitation, three-level; four-level; five-level; six-level; greater than six levels) shall mean an inverter or an inverter phase-leg capable of creating three or more voltage levels at each terminal point typically with respect to a DC link voltage point somewhere in the inverter.
For example and without limitation, for a four-level inverter phase-leg, the DC voltage of a voltage intermediate circuit is subdivided into four DC potential levels. As non-limiting examples, a conventional NPC phase-leg has six IGBTs and a minimum of four diodes per phase-leg, so the minimum number of switches for a three-phase inverter is 18 or 30 depending on whether the diodes are counted. An NPP phase-leg, on the other hand, has basically a single ideal switch per level, per phase, so there is a minimum of twelve switches for a four-level NPP inverter. However, the ideal switch implementation is not believed to be realizable with current technology, so this number is generally much higher. A corresponding four-level inverter for three phases has, for example and without limitation, eighteen, thirty, thirty six or seventy two switches (e.g., without limitation, if a common voltage rating was desired for all switches, although with a variety of voltage ratings, this would drop to 36 switches for an NPC inverter and 72 switches for an NPP inverter.
Similarly, for example and without limitation, for a five-level inverter phase-leg, the DC voltage of a voltage intermediate circuit is subdivided into five DC potential levels. A corresponding inverter for three phases has, for example and without limitation, forty two or sixty switches. Again, an NPP phase-leg has basically a single ideal switch per level, per phase, so there is a minimum of fifteen switches for a five-level NPP inverter. However, the ideal switch implementation is not believed to be realizable with current technology, so this number is generally much higher.
As employed herein, the term “power converter circuit” shall mean a multilevel inverter. Non-limiting examples of multilevel inverters include a diode-clamped multilevel inverter (DCMLI); a multilevel neutral point clamp (MLNPC) inverter; a three-level neutral point clamp inverter; a four-level neutral point clamp inverter (e.g., a four-level NPC); a five-level neutral point clamp inverter (e.g., a five-level NPC); a multilevel neutral point piloted (NPP) anti-parallel inverter; a multilevel neutral point piloted inverter; a three-level neutral point piloted inverter; a four-level neutral point piloted inverter; and a five-level neutral point piloted inverter.
DCMLI and MLNPC generally refer to the same power converter circuit. A three-level NPC, a four-level NPC and a five-level NPC, for example, are versions of an MLNPC or DCMLI.
As employed herein, the statement that two or more parts are “connected” or “coupled” together shall mean that the parts are joined together either directly or joined through one or more intermediate parts. Further, as employed herein, the statement that two or more parts are “attached” shall mean that the parts are joined together directly.
There are a wide variety of ways to provide the mechanical arrangement (e.g., without limitation, physical circuit layout) in accordance with embodiments of the disclosed concept. One non-limiting example is a single-layer printed circuit board (PCB) layout for low voltage operation. This can, for example and without limitation, employ air-cooled heat sinks, employ individual liquid-cooled heat sinks, or be immersed in a liquid coolant. Although not part of the disclosed concept, there would also be an accompanying control circuit that may or may not be part of the same PCB or power converter circuit. Typically, each phase of the power converter will employ an individual PCB. For example and without limitation, the control circuit can be disposed in an enclosure proximate the front of the assembly with or without AC current sensors, or can be disposed intermediate two PCBs. Alternatively, a DC voltage measurement board can be disposed intermediate two PCBs.
As another non-limiting example, the mechanical arrangement employs dual PCBs with each half of the phase-leg being folded. The control circuit can then either be sandwiched therebetween, or can be mechanically to the side of the main power circuits. This can, for example and without limitation, employ either individual heat sinks with air or liquid cooling, or immersion cooling.
Example PCB layouts of the power converter can typically employ PCB-mount IGBTs or MOSFETs in packages such as, for example and without limitation, TO-220 or TO-247. The power converter can also be created with surface-mount devices, such as, for example and without limitation, a DPAK package that employs the PCB as a heat sink. Other possible embodiments include conventional flat-pack IGBTs on a single or multiple relatively large heat sinks.
Another example embodiment is a medium voltage air-cooled power converter made from a folded two-PCB layout with a third control circuit PCB sandwiched integrally between the other two PCBs with an insulation layer and air between each PCB.
Example applications for the disclosed concept include, for example and without limitation, medium voltage motor drives, low voltage motor drives, grid-interface converters for alternative energy, such as wind and solar converters, as well as any power converter that creates an AC voltage.
An alternate form of the conventional electrical layout of the five-level NPC topology 2 of
In the disclosed mechanical arrangement 110 of
In the disclosed mechanical arrangement 110 of
Also referring to
Additionally, as shown in
As shown in
In the example of
Referring again to
The first half-leg 146 includes a first number (e.g., without limitation, four in this example, although 16 individual capacitors to form C16, C15, C14, C13 are shown in
If the mechanical arrangement 110 of
Referring to
An important aspect of the disclosed concept is a redrawn mechanical arrangement 210 (
Additionally, the single plane version of the layout can be divided down the capacitor axis 280 such that first 282 (e.g., without limitation, upper layer) and second 284 (e.g., without limitation, lower layer) power sections (e.g., without limitation, PCB; buswork) are created. These two power sections 282, 284 then can be sandwiched into a structure (not shown, but see the sandwich structure of
A circuit assembly for the example first power section (half-leg) 282 can be constructed using the five-level NPP mechanical arrangement 210 of
A circuit assembly for the example second power section (half-leg) 284 of
The example circuit assemblies shown in
The disclosed concept is directly applicable to inverters and motor drives of all power ranges.
The disclosed concept simplifies construction, including the use of, for example and without limitation, simple PCBs in the context of medium voltage converters. The disclosed mechanical arrangements may split the power converter at the AC connection point and unwrap the circuit into a first (e.g., without limitation, upper) section and a second (e.g., without limitation, lower) section. After this unwrap, the power converter may be constructed in a single layer or folded across an axis of DC link capacitors, thereby lending to a relatively very simple mechanical arrangement. All of the elements of the power converter are exposed to an even voltage distribution (e.g., without limitation, an even voltage from corner to corner of the example PCBs or buswork), which enables a very compact layout and allows relatively smaller clearances.
While specific embodiments of the disclosed concept have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of the disclosed concept which is to be given the full breadth of the claims appended and any and all equivalents thereof.
This application claims the benefit of U.S. Provisional Patent Application Ser. No. 61/426,051, filed on Dec. 22, 2010, which is incorporated by reference herein, and U.S. Provisional Patent Application Ser. No. 61/501,876, filed on Jun. 28, 2011, which is incorporated by reference herein.
Number | Name | Date | Kind |
---|---|---|---|
3405343 | Boksjo | Oct 1968 | A |
4203151 | Baker | May 1980 | A |
4313155 | Bock et al. | Jan 1982 | A |
4481460 | Kroning et al. | Nov 1984 | A |
4689441 | Dick et al. | Aug 1987 | A |
4734315 | Spence-Bate | Mar 1988 | A |
4906987 | Venaleck et al. | Mar 1990 | A |
5126585 | Boys | Jun 1992 | A |
5131140 | Zimmer | Jul 1992 | A |
5187668 | Okude et al. | Feb 1993 | A |
5359294 | Ganger et al. | Oct 1994 | A |
5481448 | Nakata et al. | Jan 1996 | A |
5481474 | Lee | Jan 1996 | A |
5568035 | Kato et al. | Oct 1996 | A |
5572409 | Nathan et al. | Nov 1996 | A |
5621628 | Miyazaki et al. | Apr 1997 | A |
5644483 | Peng et al. | Jul 1997 | A |
5644500 | Miura et al. | Jul 1997 | A |
5675239 | Kim et al. | Oct 1997 | A |
5684688 | Rouaud et al. | Nov 1997 | A |
5710504 | Pascual et al. | Jan 1998 | A |
5841645 | Sato | Nov 1998 | A |
5907507 | Watanabe et al. | May 1999 | A |
5910892 | Lyons et al. | Jun 1999 | A |
6005362 | Enjeti et al. | Dec 1999 | A |
6005787 | Mizukoshi | Dec 1999 | A |
6018154 | Izaki et al. | Jan 2000 | A |
6031738 | Lipo et al. | Feb 2000 | A |
6058031 | Lyons et al. | May 2000 | A |
6101109 | Duba et al. | Aug 2000 | A |
6225781 | Okamura et al. | May 2001 | B1 |
6288921 | Uchino et al. | Sep 2001 | B1 |
6314007 | Johnson, Jr. et al. | Nov 2001 | B2 |
6316917 | Ohta | Nov 2001 | B1 |
6323623 | Someya et al. | Nov 2001 | B1 |
6396000 | Baum | May 2002 | B1 |
6404170 | Okamura et al. | Jun 2002 | B2 |
6414453 | Tamagawa et al. | Jul 2002 | B1 |
6424156 | Okamura | Jul 2002 | B1 |
6430066 | Emori et al. | Aug 2002 | B2 |
6437999 | Wittenbreder | Aug 2002 | B1 |
6452363 | Jabaji | Sep 2002 | B1 |
6459596 | Corzine | Oct 2002 | B1 |
6534949 | Szczesny et al. | Mar 2003 | B2 |
6536871 | Haddick et al. | Mar 2003 | B1 |
6617830 | Nozu et al. | Sep 2003 | B2 |
6628010 | Yamamura et al. | Sep 2003 | B2 |
6741482 | Yamamoto et al. | May 2004 | B2 |
6754090 | Arai et al. | Jun 2004 | B2 |
6762366 | Miller et al. | Jul 2004 | B1 |
6777912 | Yamada et al. | Aug 2004 | B1 |
6777917 | Desprez et al. | Aug 2004 | B2 |
6791210 | Stevenson et al. | Sep 2004 | B2 |
6795323 | Tanaka et al. | Sep 2004 | B2 |
6804353 | Schmokel | Oct 2004 | B2 |
6806686 | Thrap | Oct 2004 | B1 |
6809502 | Tsujii et al. | Oct 2004 | B2 |
6818838 | Jochym et al. | Nov 2004 | B1 |
6842354 | Tallam et al. | Jan 2005 | B1 |
6846992 | Amparan et al. | Jan 2005 | B2 |
6885170 | Okamura et al. | Apr 2005 | B2 |
6930899 | Bakran et al. | Aug 2005 | B2 |
6995994 | Bijlenga et al. | Feb 2006 | B2 |
7040391 | Leuthen et al. | May 2006 | B2 |
7050311 | Lai et al. | May 2006 | B2 |
7126833 | Peng | Oct 2006 | B2 |
7206705 | Hein | Apr 2007 | B2 |
7216833 | D'Ausilio et al. | May 2007 | B2 |
7219673 | Lemak | May 2007 | B2 |
7259975 | Holme Pedersen et al. | Aug 2007 | B2 |
7271505 | Miettinen | Sep 2007 | B1 |
7313008 | Steimer | Dec 2007 | B2 |
7378757 | Nakata | May 2008 | B2 |
7379312 | Baptiste et al. | May 2008 | B2 |
7409276 | Nishina et al. | Aug 2008 | B2 |
7477505 | Timmerman et al. | Jan 2009 | B2 |
7482816 | Odajima et al. | Jan 2009 | B2 |
7495418 | Yano et al. | Feb 2009 | B2 |
7495938 | Wu et al. | Feb 2009 | B2 |
7525817 | Yashiro | Apr 2009 | B2 |
7531987 | Ohasi et al. | May 2009 | B2 |
7573732 | Teichmann et al. | Aug 2009 | B2 |
7583057 | Morita | Sep 2009 | B2 |
7586770 | Toba et al. | Sep 2009 | B2 |
7599168 | Doljack et al. | Oct 2009 | B2 |
7619907 | Urakabe et al. | Nov 2009 | B2 |
7622898 | Shimizu et al. | Nov 2009 | B2 |
7646165 | Ueda et al. | Jan 2010 | B2 |
7663268 | Wen et al. | Feb 2010 | B2 |
7671569 | Kolb et al. | Mar 2010 | B2 |
7741811 | Daio | Jun 2010 | B2 |
7751212 | Perkinson | Jul 2010 | B2 |
7777456 | Morita et al. | Aug 2010 | B2 |
7800346 | Bolz et al. | Sep 2010 | B2 |
7812572 | Bolz et al. | Oct 2010 | B2 |
7825638 | Bolz et al. | Nov 2010 | B2 |
7848319 | Ornes et al. | Dec 2010 | B2 |
20020051370 | Reichard | May 2002 | A1 |
20040212352 | Anzawa et al. | Oct 2004 | A1 |
20040263121 | Thrap | Dec 2004 | A1 |
20050077879 | Near | Apr 2005 | A1 |
20050111246 | Lai et al. | May 2005 | A1 |
20050212493 | Yamaguchi et al. | Sep 2005 | A1 |
20060038549 | Mehrotra et al. | Feb 2006 | A1 |
20060152085 | Flett et al. | Jul 2006 | A1 |
20060221653 | Lai et al. | Oct 2006 | A1 |
20070001651 | Harvey | Jan 2007 | A1 |
20070194627 | Mori et al. | Aug 2007 | A1 |
20070223258 | Lai et al. | Sep 2007 | A1 |
20080018301 | Morita | Jan 2008 | A1 |
20080055947 | Wen et al. | Mar 2008 | A1 |
20080094042 | Ferrario | Apr 2008 | A1 |
20080205093 | Davies et al. | Aug 2008 | A1 |
20080218176 | Ohashi et al. | Sep 2008 | A1 |
20080252266 | Bolz et al. | Oct 2008 | A1 |
20090086515 | Sakakibara | Apr 2009 | A1 |
20090134851 | Takeda et al. | May 2009 | A1 |
20090251099 | Brantner et al. | Oct 2009 | A1 |
20090273321 | Gotzenberger et al. | Nov 2009 | A1 |
20100090663 | Pappas et al. | Apr 2010 | A1 |
20100148582 | Carter | Jun 2010 | A1 |
20100207644 | Nestler et al. | Aug 2010 | A1 |
20100208446 | Lapassat et al. | Aug 2010 | A1 |
20100283434 | Kakiuchi | Nov 2010 | A1 |
20100321965 | Sakakibara | Dec 2010 | A1 |
Number | Date | Country |
---|---|---|
2696197 | Apr 2005 | CN |
1005132 | Oct 2001 | EP |
Entry |
---|
United States Patent and Trademark Office, “International Search Report and Written Opinion”, Jun. 20, 2012, 13 pp. |
Ryszard Strzelecki, “Analysis of DC Link Capacitor Voltage Balance in Multilevel Active Power Filters”, EPE 2001—Gratz, pp. 1-8. |
Ashish Bendre, “Comparative Evaluation of Modulation Algorithms for Neutral-Point-Clamped Converters”, IEEE Transactions on Industry Applications, Mar./Apr. 2005, pp. 634-643, vol. 41, No. 2. |
A. Nami, “A New Configuration for Multilevel Converters With Diode Clamped Topology”, In Proceedings 8th International Power Engineering Conference (IPEC 2007), pp. 661-665, Singapore. |
H. Ertl, “Active voltage balancing of DC-link electrolytic capacitors”, IET Power Electron., 2008, pp. 448-496, vol. 1, No. 4. |
Unofficial English Translation of Chinese Office Action issued in connection with corresponding CN Application No. 201180068244.8 on Jun. 3, 2015. |
Number | Date | Country | |
---|---|---|---|
20120163057 A1 | Jun 2012 | US |
Number | Date | Country | |
---|---|---|---|
61501876 | Jun 2011 | US | |
61426051 | Dec 2010 | US |