Patent Application
20060242316
The present invention relates to computer systems; more particularly, the present invention relates to transmitting data via a network.
Currently, there are various applications that involve the transfer of bulk data across multi-hop wireless networks. One such application includes the transfer of up to 6 Kbytes of data from any individual network node to a central server via cheap and low bandwidth (10-40 kbps) radio links. Problems often occur in such systems in that there may be up to five thousand nodes in the network, where failure of nodes is a relatively common occurrence.
A failure typically results in having to reboot a failed node. Reboots may occur due to hardware failures, or may be triggered by a watchdog in response to a hardware or software lockup. Failures and lockups may lose or corrupt internal protocol states, making resumption of data transfer difficult. However, due to the simple nature of operating systems used in the nodes makes boot-up relatively instantaneous, network protocols should allow a node to quickly resume data transfer after reboot.
Applications have been developed to resume a transfer after reboot (e.g., “wget-c”). However, such applications involve the re-establishment of connections and carrying out a complete transaction from the beginning.
The invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
A method for transmitting data to between a source node and a receiving node upon a failure at the source device is described. The method includes a reboot occurring at the source device due to a failure. It is subsequently determined whether a Negative Acknowledge (Nack) has been received at the source device from the receiving device. If the Nack is received, the source device continues to transmit data stored in a non-volatile memory where it left off prior to having to reboot.
In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
Some portions of the detailed descriptions that follow are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
The present invention also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. In addition, the present invention is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the invention as described herein.
The instructions of the programming language(s) may be executed by one or more processing devices (e.g., processors, controllers, control processing units (CPUs),
In one embodiment, main system memory 215 includes dynamic random access memory (DRAM); however, main system memory 215 may be implemented using other memory types. For example, in some embodiments, main system memory 215 may be implemented with a non-volatile memory.
devices may also be coupled to bus 205, such as multiple CPUs and/or multiple system memories. MCH 110 is coupled to an input/output control hub (ICH) 240 via a hub interface. ICH 240 provides an interface to input/output (I/O) devices within computer system 200.
As discussed above, the failure of a source device transmitting data to a receiving device may cause the source device to have to be rebooted, therefore causing data to potentially be lost or corrupted. According to one embodiment, a stateless mechanism is disclosed that enables bulk data transfers across device reboots and failures. Such a mechanism leverages the fact that bulk data transfers are performed in one direction (e.g., from a source device 110 to a receiving device 120). In such an embodiment, the source component on the protocol is stateless, while the receiving device maintains the state, thus allowing the source device to continue to transfer data after a failure.
In one embodiment, a Transaction ID identifies a connection established to transfer data between a source device and a receiving device. After a connection is established the data is transferred using a Negative Acknowledge (Nack) based sliding window protocol. In such an embodiment, the Nack includes a bitmap that provides information of fragments received during the current window.
According to one embodiment, data to be transferred by the source device is captured at a non-volatile memory device (e.g., main memory 215) at the source device so that contents are not lost across reboots. As discussed above, the state and other information about open connections is maintained at the receiving device. This information includes the Transaction ID for the connection, received fragments, received fragment window (e.g., bitmap that keeps track of fragments that have been received), and the starting fragment of the current window.
The source device maintains, in the non-volatile memory device, the data it needs to transfer for the active connection(s). In one embodiment, the source device is able to regain the state from the Nack when a subsequent Nack is received. At the end of a data transfer an Ack is transmitted by the receiving device to indicate the connection is to be closed. Thus, the source device may erase the data from the previous connection from the non-volatile memory so that a new connection may be established.
If the Nack has not been received, it is determined whether a Nack wait timeout has occurred, decision block 340. If a timeout has not occurred, control is returned to decision block 320 where it is again determined whether the Nack has been received. If a timeout has occurred, the source device waits for the next data capture/transmit request.
The above-described mechanism enables the dividing of the state of a unidirectional transport protocol across a reliable receiver and an unreliable transmitter so that the sender maintains a soft state and can easily recover from a failure.
Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as essential to the invention.
