The memory 180 includes, for example, four banks 181, 182, 183 and 184. In the descriptions below, these four banks 181, 182, 183 and 184 are referred to as Bank 1, Bank 2, Bank 3 and Bank 4, respectively. The three bus masters 141, 142 and 143 are sometimes referred to as Master A, Master B and Master C, respectively.
The memory access controller 100 includes an access request bank analyzer 110, a bank use state information holder 125, and an access permission signal generator 130.
The bus masters 141, 142 and 143 are processors which request memory accesses with different bus protocols and different data widths. The memory access requests from the bus masters 141, 142 and 143 are converted to the same protocol and shaped to have the same data width by the bus interfaces 151, 152 and 153. The bus matrix 160 arbitrates the memory accesses from the bus masters 141, 142 and 143 according to an arbitration method implemented by hardware or software, thereby controlling the accesses. The result of the arbitration by the bus matrix 160 among the memory accesses from the bus masters 141, 142 and 143 is input in the form of memory access request signal S01, which includes address information and access information, to the memory access controller 100.
In the memory access controller 100, the access request bank analyzer 110 generates based on the address information and access information of memory access request signal S01 access request bank information S02 indicative of to which bank an access request is directed. The access permission signal generator 130 compares access request bank information S02 and bank use state information S03 of the bank use state information holder 125. If information S02 and information S03 indicate access requests to the same bank while information S03 indicates that at least one of the banks to which access requests have been issued is currently busy, access permission signal S04 is set to indicate “access unpermitted”. If information S02 and information S03 indicate access requests to the same bank while information S03 indicates that none of the banks to which access requests have been issued is currently busy (i.e., every one of the banks is free), access permission signal S04 is set to indicate “access permitted”. The bank use state information holder 125 sets bank use state information S03 of a bank specified by the address information of a memory access permitted by access permission signal S04 to “busy” and, after passage of a predetermined period determined according to access information S06 from the access request bank analyzer 110, or when access information S06 meets a predetermined condition, updates bank use state information S03 such that the bank is shown as being “free”.
The bus matrix 160 determines based on access permission signal S04 whether or not memory access request signal S01 for which an access permission has been currently issued as a result of arbitration is allowable for memory access. If access permission signal S04 indicates “access permitted”, arbitration is carried out on subsequent accesses. If access permission signal S04 indicates “access unpermitted”, the bus matrix 160 holds the arbitration result till subsequent determination as to access permission occurs and then continues to request a permission for access from the memory access controller 100.
Access permission signal S04 is also input to the memory interface 170 at the same time. Memory access S05 permitted for access by the memory access controller 100 is converted by the memory interface 170 to a protocol suitable to memory access and is transmitted as memory access signal S07 to the memory 180. Herein, the memory interface 170 carries out an access while activating only part of the bank equivalent to a data width determined to be actually necessary based on address information, access size information, etc.
The access request bank analyzer 110 includes an address analyzer 111, a transfer direction analyzer 112, an access unit analyzer 113, a master analyzer 114, a slave clock gear ratio analyzer 115, a master clock gear ratio analyzer 116, a remapping information analyzer 117, a use scene analyzer 118, a temperature analyzer 119, a fault detection analyzer 120, and a memory initialization recognizer 121.
The address analyzer 111 generates based on the address information of memory access request signal S01 access request bank information S02 indicative of to which bank an access request is directed.
The transfer direction analyzer 112 supplies transfer direction information as access information S06 to the bank use state information holder 125. The transfer direction information is information explicitly designated by each of the bus masters 141, 142 and 143 to the memory access controller 100 as to whether an access to the memory 180 is a write access or read access. Therefore, when the memory 180 has different completion times for a read access and write access, or when the difference between the completion times for a read access and write access results from a non-memory factor, the access-prohibited time can be set for an access to a memory bank according to each of the read access and write access. For example, the read access requires several cycles of data waiting interval. However, in the case of a write access, if the memory 180 is accessible every cycle, the access-prohibited time for several cycles is set only for the read access while such setting is unnecessary for the write access. Thus, circuit cost is suppressed while the accessibility of the write access need not to be adjusted to that of the read access. Therefore, the accessibility for the entire operation can be improved.
The access unit analyzer 113 supplies access unit information as access information S06 to the bank use state information holder 125. The access unit information is information explicitly designated by each of the bus masters 141, 142 and 143 to the memory access controller 100 as to the unit of access to the memory 180. With the access unit information, such an undesirable result is avoided that part of the bank is included in a busy area even though it is not actually targeted for access and a memory access to another bank is denied. The bank width which is to be shown as being busy is limited to the width of a bank access, whereby the other area of the bank is set free so that the free part of the bank is accessible.
The master analyzer 114 supplies master information as access information S06 to the bank use state information holder 125. The master information is information explicitly designated by each of the bus masters 141, 142 and 143 to the memory access controller 100 as to the unit of access to the memory 180. Therefore, when the unit of access is determined by each of the bus masters 141, 142 and 143, the master analyzer 114 identifies the unit of access according to which master accesses. Part of the bank which is not targeted for access is set free so that the free part of the bank is accessible. In the case where the masters have different required access speeds, the inaccessible time can be set according to the requirements as to the access speed from the masters 141, 142 and 143.
For example, consider a case where a high speed memory and low speed memory are connected and use the same addresses. Herein, Masters A, B and C request different access response times. Master A accesses the high speed memory and Master B accesses the low speed memory, which are automatically switched by the memory interface 170. Each of the bus masters 141, 142 and 143 does not explicitly designate whether it accesses the high speed memory or low speed memory.
It should be noted that the inaccessible periods after the access by Master A and the access by Master B (“busy periods”) may be implemented by hardware in advance or may be settable through a register.
The slave clock gear ratio analyzer 115 supplies slave clock gear ratio information as access information S06 to the bank use state information holder 125. The slave clock gear ratio information is information explicitly designated by each of the bus masters 141, 142 and 143 to the memory access controller 100 as to the clock gear ratio in a system where the clock gear ratio between the memory access controller 100 and the memory 180 is changeable. Therefore, the inaccessible time can be set according to the clock gear ratio.
For example, the clock gear ratio between the memory access controller 100 and the memory 180 is switched between 1:1 and 3:1. The high speed memory is accessed when the clock gear ratio is 1:1, and the low speed memory is accessed when the clock gear ratio is 3:1. With such an arrangement, memory accesses suitable to the clock gear ratio and access control for the memory accesses can readily be carried out.
The master clock gear ratio analyzer 116 supplies master clock gear ratio information as access information S06 to the bank use state information holder 125. The master clock gear ratio information is information explicitly designated by each of the bus masters 141, 142 and 143 to the memory access controller 100 as to the clock gear ratio in a system where the clock gear ratio between each of the bus masters 141, 142 and 143 and the memory access controller 100 is changeable. Therefore, the inaccessible time can be set according to the clock gear ratio.
For example, a high speed memory which is inaccessible for one cycle after an access and a low speed memory which is inaccessible for three cycles after an access are connected. The clock gear ratio between each of the bus masters 141, 142 and 143 and the memory access controller 100 is switched between 1:1 and 3:1. Where the clock of the memory access controller 100 is employed as a reference cycle, if the clock gear ratio is 1:1, the memory is inaccessible for one cycle, and if the clock gear ratio is 3:1, the memory is inaccessible for three cycles.
The remapping information analyzer 117 supplies remapping information as access information S06 to the bank use state information holder 125. The remapping information is information explicitly designated to the memory access controller 100 that data is currently being remapped in a system where addressing of data location in the memory 180 is changeable. Therefore, in a system having a plurality of types of memories of different access speeds, the control of data access to memories of different access speeds with remapping is enabled by setting the inaccessible time according to the specifications regarding the speed of each memory.
The use scene analyzer 118 supplies use scene information as access information S06 to the bank use state information holder 125. The use scene information is information explicitly designated to the memory access controller 100 that data is currently being remapped in a system where addressing can be changed according to the operation speed and memory capacity required by each of the bus masters 141, 142 and 143 which operates based on an application launched by the system, and a plurality of types of memories of different access speeds are switched. Therefore, in a system having a plurality of types of memories of different access speeds, the control of data access based on the speed and capacity required by an application that runs is enabled by setting the inaccessible time according to the specifications regarding the speed of each memory.
For example, the requirements as to the accessibility to the memory 180 differ among use scenes in which the bus masters 141, 142 and 143 operate (operating applications). Each of the bus masters 141, 142 and 143 designates the use scene information explicitly classified into some categories to the memory access controller 100. The use scene analyzer 118 of the memory access controller 100 designates whether to access the high speed memory or low speed memory based on the received use scene information and the requested accessibility for respective use scenes designated by hardware or software in advance. The instruction as to whether to access the high speed memory or low speed memory is also directed to the memory interface 170 at the same time. The memory interface 170 allocates actual accesses to the high speed memory or low speed memory according to the instruction.
The temperature analyzer 119 supplies temperature information as access information S06 to the bank use state information holder 125. The temperature information is information explicitly designated to the memory access controller 100 that, in a system where a plurality of types of memories of different access speeds are switched according to the temperature obtained from an environment in which the system operates, the type of memory used is switched by addressing according to the varying temperature. Therefore, in a system having a plurality of types of memories of different access speeds, access to a memory which is inoperable in view of the specifications due to the temperature characteristic of an environment where the system operates, etc., is stopped, and the control of accessing an operable memory is enabled by setting the inaccessible time according to the specifications regarding the speed of each memory.
For example, the delay of memory access varies according to the temperature at which the memory 180 and the memory access controller 100 operate. If the temperature is lower than a predetermined temperature, an access to the high speed memory is carried out. If the temperature is higher than a predetermined temperature, an access to the low speed memory is carried out. The temperature analyzer 119 of the memory access controller 100 designates whether to access the high speed memory or low speed memory based on a table of the relationships between the received temperature information, the temperatures designated by hardware or software in advance, and operable memories. The instruction as to whether to access the high speed memory or low speed memory is also directed to the memory interface 170 at the same time. The memory interface 170 allocates actual accesses to the high speed memory or low speed memory according to the instruction.
The fault detection analyzer 120 supplies fault detection information as access information S06 to the bank use state information holder 125. The fault detection information is information explicitly designated to the memory access controller 100 that, in a system capable of distinguishing whether or not the memory 180 is operable, a fault memory is avoided such that an employable memory is selected. Therefore, in a system having a fault detection function, access to a fault memory is stopped, and the control of accessing an operable memory is enabled by setting the inaccessible time according to the specifications regarding the speed of each memory.
For example, where a high speed memory is used as a main memory, detection of a fault in the high speed memory by the fault detection function triggers the use of a reserve low speed memory. The fault detection analyzer 120 of the memory access controller 100 designates whether to access the high speed memory or low speed memory based on a table of the relationships between the received fault detection information and the memories operable at the time of detection of a fault which are designated by hardware or software in advance. The instruction as to whether to access the high speed memory or low speed memory is also directed to the memory interface 170 at the same time. The memory interface 170 allocates actual accesses to the high speed memory or low speed memory according to the instruction.
The memory initialization recognizer 121 supplies memory initialization information as access information S06 to the bank use state information holder 125. The memory initialization information is information explicitly designated to the memory access controller 100 that, in a system which initializes a memory before use, a memory which is currently in the midst of initialization is avoided such that an employable memory is selected. Therefore, in a system having a function of detecting initialization, access to a memory which is currently in the midst of initialization is stopped, and the control of accessing an operable memory is enabled by setting the inaccessible time according to the specifications regarding the speed of each memory.
For example, where a high speed memory is used as a main memory, if the memory initialization detection function detects that the high speed memory is currently in the midst of initialization, a reserve low speed memory is used. The memory initialization recognizer 121 of the memory access controller 100 designates whether to access the high speed memory or low speed memory based on a table of the relationships between the received memory initialization information and the memories operable during initialization and at the time of completion of the initialization which are designated by hardware or software in advance. The instruction as to whether to access the high speed memory or low speed memory is also directed to the memory interface 170 at the same time. The memory interface 170 allocates actual accesses to the high speed memory or low speed memory according to the instruction.
It should be noted that the inaccessible periods after the access to the high speed memory and the access to the low speed memory (“busy periods”) may be implemented by hardware in advance or may be settable through a register.
Hereinabove, utilization of the transfer direction information, access unit information, master information, etc., has been generally described. Hereinafter, utilization of the transfer direction information and access unit information, in particular, is described in detail with reference to the drawings.
Transfer direction information S06 of
Referring to
Referring to
Hereinabove, the memory access controller 100 shown in
As described hereinabove, a memory access controller of the present invention controls access requests to a memory which has a plurality of banks based on address information and access information to control memory accesses according to the types of the accesses, the conditions of a system, the type of the memory, etc., and is therefore useful for a system where a memory having a plurality of banks is accessed.
Number | Date | Country | Kind |
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2006-285018 | Oct 2006 | JP | national |