This application claims priority from Korean Patent Application No. 10-2007-0017775, filed on Feb. 22, 2007, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.
1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to a memory system, and more particularly, to a method and apparatus for accessing a linear addressable memory (LAM) using a three-dimensional address (3-D) mapping.
2. Description of Related Art
Also, double loops or triple loops occur frequently in many different kinds of programs. Particularly, triple loops are frequently used in a program for video processing. Accordingly, a method and apparatus for efficiently accessing a memory accessed by the triple loop is needed.
Exemplary embodiments of the present invention overcome the above disadvantages and other disadvantages not described above. Also, the present invention is not required to overcome the disadvantages described above, and an exemplary embodiment of the present invention may not overcome any of the problems described above.
The present invention provides a method and apparatus for efficiently accessing a memory accessed by a triple loop included in a program.
The present invention also provides a method and apparatus for efficiently mapping a linear address into a 3-D address which is suitable for an address computation of a memory accessed by a triple loop.
According to an aspect of the present invention, there is provided a memory access method, including: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining a number of addresses of the memory accessed by the triple loop using the starting address and a function, wherein the number of addresses is a×b×c.
According to another aspect of the present invention, there is provided a memory access method, further including: mapping a linear address addr of a memory into a two-dimensional (2-D) address (m, n); mapping the 2-D address (m, n) into a 3-D address (x, y, z); mapping the 3-D address (x, y, z) into a 3-D module (p, q, r); and generating a 3-D module array, (p, q, r) which comprises addresses which are mapped into the 3-D module (p, q, r), the addresses being sorted sequentially.
According to still another aspect of the present invention, there is provided a 3-D address mapping method, including: mapping a linear address addr of a memory into a 2-D address (m, n); and mapping the 2-D address (m, n) into a 3-D address (x, y, z), wherein L is a scan-line length of the memory, m is a quotient of (addr/L), n is a remainder of (addr/L), x=m, y=a quotient of (n/a), z=a remainder of (n/a), and a is a number of values which an inner-most loop variable may have.
The above and other aspects of the present invention will become apparent and more readily appreciated from the following detailed description of certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings of which:
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to the like elements throughout.
A function fullsearch( ) illustrated in
When accessing the memory with the 1-D pattern, sequential memory locations are accessed. However, when accessing the memory with the 2-D pattern or the 3-D pattern, arbitrary memory locations are accessed. In
In
According to the present exemplary embodiment, the linear address addr of the memory is mapped into the 2-D address (m, n), which is represented as,
addr→(m,n) [Equation 1]
Here, m is a quotient of (addr/L), n is a remainder of (addr/L), and L is a scan-line length of the memory. The scan-line length of the memory indicates a width when interpreting the memory. In
According to the present exemplary embodiment, an inner-most loop variable of a triple loop is i, and a number of values which the inner-most loop variable i may have is a. For example, when an inner-most loop is for (i=0; i<2; i++), the inner-most loop variable is i, and values which the inner-most loop variable i may have are 0 and 1. Accordingly, a, i.e., the number of values which the inner-most loop variable i may have, is 2. Similarly, a middle loop variable of the triple loop is j, and a number of values which the middle loop variable j may have is b. Also, an outer-most loop variable of the triple loop is k, and a number of values which the outer-most loop variable k may have is c. According to the present exemplary embodiment, both a and b are 2. In
According to the present exemplary embodiment, the 2-D address (m, n) mapped from the linear address addr of the memory is virtually mapped into a 3-D address (x, y, z), which is represented as,
(m,n)→(x,y,z) [Equation 2]
Here, x is the same as m, y is a quotient of (n/a), z is a remainder of (n/a), and a is a number of values which an inner-most loop variable of a triple loop may have. A memory 420, represented as the 3-D address (x, y, z) by virtually converting a memory 410 represented as the 2-D address (m, n) into the 3-D address (x, y, z), is illustrated in
According to the present exemplary embodiment, the 3-D address (x, y, z) is mapped into the 3-D module (p, q, r), which is represented as,
(x,y,z)→(p,q,r) [Equation 3]
Here, p=x mod a, q=y mod b, r=z mod c, a is a number of values which an inner-most loop variable of a triple loop may have, b is a number of values which a middle loop variable of the triple loop may have, and c is a number of values which an outer-most loop variable of the triple loop may have.
A memory 520, represented as the 3-D module (p, q, r) by mapping a memory 510 represented as the 3-D address (x, y, z) into the 3-D module (p, q, r), is illustrated in
According to the present exemplary embodiment, the 3-D module array (p, q, r) is generated using a generated 3-D module (p, q, r). The 3-D module array (p, q, r) includes addresses which are mapped into the 3-D module (p, q, r), and the addresses are sorted sequentially.
A starting address of a memory accessed by the triple loop is mapped into a 3-D address. Since the starting address of the memory accessed by the triple loop is a linear address, an operation of mapping the linear address into the 3-D address is performed using Equation 1 and Equation 2. For example, in
An a×b×c block is accessed using following Equation 4. Here, a is a number of values which an inner-most loop variable of the triple loop may have, b is a number of values which a middle loop variable of the triple loop may have, and c is a number of values which an outer-most loop variable of the triple loop may have. L is a scan-line length of the memory.
Here, (x1, y1, z1) is an initial 3-D address of the a×b×c block. Ap,q,r(x1, y1, z1) corresponds to a value of where an address mapped into a 3-D module (p, q, r) in the a×b×c block is located in a 3-D module array (p, q, r). In this instance, the a×b×c block has (x1, y1, z1) as the 3-D address of the starting address. Specifically, when Ap,q,r(x1, y1, z1) has a value of f, the address mapped into the 3-D module (p, q, r) in the a×b×c block, which has (x1, y1, z1) as the 3-D address of the starting address, corresponds to a value of (f+1)th in the 3-D module array (p, q, r).
According to the present exemplary embodiment, in
For example, in
Similarly, when substituting (0, 0, 0) into the 3-D module (p, q, r) using Equation 4, A0,0,0(1, 3, 1)=(0+1)×4+1+1+0=6 is obtained. Specifically, an address mapped into the 3-D module (0, 0, 0) in the 2×2×2 block, which has (1, 3, 1) as the 3-D address of the starting address, corresponds to 7th (6+1) in a 3-D module array (0, 0, 0). Referring to
Particularly, although the block to access 710 is not aligned in
In operation S810, a program code for accessing a memory with the triple loop in a program is identified. For example, referring to
In operation S820, a starting address of the memory accessed by the triple loop is obtained. In the program described with reference to
In operation S830, an a×b×c number of addresses of the memory accessed by the triple loop is obtained using the starting address and a function. For this, a linear address of the memory is mapped into a 3-D address, and a 3-D module array is computed based on the 3-D address, which has been described with reference to
In operation S910, a linear address addr of a memory is mapped into a 2-D address (m, n), which is given by Equation 1 described with reference to
In operation S920, the 2-D address (m, n) is mapped into a 3-D address (x, y, z), which is given by Equation 2 described with reference to
In operation S930, the 3-D address (x, y, z) is mapped into a 3-D module (p, q, r), which is given by Equation 3 described with reference to
In operation S940, a 3-D module array (p, q, r) which includes addresses mapped into the 3-D module (p, q, r) is generated, which has been described with reference to
The memory access method using the 3-D address mapping method according to the above-described exemplary embodiments may be recorded in computer-readable media including program instructions to implement various operations embodied by a computer. The media may also include, alone or in combination with the program instructions, data files, data structures, and the like. Examples of computer-readable media include magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD ROM disks and DVDs; magneto-optical media such as optical disks; and hardware devices that are specially configured to store and perform program instructions, such as a read-only memory (ROM), a random access memory (RAM), a flash memory, and the like. Examples of program instructions include both machine code, such as produced by a compiler, and files containing higher level code that may be executed by the computer using an interpreter. The described hardware devices may be configured to act as one or more software modules in order to perform the operations of the above-described embodiments of the present invention.
The 3DAMC 1020 performing a memory access method according to an exemplary embodiment of the present invention may be embodied as hardware. In this case, the 3DAMC 1020 is located between a processing unit 1030 and the LAM 1010. Also, the 3DAMC 1020 can access a memory by a block with respect to a program code which is accessed by a triple loop, using a 3-D address mapping method, according to an exemplary embodiment of the present invention. An operation performed by the 3DAMC 1020 may be a portion of or entire operations described with reference to
Although it is described with respect to only the triple loop, the present invention may be applied to a loop equal to or greater than a quadruple loop. In this case, the loop equal to or greater than the quadruple loop may efficiently perform a memory access by applying the present invention with respect to an inner triple loop.
According to the exemplary embodiments of the present invention, there is provided a method and apparatus for efficiently accessing a memory accessed by a triple loop included in a program.
According to the exemplary embodiments of the present invention, there is provided a method and apparatus for efficiently mapping a linear address into a 3D address which is suitable for an address computation of a memory accessed by a triple loop.
According to the exemplary embodiments of the present invention, a memory accessed by a triple loop may be accessed by a block unit regardless of an alignment of the memory.
Although a few exemplary embodiments of the present invention have been shown and described, the present invention is not limited to the described exemplary embodiments. Instead, it would be appreciated by those skilled in the art that changes may be made to these exemplary embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
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20080209159 A1 | Aug 2008 | US |