BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A (prior art) is a partial top view of a conventional dual bit nitride read only memory.
FIG. 1B (prior art) is a cross-sectional view of the dual bit nitride read only memory along the cross-sectional line 1B˜1B′ of FIG. 1A;
FIG. 2A is partial top view of a memory according to a first embodiment of the invention;
FIG. 2B is a cross-sectional view of the memory along the cross-sectional line 2B˜2B′ of FIG. 2A;
FIGS. 3A˜3E are cross-sectional diagrams showing the manufacturing process of the memory according to the first embodiment of the invention;
FIG. 4A is partial top view of a memory according to a second embodiment of the invention;
FIG. 4B is a cross-sectional view of the memory along the cross-sectional line 4B˜4B′ of FIG. 4A; and
FIGS. 5A˜5D are cross-sectional diagrams showing the manufacturing process of the memory according to the second embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
FIRST EMBODIMENT
Referring to FIGS. 2A˜2B. FIG. 2A is a partial top view of a memory according to a first embodiment of the invention. FIG. 2B is a cross-sectional view of the memory along the cross-sectional line 2B˜2B′ of FIG. 2A. In FIGS. 2A˜2B, the memory 200 includes a substrate 210, a number of bit lines 220, a number of word lines 230, a number of oxide-nitride-oxide (ONO) structures 240, a number of isolation layers 250, a number of memory cells 215 (enclosed in larger dotted circles in FIG. 2A and FIG. 2B), a number of first bit storage nodes 217a, and a number of second bit storage nodes 217b. The bit lines 220 are disposed in parallel, formed in the substrate 210, and positioned near the surface of the substrate 210. The word lines 230 are disposed in parallel and formed on the substrate 210. Furthermore, the word lines 230 are crossed with but not perpendicular to the bit lines 220. That is, an acute angle θ is contained between the word lines 230 and the bit lines 220. In the present embodiment of the invention, the acute angle θ is contained between the word line 230 and bit line 220 is preferably 45 degrees. The ONO structures 240 are disposed between the word lines 230 and the substrate 210, and spaced by the bit lines 220. The isolation layers 250 are disposed on the bit lines 220 and spaced by the ONO structures for isolating the word lines 230 and the bit lines 220. The first bit storage node 217a and the second bit storage node 217b are correspondingly formed in each ONO structure 240 adjacent to the two isolation layers 250. In the present embodiment of the invention, the substrate 210 is exemplified by a silicon substrate. The memory 200 is a dual bit nitride read only memory (NROM).
Referring to FIG. 2B. The ONO structure 240 includes a top oxide layer 241, a bottom oxide layer 245, and a nitride layer 243. The bottom oxide layer 245 is disposed on the substrate. The top oxide layer 241 is disposed on the bottom oxide layer 245. The nitride layer 243 is disposed between the top oxide layer 241 and the bottom oxide layer 245. The material of the nitride layer 243 includes silicon nitride (SiN), and the material of the word line 230 includes polysilicon. The isolation layer is a barrier diffusion (BD) oxide. However, any one who is skilled in the technology of the invention will understand that the material is exemplified as an example in the present embodiment of the invention not for limiting the scope of technology of the invention.
The memory cells 215 include the word lines 230, the bit lines 220 and the ONO structures 240. The memory cells 215 are arranged as a memory cell array as shown in FIG. 2A. Each memory cell 215 has a first bit storage node 217a and a second bit storage node 217b. The first bit storage node 217a and the second bit storage node 217b in each memory cell 215 are alternated and disposed along the direction of the word line 230.
Referring to FIGS. 3A˜3E, cross-sectional diagrams showing the manufacturing process of the memory according to the first embodiment of the invention are shown. Firstly, in FIG. 3A, a substrate 210 is provided, and then a oxide-nitride-oxide (ONO) layer 235 is formed into a piece on the substrate 210. In the step of forming the ONO structure 235, firstly, the bottom oxide layer 245a is formed into a piece on the substrate 210. Then, the nitride layer 243a is formed into a piece on the bottom oxide layer 245a. Finally, the top oxide layer 241a is formed into a piece on the nitride layer 243a.
Next, in FIG. 3B, a patterned photo-resist layer 260 is formed on the ONO structure 235. The patterned photo-resist layer 260 has a number openings 260a for exposing part of the ONO structure 235. Then, a number of parallel bit lines 220 are formed in the part of the substrate 210 corresponding to the openings 260a by using ion implantation process.
Then, in FIG. 3C, firstly, part of the top oxide layer 241a is removed. Then, part of the nitride layer 243a under there is removed. Finally, the patterned photo-resist layer 260 is removed.
Next, in FIG. 3D, a number of isolation layers 250 are formed on the bit lines 220 and then a number of ONO structures 240 are formed on the substrate 210. The ONO structures 240 are spaced by the isolation layers 250.
Then, in FIG. 3E, a number of parallel word lines 230 are formed on the substrate 210. The word lines 230 are crossed with but not perpendicular to the bit lines 220. An acute angle θ is contained between the word line 230 and the bit line 220. Furthermore, in the step of word lines 230, firstly, a polysilicon layer, is formed on the substrate 210, and then part of the polysilicon layer is removed by etching method to form the word lines 230. In the present embodiment of the invention, the acute angle θ contained between the word line 230 and the bit line 220 is preferably 45 degrees as shown in FIG. 2A. Thus, the dual bit nitride read only memory 200 is formed as shown in FIG. 3E.
In the present embodiment of the invention, the design of having the bit lines 220 be crossed with but not perpendicular to the word lines 230 enables the first bit storage node 217a and the second bit storage node 217b of the memory cell 215 to have a larger storage space and the concentration of electrons stored in the first bit storage node 217a and the second bit storage node 217b also increase. When the background radiation causes loss to the electrons stored in the memory cell, the decrease in the electron concentration of the memory cell having a high concentration of electron storage is still within a tolerable range. Therefore, the bits stored in the memory cell are still correct and the overall data are free of errors when reading.
SECOND EMBODIMENT
Referring to FIGS. 4A˜4B. FIG. 4A is partial top view of a memory according to a second embodiment of the invention. FIG. 4B is a cross-sectional view of the memory along the cross-sectional line 4B˜4B′ of FIG. 4A. In FIGS. 4A˜4B, the memory 300 includes a substrate 310, a number of bit lines 320, a number of word lines 330, a oxide-nitride-oxide (ONO) layer 340, a number of memory cells 315 (enclosed in larger dotted circles in FIG. 4A and FIG. 4B), a number of first bit storage nodes 317a, and a number of second bit storage nodes 317b. The bit lines 320 are disposed in parallel formed in the substrate 310, and positioned near the surface of the substrate 310. The word lines 330 are disposed in parallel and formed on the substrate 310. Furthermore, the word lines 330 are crossed with but not perpendicular to the bit lines 320. That is, an acute angle α is contained between the word lines 330 and the bit lines 320. In the present embodiment of the invention, the acute angle α is contained between the word line 330 and bit line 320 is preferably 45 degrees. The ONO structure 340 is continuously disposed into a piece on the substrate 310, and covers the bit lines 320. The word lines 320 are disposed on part of the ONO structure 340. The first bit storage node 317a and the second bit storage node 317b are correspondingly formed in part of ONO structure 340 adjacent to the sides of two isolation layers 250. In the present embodiment of the invention, the substrate 310 is exemplified by a silicon substrate. The memory 300 is a dual bit nitride read only memory (NROM).
Referring to FIG. 4B. The ONO structure 340 includes a top oxide layers 341, a bottom oxide layer 345, and a nitride layer 343. The bottom oxide layer 345 is disposed on the substrate. The top oxide layer 341 is disposed on the bottom oxide layer 345. The nitride layer 343 is disposed between the top oxide layer 341 and the bottom oxide layer 345. The material of the nitride layer 343 includes silicon nitride (SiN), and the material of the word line 330 includes polysilicon. The isolation layer is a barrier diffusion (BD) oxide. However, any one who is skilled in the technology of the invention will understand that the material is exemplified as an example in the present embodiment of the invention not for limiting the scope of technology of the invention.
The memory cells 315 include the word lines 330, the bit lines 320 and the ONO structure 340. The memory cells 315 are arranged as a memory cell array as shown in FIG. 4A. Each memory cell 315 has a first bit storage node 317a and a second bit storage node 317b. The first bit storage node 317a and the second bit storage node 317b in each memory cell 315 are alternated and disposed along the direction of the word line 330.
Referring to FIGS. 5A˜5D, cross-sectional diagrams showing the manufacturing process of the memory according to the second embodiment of the invention are shown. Firstly, in FIG. 5A, a substrate 310 is provided, and then a oxide-nitride-oxide (ONO) layer 340 is formed into a piece on the substrate 310. In the step of forming the ONO structure 340, firstly, the bottom oxide layer 345 is formed into a piece on the substrate 310. Then, the nitride layer 343 is formed into a piece on the bottom oxide layer 345. Finally, the top oxide layer 341 is formed into a piece on the nitride layer 343.
Next, in FIG. 5B, a patterned photo-resist layer 360 is formed on the ONO structure 340. The patterned photo-resist layer 360 has a number openings 360a for exposing part of the ONO structure 340. Then, a number of parallel bit lines 320 are formed in the part of the substrate 310 corresponding to the openings 360a by using ion implantation process.
Then, in FIG. 5C, the patterned photo-resist layer 360 is removed.
Next, in FIG. 5D, a number of parallel word lines 330 are formed on the part of the ONO structure 340. The word lines 330 are crossed with but not perpendicular to the bit lines 320. An acute angle α is contained between the word line 330 and the bit line 320. Furthermore, in the step of word lines 330, firstly, a polysilicon layer is formed on the ONO structure 340, and then part of the polysilicon layer is removed by etching method to form the word lines 330. In the present embodiment of the invention, the acute angle α contained between the word line 330 and the bit line 320 is preferably 45 degrees as shown in FIG. 4A. Thus, the dual bit nitride read only memory 300 is formed as shown in FIG. 5D.
According to the memory and the manufacturing method thereof disclosed in the above embodiment of the invention, the design of having the bit lines be crossed with but not perpendicular to the word lines enables the first bit storage node and the second bit storage node stored in the memory cell to have a larger storage space, hence the concentration of storage electron increases. When the background radiation causes loss to the electrons stored in the memory cell, the decrease in the electron concentration of the memory cell having a high concentration of electron storage is still within a tolerable range. Therefore, the bits stored in the memory cell are still correct and the overall data are free of errors when reading.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Patent Application
20080054322
