Patent Application
20100115213
(A) Field of the Invention
The present invention relates to a memory apparatus and memory management method of the same. More specifically, the memory apparatus is a mixed apparatus including a non-volatile memory and a volatile memory.
(B) Description of Related Art
For a non-volatile memory such as a flash memory, a page is a unit for writing. In other words, a small amount of data or random data can only be written to a non-volatile memory page by page in sequence. Therefore, if an amount of data is less than the capacity of a page, the data is written to the non-volatile memory until the amount of data increases to be of a page.
When the amount of data is less than a smallest writing unit, i.e., a page, or the data is not written in sequence, it may need to find a usable free block. As a result, a block may need to be erased. However, the increase of erasing times will decrease the lifetime of the non-volatile memory.
In practice, the data that cannot be written to the non-volatile memory is temporarily stored in a volatile memory such as a dynamic random access memory (DRAM). The non-volatile memory and the volatile memory constitute a mixed memory apparatus. When the data is accumulated to be of the amount of a page, the data is written to the non-volatile memory.
However, the sequence of the data stored in the volatile memory is random. Therefore, for reading or writing data, it is crucial to generate a method or an algorithm to access the data efficiently.
The present invention provides a memory apparatus having a non-volatile memory and a volatile memory and a method of memory management thereof, so as to effectively search the random and non-sequential entries stored in the volatile memory and/or write a block in the volatile memory to the non-volatile memory when the volatile memory cannot store data anymore.
Viewed from a first aspect, the present invention provides a method of memory management for an apparatus having a non-volatile memory and a volatile memory. The method comprises the steps of forming a tree structure of entries in the volatile memory, in which the tree structure has a left branch and a right branch, and a difference of heights of the left branch and the right branch is equal to or less than one; and accessing an entry in the volatile memory through the tree structure.
Viewed from a second aspect, the present invention provides a method of memory management for an apparatus having a non-volatile memory and a volatile memory. The method comprises the steps of forming a tree structure of entries in the volatile memory, in which the tree structure comprises plural balanced binary trees and is linked to an array recording blocks and roots of the plural balanced binary trees; linking memory addresses corresponding to the blocks in accordance with access sequence as a linked list; obtaining a memory address of an end of the linked list; obtaining a block corresponding to the memory address; and writing entries in the block to the non-volatile memory.
Viewed from a third aspect, the present provides a memory apparatus including a volatile memory, a non-volatile memory and a path selector. The volatile memory has a tree structure of entries in the volatile memory, in which the tree structure has a left branch and a right branch, and a difference of heights of the left branch and the right branch is equal to or less than one, and an entry in the volatile memory is accessed according to the tree structure. The path selector, e.g., a buffer, is configured to select either the volatile memory or the non-volatile memory for storing data.
Embodiments of the present invention will now be described with reference to the accompanying drawings.
Entry is of a fixed unit for data storage in a volatile memory (the data may be from a host), and indicates written positions, e.g., a block (Logic block address; LBA), a page, a partition. Entries in the volatile memory can be written to the non-volatile memory or not.
To read CMD 5, i.e., to read Entry 23, the search goes through the path of Entry 4, Entry 20 to Entry 23. Entry 23 is easily found because the height of the right branch is only two. For such balance binary tree, the time complexity of the tree for searching is of log level. For instance, if the number of entries is 8192, the entry can be searched within 13 times (log 8192=13). In other words, when data access instruction is received, the balanced binary tree undergoes a search to find the right place (entry) to read or write. If other data is written to Entry 23, the Entry 23 will be overwritten.
According to an embodiment of the present invention, a linked-list is provided to record “new” and “old” blocks. More specifically, a block to be accessed lately is deemed a “new” block, whereas a block not to be accessed for a long time is deemed an “old” block. In
When Entries in the volatile memory 12 has no free capacity for storing data, some or all data in a specific Entry needs to be written to the non-volatile memory 11. Because the ends of the linked-list indicate the newest access block and the oldest access block, e.g., block 6 is the oldest and block 5 is the newest in
According to the present invention, the random and non-sequential entries stored in the volatile memory can be effectively searched through a balanced tree. Moreover, a block in the volatile memory can be written to the non-volatile memory efficiently by verifying new and old access blocks.
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.
