Patent Application
20050108461
The present invention relates to a memory apparatus for storing data and relates, in particular, to a data memory apparatus having memory modules which are constructed from at least one database.
Specifically, the present invention relates to a memory apparatus for storing data, said apparatus having a memory module (which has a memory bank), a controller processor unit, a control bus for supplying control signals from the controller processor unit to the memory module, an address bus for supplying addressing signals from the controller processor unit to the memory module and a data bus for interchanging data between the controller processor unit and the memory module.
For the purposes of storing data, a computer system supplies the memory module with addressing data via an address bus and with control data via a control bus. The computer system supplies the memory module with the addressing data and control data both when storing data in, and when reading data from, the memory module. A data bus is used to interchange data between the computer system and the memory module. Memory modules preferably comprise DRAM (Dynamic Random Access Memory) components and are preferably used as main memories in computer systems. Memory modules of this type have the advantage that they can be manufactured at low cost but have the disadvantage that the data stored in the memory modules have to be refreshed in accordance with prescribable refresh cycles (typically 64 ms). Use is currently made of memory modules having 64 data lines, specific memory systems being designed in such a manner that 72 data lines are provided, with 64 data lines being used to transmit the data to be stored and the remaining eight data lines being used for correction logic.
An arrangement of this type comprising memory units and correction logic memory units forms a memory bank. Increasing miniaturization makes it possible to operate, together with a computer system, a plurality of memory banks in a memory module in such a manner that the system's total main memory is increased.
The computer system provides bank selection signals in order to address specific memory banks. If a memory bank (shown in
In conventional computer systems, the bank selection signals are always associated with a specific memory bank.
DE 197 14 952 describes a method for managing memory modules, in which an error log exhibiting a time stamp for errors which occur during normal operation of the memory module is kept in a management memory in the memory module, the management memory permanently storing management information. This makes it possible to permanently store errors in memory modules and error logs but not to eliminate the error without manually exchanging the memory module, i.e. removing the memory module from the system and inserting a sound memory module into the system.
Therefore, it is an object of the present invention to provide a memory apparatus and a method for storing data, in which, once an error has occurred in a memory bank, the original memory size can be restored without exchanging the memory module.
This object is achieved according to the invention by means of a memory apparatus for storing data, said apparatus having the features of patent claim 1.
The object is also achieved by means of a method specified in patent claim 9.
Further refinements of the invention can be found in the subclaims.
A fundamental concept of the invention involves providing redundant memory banks on a memory module. Furthermore, expanding the memory module with a configurable logic unit makes it possible to combine existing bank selection signals in such a manner that one of the redundant memory banks in the memory module can be addressed, in particular when one of the memory banks which is in operation exhibitsan error.
The memory module is therefore expanded, said expansion making it possible to flexibly assign different memory banks in a memory module to the addressing options which can be selected in a system.
A fundamental advantage of the present invention is thus that the reliability of the overall system can be increased. The increasing technological miniaturization advantageously makes it possible to accommodate a plurality of memory banks in a memory module. Components are thus placed, for example, on both sides or above one another in such a manner that numerous memory banks can be accommodated in a memory module.
A computer system can normally support only a particular prescribed number of memory banks; the invention provides the memory module with a number of memory banks which exceeds the number of memory banks which can be supported.
A number of redundant memory banks which, in the event of an error occurring, can replace a defective memory bank are obtained in this manner.
A further advantage of the present invention is that the memory module is expanded in a form such that there is no need for any additional lines from the memory module to the computer system or to a controller processor unit. It is thus expedient that the inventive memory apparatus and the inventive method can be used in any conventional computer system. An interface to a computer system which is being used advantageously remains unchanged.
The advantage of the invention is, in particular, that the reliability of safety/security-critical computer systems is drastically increased, since it is possible to access redundant memory banks in memory modules. Furthermore, the inventive method makes it possible to repair memory modules without manual intervention or exchanging individual memory modules. An advantage of the present invention is, in particular, that the reliability of the overall system is increased.
The inventive memory apparatus for storing data essentially has:
Furthermore, the inventive method for storing data essentially has the following steps:
The subclaims contain advantageous developments and improvements of the respective subject matter of the invention.
In line with one preferred development of the present invention, the controller processor unit has a test mode unit which is supplied with control signals via the control bus and with addressing signals via the address bus and which, on the basis of the control and addressing signals supplied, outputs a combinational logic signal for determining a logic combination for the bank selection signals.
In line with another preferred development of the present invention, the controller processor unit has a selection unit for selecting at least one memory bank in the memory module, the combinational logic signal output by the test mode unit and the bank selection signals being supplied to the selection unit.
In line with yet another preferred development of the present invention, the selection unit for selecting at least one memory bank in the memory module is formed by a logic circuit. The logic circuit in the selection unit for selecting at least one memory bank in the memory module is preferably constructed from NAND functions.
In line with yet another preferred development of the present invention, the at least one memory bank in the memory module is constructed from memory units.
In line with yet another preferred development of the present invention, the test mode unit and/or the selection unit is/are integrated, together with the memory module, in a single unit. The test mode unit and/or the selection unit is/are preferably located, together with the memory module, in the computer system or controller processor unit.
In line with yet another preferred development of the present invention, the controller processor unit provides a number of two bank selection signals for selecting at least a number of four memory banks.
In line with yet another preferred development of the present invention, the combinational logic signal output by the test mode unit and the bank selection signals are supplied, for a combinational logic operation, to the selection unit for selecting at least one memory bank in the memory module.
In line with yet another preferred development of the present invention, a test mode is used to assign the bank selection signals to at least one memory bank.
In line with yet another preferred development of the present invention, the controller processor system reacts dynamically to faulty memory banks and replaces them in the event ofan error.
Exemplary embodiments of the invention are explained in more detail in the description below and are shown in the drawings, in which:
In the figures, the same reference symbols denote the same components or steps; or components or steps having the same function.
The control bus 104 is used to supply control signals from the controller processor unit 102 to the memory module 100, while the address bus 105 is used to supply addressing signals from the controller processor unit 102 to the memory module 100 in order to prescribe memory addresses when storing and/or reading data.
The data bus 106 is used to interchange data between the controller processor unit and the memory module.
The inventive memory apparatus has a memory module 100 which, in addition to a customary memory bank 101a (dot-dashed line), has at least one further memory bank 101b (. . . 101n) which is indicated by the dotted line. Bank selection signals 205a, 205b are supplied to the memory banks. It is conceivable, in principle, to supply each memory bank with its own bank selection signal 205a-205n. However, computer systems usually provide two bank selection signals 205a, 205b such that further memory banks can be addressed only by means of a logic selection unit (described below with reference to
Bank selection lines 204a, 204b are used for this purpose. Expanding the memory module in this manner now makes it possible to address different memory banks 101b-101c in addition to an already existing memory bank 101a. This results in a flexible assignment capability, as will be explained below with reference to
The following table shows an example of a logic combination for two bank selection signals 201a, 201b (which are denoted CS1, CS2 in the table) in order to address corresponding memory banks 101a-101n in a memory module 100, the numbers 1 . . . 4 being used to denote the memory banks in table 1.
Table 1 illustrates the rectification of a faulty state caused byan error in the memory bank 2. In a basic state of the memory apparatus, a bank selection signal CS1 activates the memory bank 1, while a bank selection signal CS2 activates the memory bank 2. By way of example, a correction logic unit has used parity tests, for example, to determinean error in the memory bank 2 in such a manner that the bank selection signal CS2 is now assigned to the memory bank 3 on the basis of the combinational logic signal 206. The memory bank 4 listed in table 1 continues to be available as a redundant memory bank, while the memory bank 2 is no longer addressed by the system, since it exhibitsan error.
Therefore, the advantage of the present invention can clearly be seen such that the controller processor system 102 can react dynamically to faulty memory banks, it being possible to replace faulty memory banks with sound memory banks at any time provided that there is sufficient redundancy in the system, i.e. provided that there are enough sound memory banks in the memory module 100. Increasing miniaturization of memory components makes it possible in any case to realize a plurality of memory banks in a memory module.
The bank selection signal 205a is supplied to the selection unit 203 via the bank selection line 204a, while the bank selection signal 205b is supplied to the selection unit 203 via the bank selection line 204b.
It should be pointed out that the selection unit 203 contains a logic circuit for logically combining the signals which have been supplied, i.e. the combinational logic signal 206 and the corresponding bank selection signals 205a, 205b, logic circuits of this type being formed, for example, by means of NAND functions, as are known by those skilled in the art. Memory modules usually have 72 data lines, eight of which are used by the computer system for parity checks.
This ensures that data are not changed when transmitted between the memory module 100 and the computer system or controller processor unit 102, or in the memory module 100 itself. In the event of an error, the system can repeat a storage operation. It is furthermore possible to react dynamically to faulty memory banks in such a manner that, when the system establishes that the number of data errors occurring is increasing, a faulty memory bank is determined.
When a prescribed number oferrors has been exceeded, the system can automatically replace the faulty memory bank with a redundant memory bank. In this case, there is advantageously no need for external intervention, thus increasing the reliability of the overall system. This increases system reliability without having to increase the number of bank selection signals.
Reference is made to the introduction to the description with regard to the conventional memory apparatus shown in
Although the present invention was described above with reference to preferred exemplary embodiments, it is not restricted thereto but rather can be modified multifariously.
Nor is the invention restricted to the application options mentioned.
List of Reference Symbols
In the figures, the same reference symbols denote the same components or steps, or components or steps having the same function.
| Number | Date | Country | Kind |
|---|---|---|---|
| 103 45 978.2 | Oct 2003 | DE | national |
