Memory arbitration system and method having an arbitration packet protocol

Abstract

A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Description

TECHNICAL FIELD

This present invention is related generally to a memory system for a processor-based computing system, and more particularly, to a hub-based memory system having an arbitration system and method for managing memory responses therein.

BACKGROUND OF THE INVENTION

Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The memory devices of the system memory, typically arranged in memory modules having multiple memory devices, are coupled through a memory bus to the memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory through the memory bus. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.

In memory systems, high data bandwidth is desirable. Generally, bandwidth limitations are not related to the memory controllers since the memory controllers sequence data to and from the system memory as fast as the memory devices allow. One approach that has been taken to increase bandwidth is to increase the speed of the memory data bus coupling the memory controller to the memory devices. Thus, the same amount of information can be moved over the memory data bus in less time. However, despite increasing memory data bus speeds, a corresponding increase in bandwidth does not result. One reason for the non-linear relationship between data bus speed and bandwidth is the hardware limitations within the memory devices themselves. That is, the memory controller has to schedule all memory commands to the memory devices such that the hardware limitations are honored. Although these hardware limitations can be reduced to some degree through the design of the memory device, a compromise must be made because reducing the hardware limitations typically adds cost, power, and/or size to the memory devices, all of which are undesirable alternatives. Thus, given these constraints, although h is easy for memory devices to move “well-behaved” traffic at ever increasing rates, for example, sequel traffic to the same page of a memory device, it is much more difficult for the memory devices to resolve “badly-behaved traffic,” such as bouncing between different pages or banks of the memory device. As a result, the increase in memory data bus bandwidth does not yield a corresponding increase in information bandwidth.

In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data are output from the SDRAM device only after a delay of several clock periods. Therefore, although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices. Increasing the memory data bus speed can be used to help alleviate the latency issue. However, as with bandwidth, the increase in memory data bus speeds do not yield a linear reduction of latency, for essentially the same reasons previously discussed.

Although increasing memory data bus speed has, to some degree, been successful in increasing bandwidth and reducing latency, other issues are raised by this approach. For example, as the speed of the memory data bus increases, loading on the memory bus needs to be decreased in order to maintain signal integrity since traditionally, there has only been wire between the memory controller and the memory slots into which the memory modules are plugged. Several approaches have been taken to accommodate the increase in memory data bus speed. For example, reducing the number of memory slots, adding buffer circuits on a memory module in order to provide sufficient fanout of control signals to the memory devices on the memory module, and providing multiple memory device interfaces on the memory module since there are too few memory module connectors on a single memory device interface. The effectiveness of these conventional approaches are, however, limited. A reason why these techniques were used in the past is that it was cost-effective to do so. However, when only one memory module can be plugged in per interface, it becomes too costly to add a separate memory interface for each required memory slot. In other words, it pushes the system controllers package out of the commodity range and into the boutique range, thereby, greatly adding cost.

One recent approach that allows for increased memory data bus speed in a cost effective manner is the use of multiple memory devices coupled to the processor through a memory hub. In a memory hub architecture, or a hub-based memory sub-system, a system controller or memory controller is coupled over a high speed bi-directional or unidirectional memory controller/hub interface to several memory modules. Typically, the memory modules axe coupled in a point-to-point or daisy chain architecture such that the memory modules are connected one to another in series. Thus, the memory controller is coupled to a first memory module, with the first memory module connected to a second memory module, and the second memory module coupled to a third memory module, and so on in a daisy chain fashion.

Each memory module includes a memory hub that is coupled to the memory controller/hub interface and a number of memory devices on the module, with the memory hubs efficiently routing memory requests and responses between the controller and the memory devices over the memory controller/hub interface. Computer systems employing this architecture can use a high-speed memory data bus since signal integrity can be maintained on the memory data bus. Moreover, this architecture also provides for easy expansion of the system memory without concern for degradation in signal quality as more memory modules are added, such as occurs in conventional memory bus architectures.

Although computer systems using memory hubs can provide superior performance, various factors may affect the performance of the memory system. For example, the manner in which the flow of read data upstream (i.e., back to the memory hob controller in the computer system) from one memory hub to another is managed will affect read latency. The management of the flow of read data by a memory hub may be generally referred to as arbitration, with each memory hub arbitrating between local memory read responses and upstream memory read responses. That is, each memory hub determines whether to send local memory read responses first or to forward memory read responses from downstream (i.e., further away from the memory hub controller) memory hubs first. Although the determination of which memory read response has lower priority will only affect the latency of that specific memory read response, the additive effect of the memory read responses having increased latency will affect the overall latency of the memory system. Consequently, the arbitration technique employed by a memory hub directly affects the performance of the overall memory system. Additionally, the implementation of the arbitration scheme will affect the overall read latency as well, since inefficient implementation will negatively impact system memory performance despite utilizing a desirable arbitration scheme. Therefore, there is a need for a system and method for implementing an arbitration scheme for managing memory responses in a system memory having a memory hub architecture.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial block diagram of a computer system having a memory hub based system memory in which embodiments of the present invention can be implemented.

FIG. 2 is a functional block diagram of an arbitration control component according to an embodiment of the present invention that can be utilized in the memory hubs of FIG. 1.

FIG. 3 is a data structure diagram of an arbitration packet and memory response according to an embodiment of the present invention.

FIGS. 4A and 4B show flow diagrams of the operation of the arbitration control component of FIG. 2 according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 illustrates a computer system 300 having a memory hub architecture in which embodiments of the present invention can be utilized. The computer system 100 includes a processor 104 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 104 includes a processor bus 106 that normally includes an address bus, a control bus, and a data bus. The processor bus 106 is typically coupled to cache memory 108, which, is typically static random access memory (“SRAM”). The processor bus 106 is further coupled to a system controller 110, which is also referred to as a bus bridge.

The system controller 110 also serves as a communications path to the processor 104 for a variety of other components. More specifically, the system controller 110 includes a graphics port that is typically coupled to a graphics controller 112, which is, in turn, coupled to a video terminal 114. The system controller 110 is also coupled to one or more input devices 118, such as a keyboard or a mouse, to allow an operator to interface with the computer system 100. Typically, the computer system 100 also includes one or more output devices 120, such as a printer, coupled to the processor 104 through the system controller 110. One or more data storage devices 124 are also typically coupled to the processor 104 through the system controller 110 to allow the processor 104 to store data or retrieve data from internal or external storage media (not shown). Examples of typical storage devices 124 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs).

The system controller 110 contains a memory hub controller 128 coupled to several memory modules 130a-n through a bus system 154, 156. Each of the memory modules 130a-n includes a memory hub 140 coupled to several memory devices 148 through command, address and data buses, collectively shown as bus 150. The memory hub 140 efficiently routes memory requests and responses between the controller 128 and the memory devices 148. Each of the memory hubs 140 includes write buffers and read data buffers. Computer systems employing this architecture allow for the processor 104 to access one memory module 130a-n while another memory module 130a-n is responding to a prior memory request. For example, the processor 104 can output write data to one of the memory modules 130a-n in the system while another memory module 130a-n In the system is preparing to provide read data to the processor 104. Additionally, a memory hub architecture can also provide greatly increased memory capacity in computer systems.

FIG. 2 is a functional block diagram illustrating an arbitration control component 200 according to one embodiment of the present invention. The arbitration control component 200 can be included in the memory hubs 140 of FIG. 1. As shown in FIG. 2, the arbitration control component 200 includes two queues for storing associated memory responses. A local response queue 202 receives and stores local memory responses LMR from the memory devices 148 on the associated memory module 130. A remote response queue 206 receives and stores downstream memory responses which cannot be immediately forwarded upstream through a bypass path 204. An arbitration control circuit 210 is coupled to the queues 202, 206 through a control/status bus 136, which allows the arbitration control circuit 210 to monitor the contents of each of the queues 202, 206, and utilizes this information in controlling a multiplexer 208 to thereby control the overall arbitration process executed by the memory hub 140. The control/status bus 136 also allows “handshaking” signals to be coupled from the queues 202, 206 to the arbitration control circuit 210 to coordinate the transfer of control signals from the arbitration control circuit 210 to the queues 202, 206.

The arbitration control circuit 210 is further coupled to the high-speed, link 134 to receive arbitration packets from downstream memory hubs. As will be explained in more detail below, arbitration packets are provided in advance of an associated memory response, and provide the arbitration control circuit 210 of an upstream memory hub with information to enable the appropriate path through the receiving memory hub in anticipation of receiving the associated memory response. Additionally, the arbitration control circuit 210 generates an arbitration packet to be provided prior to an associated LMR to serve as an early indication of the associated memory response when data is read from the memory devices 148 (FIG. 1) in response to a read request. As previously discussed, the arbitration packet will provide upstream memory hubs with appropriate information and give the respective arbitration control circuits 210 time to make decisions regarding enablement of the appropriate data paths before the memory response arrives. The arbitration control circuit 210 prepares the arbitration packet while read data for the memory response is being retrieved from memory devices 148. The arbitration packet is provided through a switch 212 to either the multiplexer 208 or the local response queue 202, depending on whether if the upstream memory hub is idle or busy. The multiplexer 208, under the control of the arbitration control circuit, couples the high-speed link 134 to receive memory responses from the remote response queue 206 or the bypass path 204, arbitration packets from the arbitration control circuit 210, or arbitration packets and memory responses from the local response queue 202. In an alternative embodiment of the present invention, the arbitration packets are generated in an arbitration packet circuit, rather than in the arbitration control circuit 210, as shown in FIG. 2. Additionally, although shown in FIG. 2 as providing the arbitration packet to the multiplexer 208 to be injected into the stream of data, the arbitration packet can alternatively be provided to the local response queue 202 and placed before the associated read response packet to be injected into the data stream. It will be appreciated by those ordinarily skilled in the art that modifications to the embodiments of the present invention, such as the location at which the arbitration packet is generated or the manner in which the arbitration, packet is placed into the data stream prior to the associated read packet, can be made without departing from the scope of the present invention.

FIG. 3 illustrates a data structure 300 for arbitration packets and memory responses according to an embodiment of the present invention. The data structure 300 is divided into 8-bit bytes of information, with each byte of information corresponding to a sequential bit-time. Each bit-time represents an increment of time in which new data can be provided. A response header field 302 includes two bytes of data that indicate the response is either an arbitration packet or a memory response. An address field 304 includes data that is used to identify the particular hub to which the arbitration packet or memory response is directed. A command code field 306 will have a value to identity the data structure 300 as an arbitration packet, and not as a memory response. Arbitration packets and memory responses are similar, except that the data pay load of data fields 308 are “don't cares” for arbitration packets. In the data structure 300, all 16 bits of size fields 310 carry the same value to indicate the size of the data, payload carried by the memory response. For example, a “0” indicates that 32 bytes of data are included, and a “1” indicates that 64 bytes of data are included. It will be appreciated by one ordinarily skilled in the art that the embodiment of the data structure 300 shown in FIG. 3 has been provided by way of example, and that modifications to the data structure 300 can be made without deviating from the scope of the present invention. For example, the number and type of data fields of the data structure 300 can be changed or the number of bits for each bit time can be changed and still remain within the scope of the present invention.

Operation of the arbitration control component 200 (FIG. 2) will be described with reference to the flow diagrams of FIGS. 4A and 4B. Following the receipt of a read data command, at a step 402 the memory hub initiates a read operation to retrieve the requested read data from the memory devices 148 (FIG. 1) for the memory response that will be provided to the requesting target. At a step 404, the arbitration control circuit 210 of the memory hub determines whether the local data path is idle by checking the status of the local response queue 202. If the local data path is idle, an arbitration packet is generated by the arbitrations control circuit 210 during the retrieval of the read data from the memory devices 148 at a step 406. When the arbitration packet and the memory response have been prepared, and are ready for transmission, at a step 408 an upstream memory hub is queried to determine if it is busy. Where the upstream memory hub is idle, the arbitration packet is sent to the upstream memory hub, followed by the memory response at steps 410, 412. However, if the upstream memory hub is busy, the arbitration packet is discarded at a step 414 and the memory response is stored in a local response queue 202 at a step 416. Similarly, in the event that at the step 404 it was determined that, the local data path is busy, the memory response is also stored in the local response queue at the step 416. At a step 418 the memory response is stored in the local response queue 202 until it is selected for transmission to the upstream memory hub in accordance with an arbitration scheme implemented by the memory hub. At a step 420, the memory response is transmitted through each upstream memory hub in accordance with the arbitration scheme until the memory response reaches the target destination. Suitable arbitration schemes are well known in the art, and will not be described in detail herein. An example of an arbitration scheme that is also suitable for use is described in more detail in commonly assigned, co-pending U.S. patent application Ser. No. 10/690,810, entitled ARBITRATION SYSTEM AND METHOD FOR MEMORY RESPONSES IN A HUB-BASED MEMORY SYSTEM to lames W. Meyer and Cory Kanski, filed on Oct. 20, 2003, which is incorporated herein by reference.

As described therein, the local and remote response queues 202, 206 and the bypass path 204 are utilized to implement various response arbitration schemes. For example, in one embodiment, the arbitration control circuit executes an arbitration scheme that gives downstream responses, or remote responses, priority over local, responses. Alternatively, in another embodiment described, the arbitration control circuit executes an arbitration scheme that gives priority to local responses over downstream responses. In another embodiment, the arbitration control circuit alternates between a predetermined number of responses from local and downstream memory, for example, local and remote responses can be alternately forwarded, or two local responses are forwarded followed by two remote responses, and so on. Another embodiment described therein utilizes an oldest first algorithm in arbitrating between local and downstream memory responses. That is, in operation, the arbitration control circuit 210 monitors response identifier portions of the memory responses stored in the local response queue and the remote response queue and selects the oldest response contained in either of these queues as the next response to be forwarded upstream. Thus, independent of the response queue in which a memory response is stored, the arbitration control circuit forwards the oldest responses first.

It will be appreciated by those ordinarily skilled in the art that other arbitration methods and schemes can be utilized without departing from the scope of the present invention.

Returning to the steps 410, 412 where the arbitration packet is first transmitted to an upstream memory hub and then followed by the memory response, the arbitration control circuit 210 of the upstream memory hub receives the arbitration packet at a step 422. The arbitration packet is decoded, and the appropriate data path is enabled by the arbitration control circuit 210 based on the information decoded at steps 424, 426. By the time the memory response is received at a step 430, the appropriate data path is enabled by the arbitration control circuit 210. At a step 428, the next upstream memory hub is queried to determine if it is busy. If not, the arbitration packet and then the memory response are transmitted to the next upstream memory hub in a bypass fashion at a step 432. The transmission of the arbitration packet and the memory response in the bypass fashion is facilitated by enabling the appropriate data path through the memory hub based on the decoded information of the arbitration packet that is sent at the step 410 before the associated memory response is sent at the step 412.

Returning to the step 428, if it is determined that the next upstream memory hub is busy, the arbitration packet is discarded at the step 440, and the memory response is stored in the remote response queue 206 until the memory response is selected for transmission to the next upstream memory hub according to the arbitration scheme employed at a step 442. At the step 420, the memory response will make its way upstream through the memory hubs in accordance with the arbitration scheme until reaching its target destination.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention, for example, embodiments of the present invention have been described herein with respect to a memory hub-based system memory used in a computer system. However, it will be appreciated that embodiments of the present invention can be used in memory systems other than hub-based memory systems, where appropriate. Moreover, embodiments of the present invention can also be used in memory hub-based systems that are utilized in processor based systems, as known, in the art, other than computer systems. Accordingly, the invention is not limited except as by the appended claims.

Claims

1. An apparatus, comprising: a first memory hub coupled to a memory device, the first memory hub configured to, responsive to a read request, retrieve read data from the memory device based on the read request and generate arbitration data associated with the read request, wherein generation of the arbitration data at least partially overlaps with retrieval of the read data from the memory device, the first memory hub further configured to provide the arbitration data to a second memory hub, the first memory hub further configured to provide the read data to the second memory hub after provision of the arbitration data.

2. The apparatus of claim 1, wherein the first memory hub comprises arbitration control circuit that is configured to generate the arbitration data.

3. The apparatus of claim 2, wherein the first memory hub further comprises a configurable data path, where the arbitration control circuit is configured to configure the configurable data path to provide the arbitration data associated with the read request to the second memory hub.

4. The apparatus of claim 3, wherein the arbitration control circuit is further configured to configure the configurable data path to provide the read data to the second memory hub.

5. The apparatus of claim 3, wherein the first memory hub is further configured to receive data from a third memory hub and to provide the arbitration data from the third memory hub to the second memory hub via the configurable data path based on a status of the second memory hub.

6. The apparatus of claim 1, wherein the arbitration control circuit is further configured to determine whether the second memory hub is idle.

7. A system, comprising: a system controller configured to provide a read request;a plurality of memory modules coupled to the system controller, a memory module of the plurality of memory modules including a respective memory hub and a respective plurality of memory devices, the memory huh configured to receive the read request, the memory hub further configured to, responsive to the read request, retrieve read data from at least one of the plurality of memory devices based on the read request and generate arbitration data associated with the read request, wherein generation of the arbitration data at least partially overlaps with retrieval of the read data, the memory hub further configured to provide the arbitration data to another memory hub of another memory module of the plurality of memory modules, the memory hub further configured to provide the read data to the another memory hub after provision of the arbitration data.

8. The system of claim 7, wherein the memory hub is further configured to query the another memory hub to determine whether the another memory hub is idle.

9. The system of claim 7, wherein the memory hub is further configured to provide the read data to the another memory hub when the another memory hub is idle.

10. The system of claim 7, wherein the memory hub comprises a buffer that is configured to store the read data.

11. The system of claim 7, wherein the memory hub is further configured to receive arbitration data from a previous memory hub of a previous memory module of the plurality of memory modules, wherein the memory hub comprises a bypass path that is configured to provide the arbitration data from the previous memory hub to the another memory hub when the another memory hub is idle.

12. The system of claim 11, wherein the memory hub comprises a buffer that is configured to store the arbitration data from the previous memory hub when the another memory hub is busy.

13. An apparatus coupled to at least one memory, the apparatus comprising: remote and local input nodes;an output node;a configurable data path coupled to the remote and local input nodes and further coupled to the output node, the configurable data path operable to couple at least one read response received by the remote and local input nodes to the output node; andan arbitration control circuit coupled to the configurable data path, the output node, and the remote and local input nodes, the arbitration control circuit configured to generate an arbitration packet that includes data indicative of a data path configuration for a local read response received by the local input node, wherein generation of the arbitration packet at least partially occurs during a time when read data associated with the local read response is being retrieved from the at least one memory, the arbitration control circuit further configured to provide the arbitration packet to the output node prior to providing, the local read response to the output node.

14. The apparatus of claim 13, wherein the configurable data path comprises: a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit;a bypass data path coupled to the remote input node and a first input of the multiplexer;a local queue having an input coupled to the local, input node and further having an output coupled to a second input of the multiplexer; anda remote queue having an input coupled to the remote input node and further having an output coupled to a third input of the multiplexer.

15. The apparatus of claim 14, wherein the arbitration control circuit is configured to store the local read response received by the local input node in the local queue and a downstream read response in the remote queue until the output node is ready to receive a read response.

16. The apparatus of claim 13, wherein the arbitration control circuit is configured to determine whether a local data path of the apparatus coupled to the local input node is idle, and in response to the local data path being idle, the arbitration control circuit is configured to generate the arbitration packet for the local read response received by the local input node.

17. The apparatus of claim 16, wherein the arbitration packet and the local read response of the local data path is selected for transmission to the output node responsive to a predetermined arbitration scheme.

18. The apparatus of claim 13, wherein the arbitration control circuit is further operable to generate data for the arbitration packet that is used to distinguish the arbitration packet from a read response.

19. The apparatus of claim 18, wherein the data for the arbitration packet used to distinguish the arbitration packet from the read response includes a single byte of data used to distinguish the arbitration packet from the read response.

20. A hub, comprising: a bypass data path coupled between an input node and an output node on which read responses are applied in response to being enabled; andan arbitration control circuit coupled to the bypass data path operable to receive an arbitration packet from a downstream hub and enable the bypass data path to receive a read response from the downstream hub responsive to the received arbitration packet, the arbitration packet including a data path field having activation data to enable the bypass data path of an upstream hub.

21. The hub of claim 20, further comprising: a switch coupled to the arbitration control circuit, and configured to receive arbitration packets from the arbitration control circuit;a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit, the multiplexer further having a first input coupled to the bypass data path and a second input coupled to the switch;a local queue coupled to the switch, and having an input coupled to a local input node and further having an output coupled to a third input of the multiplexer; anda remote queue having an input coupled to the input node and further having an output coupled to a fourth input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

22. The hub of claim 21, wherein the arbitration control circuit is configured to store the read response received from the downstream hub in the remote queue when the upstream hub is busy.

23. The hub of claim 21, wherein the arbitration control circuit is configured to store read data from a memory device coupled to the hub in the local queue, and generate an arbitration packet in response to the received read data when the upstream hub is not busy.

24. The hub of claim 21, wherein the switch is configured to provide the arbitration packet to the multiplexer or the local queue based at least in part on whether the upstream hub is idle or busy.