The present invention generally relates to a memory architecture for the Viterbi decoder and an operating method therefor and, more particularly, to a power efficient low latency survivor memory architecture for the Viterbi decoder and an operating method for the memory architecture.
The convolutional code has been widely used in communication systems to reduce transmission error. Among convolutional code decoding methods, the Viterbi algorithm is one with the maximum likelihood. More particularly, the survivor memory unit is the key part of the Viterbi decoder, upon which the decoding latency and the power consumption depend.
The Viterbi algorithm uses data matching to generate the survivor path for each state. As the data exceeds a certain amount, all the survivor paths converge to a correct solution. Meanwhile, the amount of data is referred to as a decoding length. The survivor memory unit (SMU) stores the survivor path to perform decoding after the decoding length is exceeded. Generally, the survivor memory architecture comprises two architectures as described hereinafter.
1. Register Exchange (RE) Architecture:
In a RE architecture, the registers are connected according to the trellis diagram of the convolutional encoder to perform data exchange according to the decision bits generated by an add-compare-select unit (ACSU). For detailed description,
2. Trace-Back (TB) Architecture:
Write: Writing the decision bits into the memory unit in a time order;
Trace-Back: Reading the decision bits in a trace-back approach from a position where a last data is written so as to obtain a last convergence state;
Idle: The memory unit idle; and
Decode: reading survivor path information from the convergence state to perform decoding.
Since the wireless communication industry is continuously growing and the design of most transceivers is focused upon the reduction of power consumption, most of the Viterbi decoders used in transceivers use the trace-back approach for decoding. Therefore, there is need in providing a power efficient low latency survivor memory architecture for the Viterbi decoder and an operating method for the memory architecture to reduce power consumption of the Viterbi decoder by decreasing the exchange times of contents in the trace-forward units.
One aspect of the invention to provide a memory architecture for the Viterbi decoder and an operating method thereof, being capable of reducing the power consumption and the decoding latency.
This aspect of the invention provides a memory architecture for the Viterbi decoder. The memory architecture has
a plurality of trace-forward units, capable of receiving a switching signal and a decision bit sequence respectively and generating a plurality of state signals according to the received decision bit sequence when the received switching signal is a turn-on signal; and a signal selecting unit, being electrically connected to the trace-forward units.
The signal selecting unit outputs a desired state bit sequence according to the state signals, a second decision signal, an initial state bit sequence and a last state bit sequence.
Another aspect of the invention further provides an operating method for a memory architecture for the Viterbi decoder. The operating method comprises:
(1) enabling each of a plurality of trace-forward units to receive a switching signal respectively, wherein one of the trace-forward units generates a plurality of state signals according to a received decision bit sequence when the switching signal is a turn-on signal, while the rest of the trace-forward units remain their original states;
(2) enabling a signal selecting unit to output a desired state bit sequence according to the state signals, a second decision signal, an initial state bit sequence and a last state bit sequence; and
(3) enabling the switching signal of a currently operating one of the trace-forward units to be a turn-off signal and enabling the switching signal of a next one of the trace-forward units to be a turn-on signal so as to go to step (1).
Thereby, the exchange times of contents in the trace-forward units are decreased to reduce the power consumption of the Viterbi decoder so that the problems in the conventional architecture and the operating method are overcome.
The objects, spirits and advantages of the embodiment of the present invention will be readily understood by the accompanying drawings and detailed descriptions, wherein:
The present invention can be exemplified but not limited by the embodiment as described hereinafter.
The number of the trace-forward units 200-20n is not restricted. Each of the trace-forward units 200-20n receives a switching signal enable(1)-enable(k) and a decision bit sequence respectively, and generates a plurality of state signals according to the received decision bit sequence when the received switching signal is a turn-on signal. One of the switching signals is a turn-on signal while the rest of the switching signals are turn-off signals so that only one of the trace-forward units 200-20n is operating, which reduces the power consumption. The number of the bits in the decision bit sequence is not restricted.
The signal selecting unit comprising a plurality of first signal selecting units 300-30n, a plurality of second signal selecting units 400-40n and a third signal selecting unit 500. The first signal selecting units 300-30n are exemplified by and not restricted to multiplexers. The number of the first signal selecting units is not restricted. The first signal selecting units 300-30n are electrically connected to the trace-forward units 200-20n respectively. The first signal selecting units 300-30n receive the state signals respectively and select one from the state signals according to a first decision signal respectively.
The second signal selecting units 400-40n are exemplified by and not restricted to multiplexers. Similarly, the number of the second signal selecting units is not restricted. The second signal selecting units 400-40n are electrically connected to the first signal selecting units 300-30n respectively. The second signal selecting units 400-40n receive the initial state bit sequence and the state signals from the next first signal selecting units respectively, and select one from the state signals from the initial state bit sequence and the next first signal selecting units as the first decision signal output according to the second decision signal respectively. The number of bits in the initial state bit sequence is not restricted.
The third signal selecting unit 500 is exemplified by and not restricted to a multiplexer. The third signal selecting unit 500 is electrically connected to the first signal selecting units 300-30n. The third signal selecting unit 500 receives the state signals selected and output by the first signal selecting units 300-30n, and selects one from the state signals selected and output by the first signal selecting units 300-30n as the desired state bit sequence according to the last state bit sequence.
In Step (1), each of a plurality of trace-forward units receives a switching signal respectively, wherein one of the trace-forward units generates a plurality of state signals according to a received decision bit sequence when the switching signal is a turn-on signal, while the rest of the trace-forward units remain their original states. One of the switching signals is a turn-on signal while the rest of the switching signals are turn-off signals so that only one of the trace-forward units is operating, which reduces the power consumption. The number of the trace-forward units is not restricted, and neither is the number of the bits in the decision bit sequence.
In Step (2), the first signal selecting units (exemplified by and not limited to multiplexers) receive the state signals respectively and select one from the state signals according to a first decision signal respectively. The number of the first signal selecting units is not restricted.
In Step (3), the second signal selecting units (exemplified by and not limited to multiplexers) receive the initial state bit sequence and the state signals from the next first signal selecting units respectively, and select one from the state signals from the initial state bit sequence and the next first signal selecting units as the first decision signal output according to the second decision signal respectively. The number of the second signal selecting units is not restricted, and neither is the number of the bits in the initial state bit sequence.
In Step (4), the third signal selecting unit (exemplified by and not limited to a multiplexer) receives the state signals selected and output by the first signal selecting units, and selects one from the state signals selected and output by the first signal selecting units as the desired state bit sequence according to the last state bit sequence.
In Step (5), the switching signal of a currently operating one of the trace-forward units is a turn-off signal and the switching signal of a next one of the trace-forward units is a turn-on signal so as to go to step (1).
Accordingly, the present invention discloses a memory architecture for the Viterbi decoder and an operating method for the memory architecture to reduce power consumption of the Viterbi decoder by decreasing the exchange times of contents in the trace-forward units. Therefore, the present invention is useful, novel and non-obvious.
Although this invention has been disclosed and illustrated with reference to particular embodiments, the principles involved are susceptible for use in numerous other embodiments that will be apparent to persons skilled in the art. This invention is, therefore, to be limited only as indicated by the scope of the appended claims.
Number | Date | Country | Kind |
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096151390 | Dec 2007 | TW | national |