Patent Application
20240274064
Reference is made to U.S. patent application Ser. No. 17/730,593 filed Apr. 22, 2022, entitled Multi-Row Bufferingfor Active-Matrix Cluster Displays by Cok, the disclosure of which is incorporated by reference herein in its entirety.
The present disclosure relates to display memory architectures having active-matrix cluster controllers for groups of pixels. The pixels in each group are controlled using passive-matrix control.
Flat-panel displays are widely used in conjunction with computing devices, in portable electronic devices, and for entertainment devices such as televisions. Such displays typically employ an array of pixels distributed over and on a display substrate to display images, graphics, or text. In a color display, each pixel includes light emitters that emit light of different colors, such as red, green, and blue. For example, liquid crystal displays (LCDs) employ liquid crystals to block or transmit light from a backlight behind the liquid crystals and organic light-emitting diode (OLED) displays rely on passing current through a layer of organic material that glows in response to the current. Displays using inorganic light-emitting diodes (LEDs) as pixel elements are also in widespread use for outdoor signage and have been demonstrated in a 55-inch television.
Displays are typically controlled with either a passive-matrix (PM) control scheme employing only electronic control circuitry external to the pixel array or an active-matrix (AM) control scheme employing electronic control circuitry in the pixels on the display substrate and associated with each light-emitting element. Both OLED displays and LCDs using passive-matrix control and active-matrix control are available. An example of such an AM OLED display device is disclosed in U.S. Pat. No. 5,550,066.
In a PM-controlled display, each pixel in a row is stimulated to emit light at the same time while the pixels in the other rows do not emit light and each row is sequentially activated at a high rate to provide the visual illusion that all of the rows or pixels simultaneously emit light. Because of the high rate (refresh) requirement, PM displays are typically limited in size (area) and in the number of pixel rows. In contrast, in an AM-controlled display, data is concurrently provided to and stored in pixels in a row and the rows are sequentially selected to load the data in the selected row. Each pixel emits light corresponding to the stored data when pixels in other rows receive data so that all of the rows of pixels in the display emit light at the same time, except possibly the row loading pixels. In such AM systems, the row activation rate can be much slower than in PM systems, for example divided by the number of rows. Control of the light-emitting elements is usually provided through a data signal line (display column wire), a select signal line (display row wire), a power connection, and a ground connection. AM displays are often much larger in area and number of pixels than PM displays.
In a conventional AM display, each display sub-pixel (e.g., light emitter) is controlled by one control element, and each control element includes at least one transistor. For example, in a simple active-matrix organic light-emitting diode (OLED) analog display, each control element includes two transistors (a select transistor and a power driving transistor) and one capacitor for storing a charge specifying the luminance of the light emitter. Each OLED element employs an independent control electrode connected to the power transistor and a common electrode. In contrast, an LCD typically uses a single transistor to control each pixel. Such circuits can be expensive and require significant area on a display substrate, especially for thin-film circuits on the substrate of a flat-panel display.
U.S. Pat. No. 8,207,954 filed Nov. 17, 2008, entitled Display Device with Chiplets and Hybrid Drive by Cok et al. describes a display device comprising a two-dimensional array of pixels associated into a plurality of pixel groups. A separate set of group row electrodes and group column electrodes are connected to pixels in each pixel group and are controlled by two or more chiplets within the pixel array. The chiplets have storage elements storing a value representing a desired luminance for each pixel.
There remains a need for display systems that provide improved efficiency and performance with reduced costs.
The present disclosure includes, among various embodiments, an active-matrix display with passive-matrix pixel clusters comprising pixel clusters and a display controller.
According to embodiments of the present disclosure, a hybrid display comprises pixel clusters and a display controller. Each of the pixel clusters comprises (i) pixels, (ii) a pixel memory for storing fewer than two pixel values for each of the pixels, and (iii) a cluster controller. Each cluster controller can be operable to (a) control each of the pixels in the pixel cluster to emit light corresponding to the fewer than two pixel values for each of the pixels, (b) receive the fewer than two pixel values for each of the pixels in the pixel cluster, and (c) store the fewer than two pixel values in the pixel memory for each of the pixels in the pixel cluster. The display controller can be operable to provide the fewer than two pixel values for each of the pixels in each pixel cluster to each of the cluster controllers. In embodiments, the fewer than two pixel values for each of the pixels in each pixel cluster are digital values (e.g., digital pixel values). Each of the cluster controllers can be operable to receive the fewer than two pixel values for each of the pixels in the pixel cluster from the display controller and store the received fewer than two pixel values for each of the pixels in the pixel memory at the same time that each of the cluster controllers controls the pixels in the pixel cluster to emit light corresponding to the fewer than two pixel values for each of the pixels in the pixel cluster.
In some embodiments, a hybrid display comprises pixel clusters and a display controller. Each of the pixel clusters comprises (i) pixels, (ii) a pixel memory for storing pixel values for each of the pixels, and (iii) a cluster controller operable to (a) control the pixels to emit light corresponding to the pixel values, (b) receive the pixel values, and (c) store the pixel values in the pixel memory. The display controller can be operable to provide the pixel values to the cluster controller for each of the pixel clusters. In embodiments, for each of the pixel clusters the cluster controller is operable to store one or more of the pixel values in the pixel memory at a same time that the cluster controller controls the pixels to emit light using one or more of the pixel values. In embodiments, the pixel values are digital pixel values. In some embodiments, each of the cluster controllers is operable to receive the pixel values from the display controller and store the received pixel values in the pixel memory at the same time that the cluster controller controls the pixels to emit light corresponding to the pixel values.
According to embodiments of the present disclosure, for each of the pixel clusters the pixels in the pixel cluster are controlled by the cluster controller with passive-matrix control. In some embodiments, for each of the pixel clusters, the cluster controller controls the pixels to emit light using pulse-width modulation control. In some embodiments, an amount of time to write a pixel value into the pixel memory is no greater than an amount of time of a shortest pulse of the pulse-width modulation control. In some embodiments, an amount of time to write a pixel value into the pixel memory is equal to or greater than an amount of time of a shortest pulse of the pulse-width modulation control.
According to embodiments of the present disclosure, for each of the pixel clusters, each of the pixels comprises C light emitters, each of the pixel values comprises C luminance values, each corresponding to one of the C light emitters, each of the luminance values has D bits, the pixels are disposed in an array of M rows and N columns, M is no less than two, N is no less than one, and C is no less than one, and the pixel memory has (i) a storage for pixel values of at least M×N×C×D bits (e.g., the pixel memory has a storage size of at least M×N×C×D bits) and (ii) at least M row addresses. For example, the M row addresses can have a range from 0 to (M−1).
In some embodiments, the pixel memory can have M×D row addresses and each row address can access C×N bits, where each bit corresponds to a bit of a luminance value. In some embodiments, the pixel memory has M row addresses and each row address accesses N pixel values equivalent to C×N luminance values and C×N×D bits.
According to some embodiments, the cluster controller is operable to read output pixel data stored at row address IOUTPUT of the pixel memory and control each of the pixels corresponding to row address IOUTPUT to emit light corresponding to the output pixel data at a same time that the cluster controller stores input pixel data at row address IINPUT of the pixel memory. In some embodiments, IOUTPUT equals IINPUT (e.g., IOUTPUT=IINPUT). In some embodiments, IOUTPUT does not equal IINPUT (e.g., IOUTPUT≠IINPUT). In some embodiments, the pixel memory has M row addresses and (IOUTPUT<M) and (IINPUT<M).
According to embodiments of the present disclosure, the pixel memory storage is no greater than a storage of N×(M+1) pixel values. In some embodiments, storage of the pixel memory (e.g., pixel memory storage) is no greater than a storage of N×M pixel values plus N×C bits.
In some embodiments, the cluster controller is operable to read output pixel data stored at row address IOUTPUT of the pixel memory and control each of the pixels corresponding to row address IOUTPUT to emit light corresponding to the output pixel data at a same time that the cluster controller stores input pixel data in one or more row addresses IINPUT of the pixel memory where (IINPUT≠IOUTPUT). In some embodiments, the pixel memory has M row addresses, IOUTPUT<M, and IINPUT<M. The one or more row addresses IINPUT can be two or more row addresses. In some embodiments, the pixel memory has M row addresses and the one or more row addresses IINPUT are (M−1) row addresses.
In some embodiments, the cluster controller is operable to read output pixel data stored at row address IOUTPUT of the pixel memory and copy the pixel data into the pixel memory at row address IOUTPUT2, where IOUTPUT≠IOUTPUT2. In some embodiments, the cluster controller is operable to copy the pixel data bit wise. In some embodiments, the cluster controller is operable to copy the pixel data pixel value wise.
In some embodiments of the present disclosure, the pixel memory storage is (M+1)×N×C×D bits in size and the pixel memory has row addresses having a range at least from zero to M. The cluster controller can be operable to read output pixel data stored at row address IOUTPUT of the pixel memory (IOUTPUT<(M+1)) and control the pixels corresponding to row address IOUTPUT to emit light corresponding to the output pixel data at a same time that the cluster controller stores input pixel data at one or more row addresses IINPUT of the pixel memory, where (IINPUT≠IOUTPUT) and (IINPUT<(M+1)).
In embodiments of the present disclosure, for each of the pixel clusters, the cluster controller is operable to receive rows of pixel values at an input rate and output rows of pixel values to display information at an output rate and the input rate is greater than the output rate. In some embodiments, for each of the pixel clusters, the cluster controller is operable to receive rows of pixel values at an input rate and output rows of pixel values to display information at an output rate and the input rate is less than or equal to the output rate. In some embodiments, for each of the pixel clusters, the cluster controller is operable to sequentially output single bits of each pixel value in a row of pixel values from the pixel memory and control the pixels to emit light corresponding to the single bits.
According to embodiments of the present disclosure, for each of the pixel clusters, the cluster controller is operable to write a pixel value into the pixel memory between output of single bits in a pixel value. In some embodiments, for each of the pixel clusters, the cluster controller is operable to write a pixel value into the pixel memory during output of single bits in a pixel value. In some embodiments, the cluster controller is operable to input a pixel value into the pixel memory in a blanking interval after controlling the pixels to emit light corresponding to a bit of a luminance value or in a blanking interval after controlling the pixels to emit light corresponding to an entire pixel value.
According to some embodiments of the present disclosure, the cluster controller is operable to (i) receive an input address of one or more input pixel values, (ii) compare the input address to an output address of a row of one or more output pixel values that are used to control the pixels to emit light and, and (iii) write the one or more input pixel values into the pixel memory only if the input address does not match the output address.
According to embodiments of the present disclosure, the cluster controller is operable to receive pixel values in a burst at regular or irregular intervals. According to embodiments of the present disclosure, for each of the pixel clusters, the cluster controller is operable to control the pixels independently of any other of the pixel clusters. In some embodiments, the pixel clusters are operable to emit light from all of the pixels in a common row at a same time. In some embodiments, each of the pixels comprises one or more light emitters that are inorganic micro-light-emitting diodes.
According to some embodiments of the present disclosure, an asynchronous memory bit cell comprises a first inverter with a first input and a first output, a second inverter with a second input and a second output, the first output connected to the second input, a write switch controllable by a write signal WC and connected between a data input and the first input, and a write-select switch controllable by an inverted WC signal and connected between the second output and the first input. Some embodiments comprise a read switch controllable by a read signal RC and connected between the first output and a data output.
In some embodiments, an asynchronous memory comprises (i) an array of memory bit cells, wherein the data input signals for the memory bit cells are connected together and the data output signals for the memory bit cells are connected together, (ii) a write-selection circuit operable to provide the write signal WC for each of the memory bit cells, and (iii) a read-selection circuit, independent of and comprising a separate circuit from the write-selection circuit, operable to provide the read signal RC for each of the memory bit cells.
In some embodiments of the present disclosure, an asynchronous memory comprises a first inverter with a first input and a first output, a second inverter with a second input and a second output, the first output connected to the second input, a write switch controllable by a write signal WC and connected between a data input and the first input, and a read switch controllable by a read signal and connected between the second output and the first input.
In some embodiments of the present disclosure, an asynchronous memory comprises an array of memory bit cells, wherein the data input (e.g., data input signals) for the memory bit cells are connected together and the data outputs for the memory bit cells are connected together, and a read-selection circuit, independent of and comprising a separate circuit from the write-selection circuit, that is operable to provide the read signal RC for each of the memory bit cells.
According to some embodiments of the present disclosure, a hybrid display comprises pixel clusters and a display controller. Each of the pixel clusters comprises (i) pixels, (ii) a pixel memory for storing fewer than two digital pixel values for each of the pixels, and (iii) a cluster controller operable to (a) control the pixels using pulse-width modulation control to emit light corresponding to the fewer than two digital pixel values, (b) receive the fewer than two digital pixel values for each of the pixels in the pixel cluster, and (c) store the fewer than two digital pixel values for each of the pixels in the pixel cluster in the pixel memory. The display controller can be operable to provide the fewer than two pixel values for each of the pixels in each pixel cluster to the cluster controller for each of the pixel clusters. In some embodiments, for each of the pixel clusters, (i) the cluster controller is operable to receive the fewer than two digital pixel values for each of the pixels in the pixel cluster from the display controller and store the fewer than two digital pixel values for each of the pixels in the pixel cluster in the pixel memory at a same time that the cluster controller controls the pixels to emit light corresponding to the fewer than two digital pixel values for each of the pixels in the pixel cluster, (ii) each of the fewer than two digital pixel values for each of the pixels in the pixel cluster comprises one or more digital luminance values, each of the one or more digital luminance values comprising multiple bits, and (iii) the pixel memory is accessed with row addresses and each unique one of the row addresses accesses a single bit of each of multiple luminance values.
In some embodiments of the present disclosure, a hybrid display comprises pixel clusters and a display controller. Each of the pixel clusters can comprise (i) pixels, (ii) a pixel memory for storing pixel values for each of the pixels, and (iii) a cluster controller operable to (a) control the pixels using pulse-width modulation control to emit light corresponding to the pixel values, (b) receive the pixel values, and (c) store the pixel values in the pixel memory. The display controller can be operable to provide the pixel values to the cluster controller for each of the pixel clusters. In some embodiments, for each of the pixel clusters, (i) the cluster controller is operable to receive the pixel values from the display controller and store the pixel values in the pixel memory at a same time that the cluster controller controls the pixels to emit light corresponding to the pixel values, (ii) each of the pixel values comprises one or more digital luminance values, each of the one or more digital luminance values comprising multiple bits, and (iii) the pixel memory is accessed with row addresses and each unique one of the row addresses accesses a single bit of each of multiple luminance values. In embodiments, the pixel memory can store fewer than two pixel values for each of the pixels. In embodiments, the pixel values for each of the pixels can be digital pixel values.
According to embodiments of the present disclosure, a method of controlling a hybrid display comprising pixel clusters, each of the pixel clusters comprising (i) pixels, (ii) a pixel memory for storing digital pixel values for the pixels, and (iii) a cluster controller, comprises receiving one or more digital pixel values at the cluster controller, storing the one or more pixel values in the pixel memory, and emitting light from the pixels (e.g., one or more of the pixels) using one or more other digital pixel values while the one or more pixel values are being stored (e.g., the pixels emit light at the same time as or concurrently with storing the one or more pixel values). The one or more other pixel values can be read bit wise from different row addresses in the pixel memory by the cluster controller to cause the pixels to emit the light. The one or more other pixel values can be read pixel value wise from one or more row addresses in the pixel memory by the cluster controller to cause the pixels to emit the light.
In some embodiments, methods of the present disclosure comprise reading pixel data (e.g., one or more pixel values or one or more bits comprised in one or more pixel values) from a row address of the pixel memory and simultaneously writing pixel data to any row address of the pixel memory (e.g., the row address or any other row address). Methods can comprise, for at least one of the pixel clusters, reading output pixel data stored at row address IOUTPUT of the pixel memory with the cluster controller and controlling each of the pixels corresponding to row address IOUTPUT to emit light corresponding to the output pixel data while the cluster controller stores input pixel data at row address IINPUT of the pixel memory. IOUTPUT can equal IINPUT. In some embodiments, IOUTPUT does not equal IINPUT. The pixel memory can have M row addresses and IOUTPUT<M and IINPUT<M.
Some methods of the present disclosure can comprise, for at least one of the pixel clusters, reading output pixel data stored at row address IOUTPUT of the pixel memory with the cluster controller and controlling each of the pixels corresponding to row address IOUTPUT to emit light corresponding to the output pixel data while the cluster controller stores input pixel data in one or more row addresses IINPUT of the pixel memory where IINPUT≠IOUTPUT. The pixel memory can have M row addresses, IOUTPUT can be less than M, and IINPUT can be less than M.
In some embodiments, the one or more row addresses IINPUT are two or more row addresses. In some embodiments, the pixel memory has M row addresses and the one or more row addresses IINPUT are (M−1) row addresses.
Some methods of the present disclosure can comprise, for at least one of the pixel clusters, reading output pixel data stored at row address IOUTPUT of the pixel memory with the cluster controller and copying the pixel data into the pixel memory at row address IOUTPUT2, where IOUTPUT≠IOUTPUT2. The copying can occur bit wise. The copying can occur pixel value wise.
Some methods of the present disclosure can comprise, for at least one of the pixel clusters reading output pixel data stored at row address IOUTPUT of the pixel memory (IOUTPUT<(M+1)) with the cluster controller and controlling the pixels corresponding to row address IOUTPUT to emit light corresponding to the output pixel data while the cluster controller stores input pixel data at one or more row addresses IINPUT of the pixel memory, where IINPUT≠IOUTPUT and IINPUT<(M+1).
Some methods of the present disclosure can comprise, for at least one of the pixel clusters receiving rows of pixel values at the cluster controller at an input rate and outputting rows of pixel values with the cluster controller at an output rate to control the pixels in the pixel cluster to emit light, wherein the input rate is greater than the output rate. Some methods of the present disclosure can comprise, for at least one of the pixel clusters receiving rows of pixel values at the cluster controller at an input rate and outputting rows of pixel values with the cluster controller at an output rate to control the pixels in the pixel cluster to emit light, wherein the input rate is less than or equal to the output rate.
Some methods of the present disclosure can comprise, for at least one of the pixel clusters sequentially outputting single bits of each pixel value in a row of pixel values from the pixel memory with the cluster controller and controlling the pixels to emit light corresponding to the single bits.
Some methods of the present disclosure can comprise, for at least one of the pixel clusters, writing a pixel value into the pixel memory between output of single bits in a pixel value. Some methods of the present disclosure can comprise, for at least one of the pixel clusters, writing a pixel value into the pixel memory during output of single bits in a pixel value.
Some methods of the present disclosure can comprise, for at least one of the pixel clusters, inputting a pixel value into the pixel memory in a blanking interval after controlling the pixels to emit light corresponding to a bit of a luminance value or in a blanking interval after controlling the pixels to emit light corresponding to an entire pixel value.
Some methods of the present disclosure can comprise, for at least one of the pixel clusters receiving an input address of one or more input pixel values at the cluster controller, comparing the input address to an output address of a row of one or more output pixel values that are used to control the pixels to emit light, and writing the one or more input pixel values into the pixel memory only if the input address does not match the output address.
Some methods of the present disclosure can comprise, for at least one of the pixel clusters receiving pixel values at the cluster controller in a burst at regular or irregular intervals and storing the pixel values in the pixel memory.
Embodiments of the present disclosure provide active and passive display control methods and architectures that enable improved control of displays with reduced power and improved bit depth.
The foregoing and other objects, aspects, features, and advantages of the present disclosure will become more apparent and better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:
Features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The figures are not drawn to scale since the variation in size of various elements in the Figures is too great to permit depiction to scale.
Embodiments of the present disclosure provide, inter alia, active- and passive-matrix display control methods and architectures that require fewer or smaller and less expensive control circuits with improved performance for flat-panel displays (e.g., large-substrate displays) with an array of pixels. The pixels can comprise one or more light emitters that are inorganic light-emitting diodes.
According to some embodiments of the present disclosure and as illustrated in
Pixel clusters 20 can be, but are not necessarily, spatially separate and non-overlapping so that nothing in a pixel cluster 20 is disposed spatially within an area of display substrate 10 that includes another, different pixel cluster 20. Pixel memory 25 of a pixel cluster 20 comprises all of the pixel values stored in pixel cluster 20 necessary to output and display the pixel values. Pixel memory 25 storage is the amount of pixel data that pixel memory 25 can store and does not include any buffering or pixel value storage necessary to input pixel values to pixel cluster 20. Pixel memory 25 includes only memory devices necessary to store pixel values and control pixels 24 to emit light corresponding to the stored pixel values. Thus, according to embodiments of the present disclosure, a hybrid display 90 comprises pixels 24 divided into mutually-exclusive groups (pixel clusters 20). Each pixel cluster 20 comprises multiple pixels 24 controlled with a cluster controller 22 as passive-matrix pixels 24 that do not include any memory in the pixel. Instead, cluster controller 22 comprises pixel memory 25 storing the pixel values corresponding to each pixel 24.
A display controller 14 can be operable to provide pixel values to cluster controllers 22 for example through a display row controller 16 and display column controller 18 responsive to pixel-value receiver 15. In embodiments of the present disclosure, the pixel values are digital values and each of cluster controllers 22 is operable to receive pixel values from display controller 14 and store the pixel values in pixel memory 25 at the same time that cluster controller 22 controls pixels 24 to emit light corresponding to the pixel values. The display is a hybrid display 90 because, although pixels 24 in each pixel cluster 20 are controlled as passive-matrix pixels 24, each pixel cluster 20 stores pixel values corresponding to pixels 24 of pixel cluster 20 and the pixel clusters 20 are therefore active-matrix. Externally, hybrid display 90 appears to operate as an active-matrix display.
According to embodiments of the present disclosure, display substrate 10 can be any substrate on which cluster controller 22, pixel memory 25 and pixels 24 can be disposed and electrically interconnected, for example glass, plastic, semiconductor, ceramic, or sapphire substrates or substrates useful in flat-panel displays or wafers used in the construction of integrated circuits and suitable for photolithographic processes. Display controller 14 can comprise one or more control and data circuits, for example integrated circuits comprising silicon CMOS circuits. In some embodiments, display controller 14 comprises a display row controller 16 for providing signals such as control signals to cluster controllers 22 of pixel clusters 20, for example through display row wires 17 electrically connected to rows of pixel clusters 20, a display column controller 18 for providing signals such as data signals (e.g., digital pixel values) to cluster controllers 22 of pixel clusters 20, for example through display column wires 19 electrically connected to columns of pixel clusters 20, and a pixel-value receiver 15 that receives digital pixel values corresponding to pixels 24 in an image from an external source. Pixel-value receiver 15 can transmit digital pixel values to display row and column controllers 16, 18, as well as transmit control and timing signals. Any one or more of display row controller 16, display column controller 18, and pixel-value receiver 15 can be integrated circuits, for example silicon CMOS circuits or mixed signal circuits made using photolithographic methods and materials suitable for providing data and control signals to cluster controller 22. Any one or more of display row wires 17, display column wires 19, cluster row wires 26, and cluster column wires 28 can be disposed on display substrate 10 using photolithographic methods and materials, for example patterned metal conductors deposited by metal evaporation and photoresist mask patterning. The dashed lines in
Any one or more of cluster controller 22 and pixel memory 25 can be integrated circuits, for example silicon CMOS circuits or mixed-signal circuits made using photolithographic methods and materials. Cluster controller 22 can be a state machine, can comprise digital logic, or can be a programmable micro-controller. Cluster controller 22 can be operable to receive control and data signals (e.g., digital pixel values) from display row and column controllers 16, 18, write and receive digital pixel values to and from pixel memory 25, and control pixels 24 to emit light corresponding to the digital pixel values stored in pixel memory 25 through cluster row wires 26 and cluster column wires 28, e.g., using passive-matrix control.
Display column controller 18 can be, for example, an integrated circuit that provides control, timing (e.g., clocks) or pixel values (e.g., column-data signals) through display column wires 19 (column-data lines) to columns of pixel clusters 20 to enable light emitters 60 to control light in hybrid display 90. Each display column wire 19 can be electrically separate and optionally independently controlled from every other display column wire 19 by display column controller 18. Display column controller 18 can comprise a single integrated circuit or can comprise multiple integrated circuits, e.g., electrically connected integrated circuits. The integrated circuit(s) can be micro-transfer printed onto display substrate 10 as unpackaged dies and can comprise fractured or separated tether(s).
Display row controller 16 can be, for example, an integrated circuit that provides control signals (e.g., row-select signals) and/or timing signals (e.g., clocks or timing signals such as pulse-width modulation (PWM) signals) through display row wires 17 (row-select lines) to rows of pixel clusters 20 to cause light emitters 60 to control light in hybrid display 90. Each display row wire 17 can be electrically separate and optionally independently controlled from every other display row wire 17 by display row controller 16. Display row controller 16 can comprise a single integrated circuit or can comprise multiple integrated circuits, e.g., electrically connected integrated circuits. The integrated circuit(s) can be micro-transfer printed onto display substrate 10 as unpackaged dies and can comprise broken (e.g., fractured) or separated tether(s).
Pulse-width modulation (PWM) is a control method that uses temporally sequential pulses (digital signals) of different periods (typically relative powers of two). Each pulse can be combined with a bit of a luminance value having a place (e.g., power of two) corresponding to the period of the pulse to provide a control signal, for example to control light emitters 60 to emit light with a constant current during the pulse period. As used herein, a PWM cycle is the time required to temporally output all of the pulses corresponding to a luminance signal (e.g., 256=28 for an eight-bit luminance value).
Pixels 24 can each comprise one or multiple light emitters 60, such as light-emitting diodes. In some embodiments, light emitters 60 can comprise light-emitting diodes, e.g., inorganic light-emitting diodes such as horizontal inorganic light-emitting or vertical inorganic light-emitting diodes. In embodiments of the present disclosure inorganic light-emitting diodes can be micro-inorganic-light-emitting diodes. Inorganic light-emitting diodes can have a small area, for example having a length and a width each no greater than 5 microns, no greater than 10 microns, no greater than 20 microns, no greater than 50 microns, no greater than 100 microns, or no greater than 200 microns. Inorganic light-emitting diodes can have a small thickness, for example having a thickness no greater than 50 microns, no greater than 20 microns, no greater than 10 microns, no greater than 5 microns, or no greater than 2 microns. Such small light emitters 60 leave additional area on display substrate 10 for more or larger wires, e.g., display column wires 19, display row wire 17, or ground and power wires, or circuits, e.g., cluster controllers 22.
Pixels 24 can comprise a red light-emitting diode that emits red light, a green light-emitting diode that emits green light, and a blue light-emitting diode that emits blue light (collectively light-emitting diodes or LEDs) under the control of cluster controller 22. In certain embodiments, light emitters 60 that emit light of other color(s) are included in pixel 24, such as a yellow light-emitting diode. Light-emitting diodes can be mini-LEDs (e.g., having a largest dimension no greater than 500 microns) or micro-LEDs (e.g., having a largest dimension of less than 100 microns). Pixels 24 can emit one color of light or white light (e.g., as in a black-and-white hybrid display 90) or multiple colors of light (e.g., red, green, and blue light as in a color hybrid display 90). Pixel clusters 20 can comprise multiple elements disposed and electrically connected directly on display substrate 10. Pixel clusters 20 can comprise multiple elements disposed and electrically connected on a cluster substrate non-native to (e.g., separate and independent from) display substrate 10 with the cluster substrate disposed on display substrate 10. In some embodiments, one or more pixel clusters 20 include one or more elements disposed and electrically connected directly on display substrate 10 and one or more elements disposed and electrically connected on a cluster substrate non-native to display substrate 10 (e.g., and electrically interconnected with the one or more elements disposed and electrically connected directly on display substrate 10 with one or more electrical connections, which can include one or more vias).
Cluster controller 22 can comprise one or more integrated circuits, for example one or more micro-devices. Any one or more of cluster controller 22 and LEDs can be micro-transfer printed onto display substrate 10 or onto a cluster substrate. Cluster controller 22 and LEDs can be connected with cluster row wires 26 connecting rows of light emitters 60 to cluster controller 22 or display row controller 16 and cluster column wires 28 connecting columns of light emitters 60 to cluster controller 22 or display column controller 18. A cluster substrate can be micro-transfer printed from a cluster source substrate onto display substrate 10 and electrically connected to control signal wires (e.g., display row wires 17 or row-control lines, display column wire 19, power, and ground signal wires) on display substrate 10. Micro-transfer printed devices or structures (e.g., LEDs, cluster controllers 22, or cluster substrates) can comprise broken (e.g., fractured) or separated tether(s) as a consequence of micro-transfer printing from a source to a target substrate.
According to some embodiments of the present disclosure, a cluster controller 22 receives column-data signals (e.g., pixel values) from display column controller 18 through display column wire 19 and row-select signals (e.g., timing or control signals) from display row controller 16 through display row wire 17. When a pixel cluster 20 is selected by a row-select signal on display row wire 17, pixel values received on display column wire 19 can be stored in pixel memory 25 by cluster controller 22 at the same time as cluster controller 22 outputs pixel values from pixel memory 25 to control light emitters 60 to emit light.
Pixel memory 25 can be a static random-access memory (SRAM) or one or more registers, e.g., comprising one or more flipflops, latches, or memory cells. Registers of pixel memory 25 can be shift registers, for example serial shift registers or parallel shift registers, or registers that can receive data in parallel and output data serially, or vice versa. In some embodiments, pixel memory 25 does not include any storage providing buffers for inputting and temporarily storing pixel values received from display controller 14 prior to storing the received pixel values in pixel memory 25 and outputting the pixel values from pixel memory 25. Pixel memories 25 in pixel cluster 20 store fewer than twice as many pixel values as pixels 24 in pixel cluster 20. Thus, pixel memory 25 cannot be a double-buffered memory and cannot have two memory banks where each memory bank stores all of the pixel values for pixel cluster 20 corresponding to an image frame. An image frame is an entire image comprising pixel values for display with pixels 24 in hybrid display 90. Image frames are typically successive, e.g., are supplied in a temporal stream as in a typical video image sequence.
Embodiments of the present disclosure are intended to provide a memory architecture for a pixel memory 25 in each pixel cluster 20 that has reduced size and reduced leakage and hence reduced power usage. In embodiments of the present disclosure, cluster controller 22 is operable to receive pixel values from display controller 14 and store the received pixel values in pixel memory 25 at the same time that pixels 24 emit light corresponding to pixel values, even though pixel memory 25 is not double buffered. In some conventional systems, the amount of memory required can be 2M rows of pixel data whereas embodiments of the present disclosure store fewer rows of pixel data than 2M in the display where M is the number of rows of pixels 24 in pixel cluster 20.
According to embodiments of the present disclosure, cluster controller 22 can be operable to input pixel data at an input rate and, at the same time or different times, output stored pixel data from pixel memory 25 at an output rate to control light emitters 60 to emit light corresponding to the pixel data. The output rate can be different from the input rate, and in some embodiments, the output rate is greater than the input rate, for example an integral multiple such as two, four, eight, sixteen, or 2× times. In some embodiments, the input and output can be unsynchronized (asynchronous) or independent and an input (receipt or write of digital pixel values) does not affect the output (read and display of digital pixel values by light-emitters 60 in pixels 24) and vice versa. Such asynchronous operation enables input and output at different transmission rates, for example receiving digital pixel values (e.g., rows of pixel data) of an image frame at a greater input rate (e.g., in a burst mode) than an output rate displaying the digital pixel values stored in pixel memory 25 either at regular intervals or irregular intervals. For example, a portion of the digital pixel values of an image frame corresponding to pixels 24 in a pixel cluster 20 stored in pixel memory 25 can be displayed at 100 frames per second (e.g., pixel values in pixel memory 25 are displayed every 10 milliseconds) and digital pixel values of a subsequent image frame received from display controller 14 in 5 milliseconds at 10 millisecond intervals so that input is temporally discontinuous. In some embodiments, the input rate can be equal to the output rate so that the input frame rate is equal to the output frame rate. In some embodiments, the input rate can be less than the output rate so that pixel values can be output more than once while pixel values are input. In such embodiments, the input frame rate is less than the output frame rate, so frames are repeatedly displayed, for example in a refresh-on-demand hybrid display 90.
Pixels 24 in pixel clusters 20 can be controlled by cluster controller 22 using passive-matrix control so that pixels 24 are passive-matrix pixels 24. Each pixel 24 can include one or more light emitters 60, for example, inorganic micro-light-emitting diodes. Because pixels 24 are passive-matrix pixels 24 they do not include any memory or storage devices such as a random access memory, one or more flipflops, one or more latches, a serial shift register, a parallel shift register, or a serial-in/parallel-out shift register. Pixels 24 can each include multiple light emitters 60 that each emit light of a different color, for example red, green, and blue light when provided with pixel data and suitable control, power, and ground signals forming a picture element or pixel 24 in hybrid display 90). Each individual light emitter 60 in pixel 24 can be a sub-pixel of pixel 24 or can be included in a sub-pixel of pixel 24 (e.g., where redundant emitters for one or more colors are used). Embodiments of the present disclosure can reduce, eliminate, or avoid flickering or image artifacts, and can improve the appearance of image pixel data on hybrid display 90. Embodiments of the present disclosure provide reduced memory requirements for logically and temporally decoupled input and output pixel control methods in a display.
Pixels 24 in pixel clusters 20 can be disposed on display substrate 10 in a regular array such as a rectangular array, for example both within pixel clusters 20 and including all of pixels 24 in all of pixel clusters 20 in a regular two-dimensional array that, together, form display area 12. Cluster controllers 22 can be disposed on or over display substrate 10 between pixels 24 in a pixel cluster 20 or between pixel clusters 20, for example between adjacent rows or columns of pixels 24 in different pixel clusters 20 (as shown in
Digital pixel values are received by pixel-value receiver 15, for example from an external image source. Each digital pixel value includes all of the information necessary to control all of light emitters 60 in a single pixel 24. For example, each digital pixel value can include D binary bits where D is the number of bits (the bit depth) in a digital luminance value used to control a single light emitter 60, for example, 8 bits 12 bits, or 16 bits. The bit depth D of a binary digital pixel value specifies the number of luminance levels (equal to 2D) at which light emitters 60 can emit light. If each pixel 24 comprises C light emitters 60, for example three light emitters 60 that each emit one of red, green, and blue light, then the pixel value for each pixel 24 has C×D bits, for example 24 bits (three colors×eight-bit luminance value), 36 bits (three colors×twelve-bit luminance value), or 48 bits (three colors×sixteen-bit luminance value) organized in three digital luminance values of eight, twelve, or sixteen bits each, respectively. Pixel memory 25 stores at least one digital pixel value for each pixel 24 in pixel cluster 20. If pixel 24 has only one light emitter 60, then C=1 and the pixel value has one luminance value so that the pixel value and the luminance value are equivalent. The term pixel data refers herein to any of pixel values, luminance values, or one or more bits of a pixel value.
Each pixel cluster 20 can comprise M by N pixels 24, e.g., arranged in M rows by N columns, each having C light emitters, so that pixel memory 25 stores M×N digital pixel values each having C luminance values (one for each emitter)×D bits for each luminance value for a storage of at least M×N×C×D bits. (Individual rows M, columns N, colors C, and bits D are referenced generally from 0 to (M−1), (N−1), (C−1), and (D−1), respectively.) In embodiments of the present disclosure, pixel values for pixels 24 in pixel clusters 20 can be disposed in an array of M rows and N columns, wherein M is no less than two and N is no less than one, and pixel memory 25 stores received pixel values in an M×N array having unique row addresses ranging from at least (or only) from zero to (M−1). In some embodiments, a larger pixel memory 25 has row addresses from zero to M, thereby facilitating data loading using the extra row address.
Luminance value bits of each pixel value in pixel memory 25 can be organized in different logical arrangements at different pixel memory 25 addresses for different embodiments of the present disclosure. In some embodiments, pixel memory 25 has M×D unique row addresses and each row address accesses (e.g., can be used to read or write) C×N bits in pixel memory 25 so that each unique row address accesses (e.g., inputs or outputs) a single bit of each luminance value in each pixel value, for example for memory architectures shown in
In some embodiments, pixel memory 25 has M unique row addresses and each row address stores N pixel values, where each pixel value has C×N luminance values and C×N×D bits, for example for memory architectures shown in
Conventional analog displays can use capacitors to store analog values as charges that control drive transistors for light emitters. When updated, the capacitors can monotonically change from a prior charge to an updated charge so that the light emitted likewise changes monotonically from a prior luminance to an updated luminance for a successive image frame avoiding pixel display artifacts. Moreover, the capacitors can control an output transistor at the same time that an input transistor modifies the charge on the capacitor, that is data in the capacitor circuit (charge) can be read from and written to at the same time. Embodiments of the present disclosure implement such a capability using digital pixel values, a digital memory, digital input and output circuits, and digital light emitter 60 drive control, e.g., using constant-current pulse-width modulation control.
In contrast to digital circuits of the present disclosure, analog storage (e.g., capacitors) and control methods can require a relatively large area of a semiconductor integrated circuits and experience significant charge leakage, especially for thin-film transistor circuits commonly found in flat-panel displays, thereby increasing costs and power usage while reducing resolution. Moreover, simple analog circuits do not provide a constant-current light emitter control and more complex analog circuits use more area over a display substrate 10, limiting display resolution. A similar update for displays using digital storage with smaller components and less leakage is conventionally performed by outputting pixel values stored in a first memory bank while updated data is received and stored in a second independent memory bank, e.g., together defining a double-buffered memory system. At the end of a display cycle (image frame display period), the memory banks are switched so that pixel values from the second memory bank are output while updated pixel values from a next image frame are stored in the first memory bank. However, two memory banks, one for pixel values for each of two image frames requires twice the area of a semiconductor integrated circuit, twice the power, twice the charge, and results in twice the current leakage. Thus, embodiments of the present disclosure provide pixel control with reduced pixel memory 25 area (and cost) as well as reduced power usage, and increased resolution.
In embodiments of the present disclosure, cluster controller 22 controls passive-matrix pixels 24 using pulse-width modulation having temporally variable pulses of constant current. Constant-current control is useful for light emitters 60 comprising inorganic light-emitting diodes because inorganic light-emitting diodes are most efficient at a particular current. Thus, operating the inorganic light-emitting diodes at a particular current of maximal or near maximal efficiency reduces power use in pixels 24 for a desired amount of output light. Variable luminance for the pixels 24 is accomplished by emitting light at the most efficient current for variable amounts of time equal to an image frame period at a fast enough rate that the human visual system perceives an average luminance over the image frame period.
According to embodiments of the present disclosure and as shown in
In embodiments of the present disclosure and as illustrated in
When combined with a PWM control signal (e.g., a pulse), the additional bit storage can enable a constant-current source 30 to cause light emitters 60 to emit light. By using the additional pixel memory 25 storage, pixel memory 25 can input and receive pixel values from display controller 14 (e.g., a subsequent image frame) at the same time that light emitters 60 emit light, for example from the same row of pixels 24 for which pixel memory 25 receives subsequent pixel values where pixel memory 25 cannot both input and output pixel values at the same address at the same time. To avoid input/output (e.g., read/write) conflicts for a memory address of pixel memory 25 that can lead to perceptible image artifacts, it is helpful if the read or write time for pixel memory 25 is smaller, preferably much smaller, than the smallest temporal period of the PWM signal, e.g., an amount of time to write pixel values into pixel memory 25 is less than a shortest pulse of the pulse-width modulation control signal, e.g., corresponding to the least-significant bit of a luminance value.
As shown in
Similarly,
In some embodiments, a conflict between reading and writing the same row of pixel values can be resolved by preventing the writing (input) of the new pixel values. This can result in a displayed frame having a portion (e.g., a row) of a first image frame and a portion (e.g., one or more rows) of a second image frame that is subsequent to the first image frame. If the image frames are regularly received by pixel cluster 20 from display controller 14, a following image frame can then update the unwritten row, for example as is commonly the case for video image streams. (At sufficiently high frame rates such effects will be unnoticeable or negligibly noticeable to a viewer. However, if a display is only refreshed on demand, such an interlaced displayed image frame may not be desired.) Such an update method can be accomplished by comparing an input row address to an output row address and writing the new pixel values in the input row only if the input and the output row addresses do not match. In some such embodiments, cluster controller 22 can be operable to (i) receive an address of input pixel values, (ii) compare the address of the input pixel values to an address of a row of output pixel values that are controlled to emit light, and (iii) (a) if the input address does not match the output address, write the input pixel values into the pixel memory or (b) if the input address does match the output address, not write the input pixel values into the pixel memory.
In the embodiments of
The embodiments illustrated in
Such embodiments can be implemented with, for example, pixel memory 25 as shown in
An output signal from bit cell 70 can be controlled with an output enable gate that, when not active, is in a high-impedance state (tristate) so that outputs from all of the corresponding bit cells 70 in a row can be connected together and no data output selection is necessary (e.g., no multiplexing is necessary). Each output enable gate can be selected with read enable signal RC (e.g., by a bit-select signal that selects the desired row of bits using a demultiplexer responsive to a read (output) address provided by cluster controller 22) combined with a read enable signal, for example a PWM period signal corresponding to the selected bit, in which case the AND gates of
Pixel memory 25 has a similar input enable gate controlling input to bit cell 70 selected by a write address combined with a write enable signal to form signal WC, for example provided by cluster controller 22. However, as shown in
In embodiments, both read selection circuits and write selection circuits are independently and separately present in cluster controller 22 (or pixel memory 25 depending on design choices) and are both independently and separately operable at a same time to read and write separate and independent pixel data from and to pixel memory 25. The read-selection circuit and write-selection circuit are not a common shared circuit used for both reading pixel data from pixel memory 25 and writing pixel data to pixel memory 25 at different times. Similarly, the data input and output signals and the wires transmitting the input and output signals are separate and independent signals and wires both operable at a same time to transmit the same or different input and output signals. Likewise, the WC and RC signals are both independently and separately operable at a same time to transmit the same or different write and read signals. Write switch 76 and read switch 74 are separate and independent transistors both operable at a same time to switch responsive to the same or different write control WC and read control RC signals. Thus, according to embodiments of the present disclosure, cluster controller 22 comprises read and write circuits (including wires and circuits comprising, for example, switches and transistors) that are both present in pixel cluster 20 and are separately and independently operable and controlled and do not share circuit elements, except for pixel memory 25 accessed by both the read and write circuits.
Thus, according to embodiments of the present disclosure and as illustrated in
As illustrated in
In display operation, it is possible that a selected bit is output and then overwritten during the PWM pulse period. If the overwritten bit is the same, there is no change in the originally desired bit output. If the overwritten bit is different, then the output can change state from a bit corresponding to a pixel 24 in an image to a bit corresponding to a pixel 24 in a subsequent image. It is also possible that bits subsequent to an output bit are overwritten so that a combination of the original pixel value and the overwritten value is output. A careful study of the possible pixel values that can be output shows that in a worst case, the displayed pixel values have no greater impact on pixel bit changes (and therefore light emitter luminance) than can be found in the most extreme pixel value changes between successively output image frames. The luminance changes are therefore deemed to be acceptable. For example, if an output bit changes state during its output period, the effective luminance of the bit will be somewhere between the intended luminance of the bit and the overwritten value. Instead of being completely on or off during the pulse period, light emitter 60 will be perceived to be partially on or off during the pulse period and have a perceived luminance between on and off over the pulse period depending on the timing of the bit change. Since the pulse period is only one of a complete PWM pulse train (PWM cycle), the effect is relatively small, or at least no worse than a transition from a pixel value that is completely on to a pixel value that is completely off (or vice versa) in successive image frames. Additionally, such an overwrite error should only persist for a single frame.
In some such embodiments and in general, cluster controller 22 can be operable to (i) read the pixel values in row IOUTPUT of pixel memory 25, (IOUTPUT<M), and control pixels 24 in row IOUTPUT to emit light corresponding to the pixel values in row IOUTPUT of pixel memory 25 at the same time that cluster controller 22 can be operable to (ii) store pixel values in rows IINPUT of pixel memory 25 where (IINPUT<M). Thus, any row of pixel memory 25 is independent of any other row so that any row can be read from and any row of pixel memory 25 can be written to at the same time.
Pixel memory 25 is shown in
As shown in
Embodiments illustrated in
In some embodiments, pixel value input and output conflicts (e.g., modification of pixel values with new image frame pixel values while the pixel values are output) can be avoided by using cluster controller 22 to ensure that an output pixel value is not input at the same time. This can be done by writing new pixel values only into rows of pixel memory 25 that are not output at the same time. In some such embodiments, a pixel value writing time can be no greater than the entire PWM cycle, so that an amount of time to write pixel values into pixel memory 25 is equal to or longer than a shortest pulse of the pulse-width modulation control. Thus, in some such embodiments, cluster controller 22 is operable to (i) read pixel values in row IOUTPUT of pixel memory 25 (IOUTPUT<M) and control pixels 24 in row IOUTPUT to emit light corresponding to the pixel values in row IOUTPUT of pixel memory 25 at the same time that cluster controller 22 is operable to (ii) store pixel values in one or more rows IINPUT of pixel memory 25 where (IINPUT≠IOUTPUT) and (IINPUT<M). Thus, any row of pixel memory 25 can be read from and any other row of pixel memory 25 can be written to at the same time (or vice versa).
In some embodiments, multiple rows of pixel values can be input during a single output of a row of pixel values. For example, during an output of a row of pixel values (e.g., a PWM cycle), two rows of pixel values can be input so that the one or more rows IINPUT are two or more rows. More generally, any and all of the pixel values in any row of pixel values that are not output at the same time can be input, so that the one or more rows IINPUT are (M−1) rows. Thus, while one row is output (read from), all of the other rows can be input (written to), especially if pixel memory 25 can input data at a greater rate than is necessary for output, for example in a burst mode.
Hybrid display 90 can comprise multiple pixel clusters 20, for example arranged in a regular array as shown in
As shown in
Cluster controller 22 can control pixels 24 with pixel values stored in pixel memory 25 by iteratively outputting rows of pixel values stored in pixel memory 25, as shown in
Steps 200A, 200B, and 200C illustrate different embodiments of the present disclosure. As shown in
As shown in
Cluster controllers 22 can be thin-film circuits. According to some embodiments of the present disclosure, cluster controllers 22 comprise integrated circuits formed in a crystalline semiconductor (e.g., silicon) substrate that are transferred from a native source wafer to non-native display substrate 10 or to a non-native cluster substrate, for example by micro-transfer printing. As a consequence of micro-transfer printing, cluster controller 22 can comprise a fractured or separated controller tether. Such crystalline circuits have much better performance and a smaller size than thin-film semiconductor circuits. The smaller size of cluster controller 22 provides additional area over display substrate 10 for larger display column wires 19, display row wires 17, pixels 24, or other circuits, enabling embodiments of the present disclosure.
According to some embodiments of the present disclosure, display row controller 16 can provide timing signals to each pixel cluster 20 in a row of pixel clusters 20 or to rows of pixels 24 at a same time, for example row-select signals or pixel timing signals such as pulse-width modulation (PWM) signals. According to some embodiments, each pixel cluster 20 can comprise a pixel timing circuit that internally and independently generates a timing signal controlling the brightness of pixels 24, for example in combination with digital data values stored in pixel memory 25. In some such embodiments, internally generated timing signals need not be provided by display row controller 16 or display column controller 18, e.g., simplifying display row controller 16, and reducing the bandwidth and frequency requirements for row-select signals on display row wires 17 or column-data signals on display column wires 19, as certain operations can instead be carried out locally in cluster controllers 22.
Embodiments illustrated in
In a method according to some embodiments of the present disclosure, integrated circuits are disposed on display substrate 10 by micro transfer printing. In some methods, integrated circuits (or portions thereof) or LEDs are disposed on a cluster substrate to form a heterogeneous pixel 24 or pixel cluster 20 and pixel cluster 20 on the cluster substrate is disposed on display substrate 10 using compound micro-assembly structures and methods, for example as described in U.S. patent application Ser. No. 14/822,868 filed Aug. 10, 2015, entitled Compound Micro-Assembly Strategies and Devices. However, since pixel clusters 20 can be larger than the integrated circuits included therein, in some methods of the present disclosure, pixel clusters 20 are disposed on display substrate 10 using pick-and-place methods found in the printed-circuit board industry, for example using vacuum grippers. Circuits and light-emitters 60 in a pixel cluster 20 can be interconnected on display substrate 10 using photolithographic methods and materials or printed circuit board methods and materials. Circuits and light emitters 60 in a pixel cluster 20 can be interconnected on a cluster substrate using photolithographic methods and materials. Pixel clusters 20 can be interconnected on display substrate 10 using photolithographic methods and materials or printed circuit board methods and materials.
In certain embodiments, display substrate 10 includes material, for example glass or plastic, different from a material in an integrated-circuit substrate, for example a semiconductor material such as silicon or GaN. Light emitters 60 can be formed separately on separate semiconductor substrates, assembled onto cluster substrates (e.g., semiconductor substrates on or in which native cluster controllers 22 can be constructed to form pixel clusters 20 and then the assembled units are located on the surface of the display substrate 10. This arrangement has the advantage that the integrated circuits or pixel clusters 20 can be separately tested on a cluster substrate and the cluster modules accepted, repaired, or discarded before pixel clusters 20 are located on display substrate 10, thus improving yields and reducing costs.
In some embodiments of the present disclosure, providing hybrid display 90, display substrate 10, or pixel clusters 20 can include forming conductive wires (e.g., display row wires 17 and display column wires 19) on display substrate 10 or a cluster substrate by using photolithographic and display substrate 10 processing techniques, for example photolithographic processes employing metal or metal oxide deposition using evaporation or sputtering, curable resin coatings (e.g. SU8), positive or negative photoresist coating, radiation (e.g. ultraviolet radiation) exposure through a patterned mask, and etching methods to form patterned metal structures, vias, insulating layers, and electrical interconnections. Inkjet and screen-printing deposition processes and materials can be used to form patterned conductors or other electrical elements. The electrical interconnections, or wires, can be fine interconnections, for example having a width of less than fifty microns, less than twenty microns, less than ten microns, less than five microns, less than two microns, or less than one micron. Such fine interconnections are useful for interconnecting micro-integrated circuits, for example as bare dies with contact pads and used with the cluster substrates. Alternatively, wires can include one or more crude lithography interconnections having a width from 2 μm to 2 mm, wherein each crude lithography interconnection electrically interconnects pixels 24 on display substrate 10. For example, electrical interconnections can be formed with fine interconnections (e.g., relatively small high-resolution interconnections) while display column wires 19 and/or display row wires 17 are formed with crude interconnections (e.g., relatively large low-resolution interconnections).
In some embodiments, red, green, and blue LEDs (e.g., micro-LEDs) or integrated circuits forming cluster controllers 22 are micro-transfer printed to cluster substrates or display substrate 10 in one or more transfers and can comprise fractured or separated tethers as a consequence of micro-transfer printing. For a discussion of micro-transfer printing techniques that can be used or adapted for use in methods disclosed herein, see U.S. Pat. Nos. 8,722,458, 7,622,367 and 8,506,867, each of which is hereby incorporated by reference in its entirety. The transferred light emitters 60 are then interconnected, for example with conductive wires and optionally including connection pads and other electrical connection structures, to enable a controller (e.g., cluster controller 22) to electrically interact with light emitters 60 to emit, or otherwise control, light.
According to various embodiments, flat-panel hybrid display 90 can include a variety of designs having a variety of resolutions, light emitter 60 sizes, and hybrid displays 90 having a range of display substrate 10 areas. Light emitters 60 of hybrid display 90 can be arranged in a regular array or an irregular array on or over display substrate 10.
In some embodiments, LEDs are formed in substrates or on supports separate from display substrate 10. For example, LEDs or cluster controller 22 are separately formed in a semiconductor wafer. LEDS or cluster controllers 22 are then removed from the wafer and transferred, for example using micro-transfer printing, to display substrate 10 or a cluster substrate. Such arrangements have the advantage of using a crystalline semiconductor substrate that provides higher-performance integrated circuit components than can be made in the amorphous or polysilicon semiconductor available in thin-film circuits on a large substrate such as display substrate 10. Such micro-transferred LEDs or cluster controllers 22 can comprise a fractured or separated tether as a consequence of a micro-transfer printing process.
By employing a multi-step transfer or assembly process, increased yields are achieved and thus reduced costs for flat-panel hybrid displays 90 of the present disclosure. Additional details useful in understanding and performing aspects of the present disclosure are described in U.S. patent application Ser. No. 14/743,981, filed Jun. 18, 2015, entitled Micro Assembled Micro LED Displays and Lighting Elements, the disclosure of which is hereby incorporated by reference herein in its entirety.
As is understood by those skilled in the art, the terms “over”, “under”, “above”, “below”, “beneath”, and “on” are relative terms and can be interchanged in reference to different orientations of the layers, elements, and substrates included in the present disclosure. For example, a first layer on a second layer, in some embodiments means a first layer directly on and in contact with a second layer. In other embodiments, a first layer on a second layer can include another layer there between.
As is also understood by those skilled in the art, the terms “column” and “row”, “horizontal” and “vertical”, and “x” and “y” are arbitrary designations that can be interchanged (unless otherwise clear from context).
Throughout the description, where apparatus and systems are described as having, including, or comprising specific components, or where processes and methods are described as having, including, or comprising specific steps, it is contemplated that, additionally, there are apparatus, and systems of the disclosed technology that consist essentially of, or consist of, the recited components, and that there are processes and methods according to the disclosed technology that consist essentially of, or consist of, the recited processing steps.
It should be understood that the order of steps or order for performing certain action is immaterial so long as operability is maintained. Moreover, two or more steps or actions in some circumstances can be conducted simultaneously. The disclosure has been described in detail with particular express reference to certain embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the following claims.
| Number | Date | Country | |
|---|---|---|---|
| 63445889 | Feb 2023 | US |
