Memory array having a reduced number of metal source lines

Abstract

A flash memory array having a reduced number of metal source lines and increased storage density. The cells are arranged in rows and columns, with the cells in a row having their control gates connected to a common word line and the cells in a column having their drains connected to a common bit line. All of the cell sources of the array are connected together with a combination of doped semiconductor and metal lines. The source metal lines are disposed generally in parallel with the bit lines. In order to reduce the number of source metal lines, the lines are spaced apart by, typically, eight, sixteen or more cell columns. The metal source lines define a sub-array therebetween. The array includes a decoder for accessing two cells in different columns of each sub-array during single reading and programming operations. Thus, each sub-array provides two bits of data rather than the customary one bit. The reduced number of metal source lines saves a significant amount of die area with a only a small sacrifice in increased effective source line resistance.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to memory arrays, and in particular to a memory array of flash memory cells having a plurality of sub-arrays separated by metal source lines in which the number of metal source lines is reduced so as to reduce the size of the array

2. Description of the Related Art

The use of non-volatile memories, particularly flash memories, has greatly increased. There are several types of flash memory arrays used in such memories. One type of conventional array 10 is called a NOR-type array as depicted in FIG. 1 . The memory cells 38 of the array each include a source, a drain and a channel region intermediate to the source and drain. A floating gate is disposed above, and insulated from the channel region and a control gate is disposed above the floating gate. In order to reduce any ambiguity regarding the distinction between the source-and drain, for the N channel memory cells, the drain is defined herein as the element which is positive with respect to the source during memory read operations.

The flash cells 38 are arranged in rows and columns, with each of the cells in a particular row having its control gate connected to a common word line WL N . All of the cells in a particular column have their drains connected to a common bit line 40 . In addition, all of the sources in the array are connected together. Note that some memory systems include arrays having multiple blocks of cells, with the sources of the cells in the same block connected together so as to permit the blocks to be erased separately. When the cells are read, the sources are all usually grounded, with the common designation for ground being V SS . Thus, the source lines are sometimes referred to as V SS lines or connections. As will be explained, the array 10 of FIG. 1 is arranged into sub-arrays, including sub-array 11 and sub-arrays 32 and 36 disposed on either side of sub-array 11 . Only a single column of sub-arrays 32 and 36 is depicted.

The sources of the cells 38 are typically connected together by way of non-metallic lines 42 , such as diffused semiconductor lines, since metal lines occupy a large amount of area. These semiconductor source lines 42 are shown in FIG. 1 running along side the word lines WL N , with the resistance of the semiconductor source lines being represented by lumped resistors R S . A source line 42 is shared with two word lines. The semiconductor lines 42 have a much greater resistance as compared to metal lines and such resistance tends to both reduce the effective cell read current and makes cell programming more difficult by either increasing the amount of time required to program the cells and/or requiring higher programming voltage to program the cell. Thus, metal source lines are used in combination with the semiconductor lines so as to reduce the overall source line resistance. As can be seen in FIG. 1 , the metal source lines 28 , 29 and 30 are effectively connected in parallel with the semiconductor lines.

The metal lines include a plurality of column segments 28 and 30 which extend generally parallel with the columns of cells and a row segment 29 which extends along the bottom of the array interconnecting all of the column segments 28 and 30 together. Typical flash memory arrays may have from 128 to 2048 rows. Typically, a sub-array will have 8, 16 or 32 columns of cells which are disposed intermediate to the metal source line column segments 28 and 30 so as to reduce the number of such metal lines, which, as previously noted, consume a large amount of die area. In the FIG. 1 example, the sub-arrays contain 16 columns of cells 38 between the metal source line column segments 28 and 30 .

As previously noted, FIG. 1 shows one memory sub-array 11 and one column of the two adjacent memory sub-arrays 32 and 36 . A typical array may have 8, 9, 16, 18, 32 or more of such sub-arrays depending upon further decoding and the number of output pins.

As is well known, in order to read a particular cell 38 it is necessary to apply appropriate voltages to the cell by way of the associated word line WL 0 -WL N and the associated bit line 40 . The common source line is usually grounded. Part of the memory address of the cell to be read provided by an associated processor or the like is decoded in the memory by an X decoder (not depicted) so as to apply a read voltage to the word line WL N connected to the cell. The remainder of the address is applied to a Y decoder which will connect an appropriate voltage to the bit lines 40 associated with the cell being read. At the same time, a sense amplifier (not depicted) is connected to the bit line 40 for use in sensing the read current.

As can be seen in FIG. 1 , the Y decoder (only a small portion of which is disclosed) includes a select transistor N associated with each cell column and connected to the bit line 40 of the column. Each of the 16 select transistors N receives a one of 16 select signal Y 0 -Y 15 . Only one of the select signals Y N is made active at any one time during memory read operations so that only one of the 16 select transistors N connected to the common data line DL N is turned on during a read operation.

In a typical memory system, each address contain a word of data, with each word having 8, 16 or more bits. If, for example, each word is 8 bits, a single select transistor N will be turned on in 8 separate memory sub-arrays so that a total of 8 bits will be read out in each read operation. For example, the decoded address may cause select signal Y 4 to go active in 8 separate sub-arrays so that 8 bits are simultaneously connected to separate data line DL N and read out of the memory for a given address.

Typical memory systems also provide that individual cells can be programmed. Such programming sequences are well known and need not be described. However, in such sequences, only one of the cells in a particular sub-array is programmed at one time. Thus, as was true in the case of cell reading, only one select signal Y N of the 16 signals applied to sub-array 11 is made active in a programming operation. Again, a total of 8, 16 or more bits can be programmed at one time depending upon the length of the individual words.

In many memories, there are a plurality of blocks which can be separately erased, as previously noted. In a typical 4 megabit memory with a 16 bit data buss, there are sometimes blocks as small as 64 Kilobits. Such blocks, with the prior art of reading one output per sub-array, could be organized with no more than 256 rows with 16 columns per sub-array because a minimum of 256 columns (16 columns per sub-array times 16 bits being operated on in parallel) would be required; that is unless, there are less columns per sub-array. Eight columns per sub-array would add twice as many metal source lines to the array, but would then allow this 64 Kilobit array to be organized as 512 rows by 128 columns. With the present invention which allows operating on two bits per sub-array, the 64 Kilobit array could be organized as 512 rows by 128 columns with the sub-array having 16 columns per metal source lines. Thus the invention can result in a saving in the overhead of metal source lines in the array while allowing the array to be organized with twice as many rows.

The present invention functions to reduce the number of metal source lines column segments so as to reduce the area occupied by these metal source lines. This is accomplished without significantly increasing the overall source line resistance so that memory reading and programming is not adversely affected. These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.

SUMMARY OF THE INVENTION

A memory array for use in a memory system is disclosed. The array is comprised of non-volatile memory cells, preferably flash memory cells. Each of the cells includes a source, a drain, a channel region intermediate the source and drain, a floating gate disposed over the channel region and insulated from the channel region and a control gate disposed over the floating gate and insulated from the floating gate. The cells being arranged in a plurality of rows and columns, with the cells located in one of the rows having their control gates connected to a common word line and with the cells located in a particular one of the columns having their drains connected to a common bit line and with all of the cells of the array having their sources connected to a common source connection.

The common source connection includes a plurality of doped semiconductor source lines which connect the sources of the cells located in one of the rows together, and a metal source line structure. The metal source line structure includes a plurality of metal source line column segments disposed generally parallel to the bit lines and connects together the doped source lines, with the metal source line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns.

The array further includes decoder means for accessing at least two cells in one of the sub-arrays at the same time for the purpose of reading the at least two cells. The cells are preferably located in separate cell columns spaced N/2 number of cell columns apart in the cell sub-array.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a typical prior art decoding arrangement for NOR type flash memory array.

FIG. 2 is a schematic diagram of one embodiment of the decoding arrangement for a NOR type flash memory array in accordance with the present invention.

FIG. 3A schematically illustrates the effective resistance of conventional memory array for a section of a word line between a pair of metal source line segments; and

FIG. 3B illustrates the effective resistance for a section of a word line between a pair of metal source line column segments in accordance with the present invention.

FIG. 4 is a comparison of the relative effective resistances of FIGS. 3 A and 3 B.

DETAILED DESCRIPTION OF THE INVENTION

Referring again to the drawings, FIG. 2 shows a memory array in accordance with the present invention. The array is similar to the prior art array of FIG. 1 in that each sub-array contains 16 columns of cells 38 which are intermediate the adjacent metal source line column segments. However, the select transistors N and the associated select signals Y are implemented such that two cells can be read at the same time within one sub-array and two cells can be programmed at the same time within one sub-array. Columns 12 - 19 of sub-array 11 have their respective bit lines 40 configured so that the bit lines can be selectively coupled to a first data line DL N and columns 20 - 27 of the sub-array have their bit lines 40 configured so that these bit lines can be selectively coupled to a second data line DL N+1 .

During a read operation, a predetermined select signal Y N is made active as is a corresponding signal Y N′ . Typically, select signals Y N and Y N′ are the same signal. Assume for example, that a cell in column 13 is to be read together with a cell in column 21 . Both signals Y 1 and Y 1′ are made active thereby connecting the associated bit lines 40 to the read voltages on lines 41 - 1 and 41 - 2 , respectively, connected to separate data lines DL N and DL N+1 . In this manner, 2 bits can be read out of each of the sub-arrays. Thus, it is possible to read out a 16 bit word from an array having only 8 metal source line column segments.

Programming is accomplished in a similar manner in that 2 cells can be programmed in a single sub-array at the same time. The two cells are addressed and the appropriate voltages are applied for programming. Again, the number of cells which can be accessed is increased without increasing the number of metal source line column segments.

In order to increase the performance of the FIG. 2 array, the decoder transistors N and the associated select signals Y N and Y N′ should be implemented so that the spacing between the two columns of cells being read or programmed is optimized so to reduce the source line resistance. Preferably, if there are N number of columns between metal source lines then the columns in the sub-array containing the cells to be read and/or programmed at the same time should be spaced N/2 columns apart. The sub-array 11 of FIG. 2 and the associated decoding transistors N and select signal Y N and Y N′ are arranged in this manner. For example, if select signal Y 3 and Y 3′ go active in a read or program operation, cells in columns 15 and 23 are selected, with such columns having the optimized separation.

The reduction in the number of metal column source lines is achieved with little increase in source line resistance. This can be illustrated by comparing the FIG. 1 prior art array with the array of the present invention as shown in FIG. 2 . FIG. 3A represents an equivalent circuit of the FIG. 1 prior art array. The center cell 38 A from column 19 of sub-array 11 is selected for reading, since this is the worst case location when considering source line resistance. The horizontal connection of resistances R 0 -R 16 between the metal source lines 28 and 30 each represent the lump resistance of the diffused semiconductor source lines R S and the memory cell diffusion resistance of the cells R D located in the same row as the selected cell. These resistances R S and R d are assumed to be of equal value and will be referred to collectively as R N . This assumption is made because the length and width of the diffusion in the array V ss connection is very similar in length and width to the V ss diffusion in the memory cell. Assuming that the cell 38 A being read is an erased cell, current I represents the cell current that will flow when the cell is addressed.

FIG. 3B is an equivalent circuit of the FIG. 2 array of the present invention. The near center cell 38 B of the sub-array (column 18 of FIG. 2 ) is being read to establish worst case conditions. The near center cell 38 B is assumed to be in an erased state and is drawing a cell current I equal to current I of cell 38 A of FIG. 3 A. In addition, a second cell 38 C in the same row is being read. Cell 38 C is located 8 columns away (column 26 of FIG. 2 ) from the other cell 38 B being read.

In the case of the FIG. ⅓A array, the maximum equivalent source resistance is the parallel combination of 8R N and 9R N for an effective resistance of 4.24R N . In the case of the FIG. ⅔B array of the present invention, the effective resistance is 4.94R N . FIG. 4 is a graph comparing the effective normalized source resistances versus the column selected ( 1 - 16 ), with curve 44 representing the prior art array and curve 46 representing the array of the present invention. The worst case increase of only 16.7% for the near center columns 6 , 7 , and 10 , 11 for the present invention over the worst case center columns 8 and 9 of the prior art is not so great as to significantly interfere with memory reading or programming operations and in many cases the reduction in die array area more than justifies this trade-off.

Thus, a novel memory array has been disclosed. Although the array has been described in some detail, it is to be understood that certain changes can be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims. For example, the invention has applicability to memory arrays other than flash memory arrays, such as RAM, SRAM and ROM. Also, the present invention has applicability where the drains, rather than sources, are grounded.

Claims

1. A memory device comprising:an array of memory cells arranged in rows and columns, memory cells located in one row are connected to a common word line, and memory cells located in one column are connected to a common bit line; a plurality of first source lines having a first resistance, each of the plurality of first source lines are connected to the memory cells in one row of the array; a second source line having a second resistance which is less than the first resistance, the second source line is connected to the plurality of first source lines in at least two locations which are separated by N number of cell columns, the at least two locations define a sub-array having N number of columns; and a decoder circuit to access two memory cells in the sub-array at the same time for the purpose of reading or writing the two memory cells.

2. The memory device of claim 1 wherein the memory cells are non-volatile.

3. The memory device of claim 1 wherein the memory cells are non-volatile floating gate transistors.

4. The memory device of claim 1 wherein the two memory cells accessed by the decoder circuit are located N/2 memory columns apart.

5. The memory device of claim 1 wherein the plurality of first source lines are fabricated from a semiconductive material, and the second source line is fabricated from metal.

6. The memory device of claim 1 wherein the N number of cell columns are 16 columns.

7. A memory device comprising:an array of memory cells arranged in rows and columns, memory cells located in one row are connected to a common word line, and memory cells located in one column are connected to a common bit line; a plurality of semiconductive source lines, each of the plurality of semiconductive source lines -are connected to the memory cells in one row of the array; a second source line having a resistance which is less than a resistance of the plurality of semiconductive source lines, the second source line is connected to the plurality of semiconductive source lines in at least two locations which are separated by N number of cell columns, the at least two locations define a sub-array having N number of columns; and a decoder circuit to access two memory cells in the sub-array at the same time for the purpose of reading or writing the two memory cells.

8. The memory device of claim 6 wherein the second source line is fabricated from metal.

9. The memory device of claim 6 wherein the memory cells are non-volatile floating gate transistors.

10. The memory device of claim 6 wherein the two memory cells accessed by the decoder circuit are located N/2 memory columns apart.

11. A flash memory device comprising:an array of non-volatile floating gate transistor memory cells arranged in rows and columns, the non-volatile floating gate transistor memory cells have a source, drain and gate nodes, the memory cells located in one row have a gate node connected to a common word line, and memory cells located in one column have a drain node connected to a common bit line; a plurality of semiconductive source lines, each of the plurality of semiconductive source lines are connected to the source nodes of the memory cells in one row of the array; a metal source line connected to the plurality of semiconductive source lines in at least two locations which are separated by N number of cell columns, the at least two locations define a sub-array having N number of columns; and a decoder circuit to access two memory cells in the sub-array at the same time for the purpose of reading or writing the two memory cells.

12. The flash memory device of claim 11 wherein the two memory cells accessed by the decoder circuit are located N/2 memory columns apart.

13. The flash memory device of claim 11 wherein the decoder circuit activates two select transistors coupled to two columns of the array to access the two memory cells.