Patent Application
20140304445
The invention concerns electrical improvements for communication buses between memory controllers and memory subsystems with multiple sockets.
Computer memory subsystems typically have a central memory controller coupled with multiple sockets, each of which can optionally be populated with a module containing one or more ranks of memory devices on its data bus. Only one memory module with at least one rank of memory installed is required for the memory channel to function. Typical memory buses today have one, two, or three sockets. Typical memory modules today contain one, two, or four ranks of memory.
The memory controller is typically wired in a daisy chain configuration with a first socket nearer the memory controller, a second socket further away, and the third socket even further from the memory controller. The position of each socket on the daisy chain affects how it will impact the quality of signals on the bus, and in particular, how fluctuations from effects such as reflections will affect the functioning of the bus.
The optionality of populated and empty sockets, coupled with options to populate each module with one or more ranks of memory, creates a large array of possible configurations. This matrix of loading combinations creates a variety of fluctuations on the electrical signals on the bus, and every combination must be simulated and tested in order to design a high quality memory subsystem. For example, a system with three slots in which any slot may have 0, 1, 2, or 4 ranks of memory has 63 possible combinations to evaluate on its data bus.
The fluctuations on the bus are largely a function of the loading each socketed module presents to the bus, with capacitance being a key aspect of that loading. A four rank module presents approximately four times as much capacitance as a one load module, for example, due to the additional memory devices connected to the bus. Each of the rank populations will therefore inject a unique set of fluctuations onto the bus.
Since the position of the socket relative to the memory controller affects the bus signal quality differently, total loading is not the only factor. Specifically, a configuration such as “empty—one rank—four ranks” is not electrically equivalent to “four ranks—empty—one rank” even though the total capacitance is the same. The fluctuations injected onto the bus are unique for each combination of loadings in each slot.
The data bus on typical memory modules also includes a series damping resistor between the card edge contact (finger) and the memory devices. These series damping resistors reduce the fluctuations on the data bus by partially isolating the loading effects of the memory ranks
Current generation memory devices typically incorporate an on-die termination (ODT) circuit on data bus signals that allows the perturbations on the data bus to be reduced.
Memory subsystems also have address bus signals which have a wider variety of configurations than the data buses. For registered modules, the address bus signals may be coupled to one or two registering clock driver chips on each module, one or both of which may internally provide a resistive termination to a termination voltage VTT with input bus termination (IBT), a function similar to the memory device ODT used on data buses.
For unbuffered modules, the address bus signals may be coupled to 4, 5, 8, 9, 10, 16, or 18 memory devices directly. Unbuffered modules typically terminate resistively to a termination voltage, VTT, at the end of a daisy chain of memory devices. Empty sockets are particularly problematic for unbuffered systems where the lack of termination on the empty socket complicates signal integrity for the memory controller which must design for very different termination environments.
Associated with address bus signals are command signals (examples are RAS#, CAS#, and WE#) , control signals (examples are CS#, CKE and ODT), and clock signals (examples are CK and CK#). While command, control, and clock signals are often routed similarly to address signals, they may have different loading based on the module configuration. For example, a module with two ranks of memory devices may place 18 loads on address, 18 loads on command, 9 loads on control, and 9 loads on clock signals. This creates an imbalance in signal loading that must be considered when designing a memory subsystem.
Termination is a critical part of current system design. Termination schemes reduce the perturbations on data and address signals and their related mask, strobe, command, control and clock signals as well. The reduction in line perturbation is critical to increases the frequency of operation and the reliability of data transferred on those lines. All of the methods described here help reduce perturbations, but cannot eliminate them.
Standard memory modules also contain a serial presence detect (SPD) EEPROM on each module that describes the module's characteristics to the memory controller host processor. Information such as the number of ranks and the module type (e.g., unbuffered or registered) are encoded on the SPD. The number of registering clock driver chips installed on registered modules is also described. The supported frequency range of operation is coded on the SPD. The SPD is coupled to sideband signals (I2C or SMBus) and does not affect the main system bus loading.
A bus loading module simulates, from a loading perspective, the presence of one or more ranks of memory. Inserting bus loading modules into an otherwise empty socket reduces the number of combinations of bus loadings that would otherwise need to be evaluated. For bus signals, the loading may be a series damping resistor, a capacitive load, a termination resistance to a termination voltage VTT, or a combination of any of these. Each signal type such as data, strobe, mask, address, command, control, or clock may require a unique combination of damping, termination, and loading as well as different values for resistance or capacitance. Though less commonly used, inductance may also be used to complete such filters on line perturbations.
Indirectly, the bus loading module simplifies system design and improves the overall quality of the bus by reducing the number of possible combinations of fluctuations.
These bus loading modules are optional. The bus can function without these load modules installed. However, the signal quality improvements when these load modules installed advantageously reduces the bit error rate on the bus and allows higher operating frequency when installed.
The presence of these modules can be detected by having the memory controller execute signal quality tests, or by incorporating a serial presence detect (SPD) EEPROM on each load module to identify its characteristics to the system.
These bus loading modules may be constructed to exactly simulate one of the common loading characteristics such as a one rank module, a two rank module, or a four rank module. Using a simple example of a load module simulating two loads, for example, the matrix of evaluation configurations for a three socket system may be reduced from 63 combinations to 26 combinations, a reduction of more than 58% in complexity by eliminating the combinations with “empty” sockets.
To those skilled in the art, it is clear that the loading can be adjusted based on simulation and testing to provide other advantageous configurations such as 1.5 loads or 3 loads yet provide the benefits of simplification.
Different systems may get better optimization from different load module types. Unique bus load modules may be used for unbuffered memory subsystems, registered memory subsystems, or other configurations, based on typical system loading configurations.
Bus load modules are constructed of typical printed circuit board materials, have a standard outline and pinout for plug-in connectivity in standard memory sockets of the systems in which they are targeted to operate. In its simplest form, a bus loading module wires from the edge connector fingers to capacitive loads on signals using standard surface mount capacitors or embedded capacitive substrates. Each capacitor may have a different value based on the type of signal it is connected to, such as a data bit, strobe, mask, address, command, control, or clock. The values of the capacitances may be chosen to simulate the loading characteristics of one or more ranks of memory, or to represent a different load that improves overall signal quality on the bus.
To reduce ringing on the bus signals from purely capacitive loads, resistors between the edge connector contacts and the load capacitors may be employed to advantageously provide a filtering to complement the signals on the bus to reduce perturbations and reduce signal noise.
Resistive elements to a termination voltage such as VTT may also be incorporated on bus loading modules to reduce reflections on the bus. These may be in addition to capacitive loads for load matching or standalone to simply reduce perturbations on the bus signals.
A serial presence detect (SPD) device may be incorporated onto a bus loading module in order to allow the system to interrogate its capabilities. The EEPROM contents can store information regarding the module type (e.g., unbuffered or registered), the memory generation represented (e.g., DDR4 SDRAM), and the number of rank loads represented on the data signals (e.g., 1, 2, or 4 or another value).
