Claims
- 1. A transistor memory cell comprising:
- a substrate having spaced source and drain regions and a channel region therebetween;
- a first insulating layer disposed on said channel region;
- a floating gate disposed on said first insulating layer and coterminous with said channel region in the width axis of the transistor to form a first capacitor having a first capacitance with said substrate;
- a second insulating layer disposed on said floating gate; and
- a control gate disposed on said second insulating layer caterminous with said floating gate in the length axis of the transistor to form a second capacitor having a second capacitance with said floating gate, said second capacitance being less than said first capacitance, and wherein said first capacitor has a greater effective area and smaller spacing than said second capacitor.
BACKGROUND OF THE INVENTION
This is a continuation of application Ser. No. 803,005 , filed 11/29/85 abandoned.
The present invention relates to a memory cell for an eraseable programmable read only memory (EPROM), and more particularly to an EPROM that is designed to have a high density of memory cells.
An EPROM comprises a plurality of memory cells. Each of said cells typically comprises a transistor having spaced source and drain regions, with a channel region therebetween. Above the channel region is a floating gate, and above the floating gate is control gate. Due to the type of programming used in the prior art, it is necessary to have a relatively large capacitance between the gates and a smaller capacitance between the floating gate and the channel region. This necessitates a relatively large control gate and large floating gate, and therefore a relatively large cell area. A thinner insulating layer between the two gates cannot be used to increase the capacitance therebetween because greater tunnelling current therebetween would undesirably occur.
Further, a typical EPROM cell has avalanche effect currents flowing therein during the WRITE operation, which results in a relatively large power dissipation and permits writing only into a further enhanced mode, thereby increasing the required WRITE and READ circuitry. Still further, only a relatively small fraction of hot (channel current) electrons are transferred to the floating gate thereby contributing to a voltage change on the floating gate. These effects make the WRITE operation relatively slow and inefficient.
It is therefore desirable to have a memory cell that is small, requires a minimum of external circuitry, can be efficiently written in a short amount of time.
A transistor memory cell in accordance with the invention comprises spaced source and drain regions with a channel region therebetween. A floating gate is disposed above the channel region to form a first capacitance therewith and a control gate is disposed above the floating gate to form a second capacitance therewith. The second capacitance is less than the first capacitance, and there is self-alignment in two directions, resulting in a smaller cell area. The side of the floating gate facing the control gate can be textured to allow tunnelling currents to flow therebetween at low voltages, thereby reducing power dissipation during the WRITE operation and increasing the speed thereof. The tunnelling currents allow writing into the depletion mode from an enhancement mode. This permits sharing of common structures for controlling READ and WRITE operations, thus reducing the memory area.
US Referenced Citations (6)
Foreign Referenced Citations (2)
| Number |
Date |
Country |
| 0123249 |
Oct 1984 |
EPX |
| 59-99760 |
Jun 1984 |
JPX |
Non-Patent Literature Citations (1)
| Entry |
| R. M. Anderson et al., "Evidence for Surface Asperity Mechanism of Conductivity in Oxide Grown on Polycrystalline Silicon", Journal of Applied Physics, vol. 43 (1977), pp. 4834-4836. |
Continuations (1)
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Number |
Date |
Country |
| Parent |
803005 |
Nov 1985 |
|
Patent Grant
4947221
