Claims
- 1. A memory device comprising:
a memory cell array, the array including a plurality of memory cells arranged in rows and columns, the rows being separated by isolation trenches; each memory cell comprising:
a trench having a capacitor formed therein; a first pass transistor having a first doped region formed from an outdiffusion of doped material formed within the trench, a second doped region formed adjacent the trench; and gate region formed within the trench, and a gate oxide formed on a sidewall of the trench; and a second pass transistor having a first doped region formed from an outdiffusion of doped material from within the trench, a second doped region formed adjacent the trench, sharing the gate region formed within the trench with the first pass transistor, and having a gate oxide formed on a sidewall of the trench.
- 2. The memory device of claim 1 further comprising a word line connected to the gate region of the first and second pass transistors and a bit line connected to the second doped regions of the first and second pass transistors.
- 3. The memory device of claim 1 further comprising a second memory cell adjacent the first memory cell and comprising a first and second pass transistor, and wherein the first pass transistor of the first memory cell and the first pass transistor of the second memory cell share a common second doped region.
- 4. The memory device of claim 1 wherein the first and second doped regions are formed of n-type material formed within p-type semiconductor material.
- 5. The memory device of claim 1 further comprising:
a trench top oxide formed within the trench between the capacitor and the gate polysilicon.
- 6. The memory device of claim 1 wherein the first doped region outdiffuses from a doped polysilicon material formed within the trench.
- 7. The memory cell of claim 1 wherein the first pass transistor and second pass transistor has a gate length and a gate width, and the gate length is equal to the gate length for the first and second pass transistors.
- 8. The memory cell of claim 2 wherein the word line and bit line are formed of one or more conductive layers comprised of one or more of polysilicon, tungsten, tungsten nitride, and tungsten silicon.
- 9. The memory device of claim 1 wherein the memory cell array is formed in a semiconductor substrate and further comprising:
a second memory cell adjacent a first memory cell and comprising a first and second pass transistor, wherein the first pass transistor of the first memory cell and the first or second pass transistor of the second memory cell share a common bulk contact in the semiconductor substrate.
- 10. The memory device of claim 1 further comprising a self-aligned insulator region formed above the trench providing electrical isolation between the gate region formed within the trench and a the bitline contacting the second doped region.
- 11. The memory device of claim 10 wherein the insulator region is formed of silicon nitride and/or silicon oxide.
- 12. The memory device of claim 2 further comprising a passing word line adjacent the word line and an insulator layer formed between the passing word line and the second doped region formed adjacent the trench.
- 13. The memory device of claim 1 wherein the memory cell array comprises an array of trenches, the array of trenches being arranged in a regularly spaced pattern.
- 14. A method of forming a memory cell, comprising:
forming a buried plate within a semiconductor substrate; forming a deep trench having sidewalls within an active area of a semiconductor substrate; forming an dielectric along the sidewalls of the deep trench; forming a trench collar along a middle portion of the deep trench; filling the trench partly with doped polysilicon, wherein the dopant in the polysilicon is outdiffused into the active area from the trench in those portions not bound by the trench collar during subsequent processing steps; forming a trench top oxide on the polysilicon; forming a gate dielectric on the vertical sidewalls of the trench filling the trench with a gate polysilicon above the trench top oxide; forming a first doped region adjacent one sidewall of the trench and a second doped region adjacent another sidewall of the trench; forming a contact to the gate polysilicon and connecting the gate polysilicon to a word line; and forming a contact to the first and second doped regions and connecting the first and second doped regions to a bit line.
- 15. The method of claim 14 further comprising etching away a portion of the active area to form an isolation trench on each side of the active area and the deep trench and filling the isolation trench with an insulator.
- 16. The method of claim 14 wherein the step of forming an oxide along the sidewalls of the deep trench comprises:
forming a first oxide along a lower portion of the sidewalls of the deep trench; and subsequently forming a gate oxide along an upper portion of the sidewalls of the deep trench.
- 17. The method of claim 15 wherein the active region is divided into a plurality of active regions by isolation trenches and deep trenches.
- 18. The method of claim 14 wherein the outdiffusion of the dopant in the polysilicon forms a third and fourth doped region, and where the first and third doped regions form the drain and source, respectively of a first pass transistor and the second and fourth doped region form the drain and source, respectively, of a second pass transistor, the first and second pass transistors sharing a common gate.
- 19. A memory circuit comprising:
a capacitor, the capacitor being formed in a lower portion of a trench; a logical pass transistor having a vertical gate formed within an upper portion of the trench, and comprising: first and second source regions; first and second drain regions; and a single gate, having a first gate oxide adjacent the first source and drain regions and a second gate oxide adjacent the second source and drain regions.
- 20. The memory circuit of claim 19 wherein the first and second source regions are formed form outdiffusing doped material from within the trench.
- 21. The memory circuit of claim 19 wherein the trench is between five microns and ten microns in depth.
- 22. The memory circuit of claim 20 wherein the doped material is doped polysilicon.
- 23. The memory circuit of claim 19 wherein the vertical gate of the logical pass transistor has a gate width that is equal to the gate length.
- 24. The memory circuit of claim 19 wherein the trench is formed within and interrupts an active region of the silicon that underlies a bit line, and further comprising an isolation trench formed on either side of the active region.
- 25. The memory circuit of claim 19 wherein the first and second source regions and the first and second drain regions and the gate polysilicon are formed of n-type semiconductor material and the active region is formed of p-type semiconductor material.
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is related to co-pending, co-assigned patent application, attorney docket number 01 P 11026 US, which application is incorporated herein by reference.