Patent Application
20200083236
This application is a continuation of International Application No. PCT/CN2018/103223, filed on Aug. 30, 2018, the disclosure of which is hereby incorporated by reference in its entirety.
The present disclosure relates to the field of semiconductor technologies and, in particular, relates to a memory cell, a memory device, and an operation method of a memory cell.
A programmable read-only memory, also known as a one time programmable memory, refers to a read-only memory that is allowed to be written only once. The commonly used structure of the one time programmable memory includes: a fuse structure, an anti-fuse structure, a floating gate structure, and so on. The structure of one time programmable memory structure of the anti-fuse structure is superior to the one time programmable memory of the fuse structure and the floating gate structure in safety and reliability.
At present, a structure of one time programmable memory structure of the anti-fuse structure generally includes at least one control tube and one anti-fuse capacitor. In an integrated circuit, one control tube can also be integrated with one capacitor to form an integral structure, so as to form one memory cell of the one-time programmable memory.
However, for the existing one time programmable memory of the anti-fuse structure, it is still needed in principle to generate gate oxide layers of two thicknesses through a dual gate process, and then to constitute one memory cell by one control tube and one anti-fuse capacitor together. The one time programmable memory of such anti-fuse structure is limited by the area of the anti-fuse structure, and the memory capacity is not high.
The present disclosure provides a memory cell, a memory device, and an operation method of a memory cell to increase the memory capacity of a one time programmable memory of an anti-fuse structure.
In a first aspect, an embodiment of the present disclosure provides a memory cell, including:
Optionally, the two ends of the first anti-fuse capacitor are respectively connected to a power end of an external circuit;
Optionally, the two ends of the second anti-fuse capacitor are respectively connected to a power end of an external circuit;
Optionally, the gate tube includes a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
In a second aspect, an embodiment of the present disclosure provides an operation method of a memory cell, which is applied to the memory cell according to any one of the first aspect, where the method includes:
Optionally, when the anti-fuse transistor is a P-type MOSFET, the forming a first voltage difference between the gate and the source of the anti-fuse transistor by controlling magnitude of a gate voltage, a source voltage, a drain voltage and a base voltage of the anti-fuse transistor includes:
Optionally, when the anti-fuse transistor is a P-type MOSFET, the forming a second voltage difference between the gate and the drain of the anti-fuse transistor by controlling magnitude of a gate voltage, a source voltage, a drain voltage and a base voltage of the anti-fuse transistor includes:
Optionally, when the anti-fuse transistor is an N-type MOSFET, the forming a first voltage difference between the gate and the source of the anti-fuse transistor by controlling magnitude of a gate voltage, a source voltage, a drain voltage and a base voltage of the anti-fuse transistor includes:
Optionally, when the anti-fuse transistor is an N-type MOSFET, the forming a second voltage difference between the gate and the drain of the anti-fuse transistor by controlling magnitude of a gate voltage, a source voltage, a drain voltage and a base voltage of the anti-fuse transistor includes:
In a third aspect, an embodiment of the present disclosure provides an operation method of a memory cell, which is applied to the memory cell according to any one of the first aspect, where the method includes:
Optionally, when the anti-fuse transistor is a P-type MOSFET, the acquiring an electrical signal of the source of the anti-fuse transistor includes:
Optionally, when the anti-fuse transistor is an N-type MOSFET, the acquiring an electrical signal of the source of the anti-fuse transistor includes:
In a fourth aspect, an embodiment of the present disclosure provides a memory device, including: at least one memory cell according to any one of the first aspect, a control signal input circuit; where the control signal input circuit is configured to generate a gate voltage, a source voltage, a drain voltage and a base voltage of the anti-fuse transistor, to execute the operation method of a memory cell according to any one of the second aspect on the memory cell.
Optionally, the memory device further includes: a memory cell reading circuit, where the memory cell reading circuit is configured to execute the operation method of a memory cell according to any one of the third aspect.
In a fifth aspect, an embodiment of the present disclosure provides a programming device for a memory cell, including:
In a sixth aspect, an embodiment of the present disclosure provides a reading device for a memory cell, including:
In a seventh aspect, an embodiment of the present disclosure provides a computer readable storage medium, including: instructions, which when executed on a computer, cause the computer to execute the operation method of a memory cell according to any one of the second aspect to program the memory cell according to any one of the first aspect.
In an eighth aspect, an embodiment of the present disclosure provides a computer readable memory medium, including: instructions, which when executed on a computer, cause the computer to execute the operation method of a memory cell according to any one of the third aspect to read a programming result for the memory cell according to any one of the first aspect.
Using the memory cell, the memory and the operation method of a memory cell provided by the present disclosure, a memory cell is constructed by a gate tube and an anti-fuse transistor, the anti-fuse transistor being formed by a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET); the gate tube is electrically connected to the gate of the anti-fuse transistor; where the gate and the source of the anti-fuse transistor respectively form two ends of a first anti-fuse capacitor, and the gate and the drain of the anti-fuse transistor respectively form two ends of a second anti-fuse capacitor. Thus the area of the anti-fuse structure can be reduced, and the memory capacity of the memory cell can be improved.
In order to more clearly illustrate technical solutions in embodiments of the present disclosure or in the prior art, the drawings used in describing the embodiments or the prior art will be briefly described below. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art could obtain other drawings from these drawings without creative effort.
The embodiments of the present disclosure have been shown by the accompanying drawings described above, and will be described in more detail later. The drawings and text descriptions are not intended to limit the scope of the concept of the present disclosure in any way, but to illustrate the concept of the present disclosure for those skilled in the art by reference to specific embodiments.
In order to make purposes, technical solutions and advantages of embodiments of the present disclosure clearer, technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative effort are within the protection scope of the present disclosure.
The terms “first”, “second”, “third”, “fourth”, etc. (if present) in the specification, claims and the above drawings of the present disclosure are used to distinguish similar objects rather than to describe a specific sequence or order. It should be understood that the data used in this way may be interchanged in suitable situations, such that the embodiments of the present disclosure described herein can be implemented, for example, in a sequence other than those illustrated or described herein. In addition, the terms “comprise” and “have” and any variations of them are intended to cover a non-exclusive inclusion. For example, processes, methods, systems, products, or devices that contain a series of steps or units are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to such processes, methods, products or devices.
The technical solutions of the present disclosure will be described in detail below with specific embodiments. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may be not repeated in some embodiments.
Hereinafter, some of the terms in the present application will be explained for easy understanding by those skilled in the art.
1) A programmable read-only memory (PROM) is allowed to be written only once, so it is also called “One Time Programmable ROM” (OTP-ROM). When the PROM is left the factory, the stored contents are all 1, and the user can write data 0 into some of the cells as needed (for part of the PROMs, data is all 0 when leaving the factory, then the user can write 1 into some of the cells) to achieve the purpose of programming.
The technical solutions of the present disclosure and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may be not repeated in some embodiments. Embodiments of the present disclosure will be described below with reference to the accompanying drawings.
When the P-type MOSFET operates as an anti-fuse capacitor, the gate, the source, the drain, and the base of the P-type MOSFET are respectively connected to an external circuit (the voltage applied to the gate, the source, the drain and the base of the P-type MOSFET by the external circuit are denoted as V1, V2, V3, and V4, respectively), a first anti-fuse capacitor is denoted as TR1, and a second anti-fuse capacitor is denoted as TR2. Specifically, V1 is controlled to be a high level, and if the breakdown of TR1 is to be achieved, V3 and V4 are controlled to be the same high level as V1, and V2 is controlled to be a low potential or a zero potential (the purpose is to generate a voltage difference, which could break down the oxide dielectric layer 15 between the gate and the source, at the gate of the P-type MOSFET). Since a breakdown voltage of the oxide dielectric layer 105 is much smaller than a breakdown voltage of a PN junction, after a certain period of voltage pulse action (or continuous voltage action), the first anti-fuse capacitor TR1 is partially broken down, so that the gate and source parts of the P-type MOSFET form a conductive path, thereby achieving a memory function of a cell. The programming principle of the second anti-fuse capacitor TR2 of the P-type MOSFET is similar to that of the first anti-fuse capacitor TR1. Specifically, V1 is controlled to be a high level, and if the breakdown of TR2 is to be achieved, V2 and V4 are controlled to be the same high level as V1, and V3 is controlled to be a low potential or a zero potential (the purpose is to generate a voltage difference, which could break down the oxide dielectric layer 15 between the gate and the drain, at the gate of the P-type MOSFET).
Specifically, if the capacitor C1 is programmed, it is needed to apply the same high levels V1, V3, V4 (to ensure that the capacitor C2 and the capacitor C3 are not broken down) while applying a low level or a zero level V2. Under the premise that a reverse breakdown voltage of a PN junction is much greater than a breakdown voltage of a gate oxide layer, the capacitor C1 is broken down after a period of voltage action, while the diode D1 and the diode D2 stay intact and are not broken down. At this time, the equivalent circuit becomes the circuit shown in
In this embodiment, the anti-fuse transistor may be an N-type MOSFET or a P-type MOSFET. For the specific principle and implementation process for the P-type MOSFET, please refer to the description with reference to
In an optional implementation, a voltage is applied to two ends of the first anti-fuse capacitor through a power end of an external circuit to partially break down an oxide dielectric layer between the gate and the source of the anti-fuse transistor, so that the gate and the source of the anti-fuse transistor form a conductive path to complete programming for the first anti-fuse capacitor. Optionally, the gate tube can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). It should be noted that this embodiment does not limit the specific type of the gate tube. Other switching devices may also be selected as the gate tube, and the function is to complete the selection of the anti-fuse transistor. Taking the gate tube being a MOSFET as an example, a voltage is applied to the gate of the gate tube to make the gate tube in an On state, and when a voltage is applied to the source/drain of the gate tube, the gate tube can apply a voltage to the gate of the anti-fuse transistor, so that the anti-fuse transistor is in an On state.
In another optional implementation, a voltage is applied to two ends of the second anti-fuse capacitor through the power end of the external circuit to partially break down an oxide dielectric layer between the gate and the drain of the anti-fuse transistor, so that the gate and the drain of the anti-fuse transistor form a conductive path to complete programming for the second anti-fuse capacitor. Optionally, the gate tube can be a
Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Taking the gate tube being a MOSFET as an example, a voltage is applied to the gate of the gate tube to make the gate tube in an On state, and when a voltage is applied to the source/drain of the gate tube, the gate tube can apply a voltage to the gate of the anti-fuse transistor, so that the anti-fuse transistor is in an On state. The external circuit described herein may be a circuit other than the gate tube 21, references for which can be found in
In this embodiment, the memory cell is constructed by the gate tube and the anti-fuse transistor, and the anti-fuse transistor is formed by a Metal-Oxide-Semiconductor
Field-Effect Transistor (MOSFET); the gate tube is electrically connected to the gate of the anti-fuse transistor; where the gate and the source of the anti-fuse transistor respectively form two ends of the first anti-fuse capacitor, and the gate and the drain of the anti-fuse transistor respectively form two ends of the second anti-fuse capacitor. Compared with the existing memory cell structure with one gate tube plus one anti-fuse capacitor, one MOSFET can directly form two anti-fuse capacitors in this embodiment, so that the memory capacity of the memory on the same integration area is greatly increased.
S101, form a first voltage difference between the gate and the source of an anti-fuse transistor or form a second voltage difference between the gate and the drain of an anti-fuse transistor, by controlling a gate voltage, a source voltage, a drain voltage and a base voltage of the anti-fuse transistor.
The operation method of a memory cell in this embodiment can be applied to the memory cell shown in
S102, if the first voltage difference is greater than a breakdown voltage of an oxide dielectric layer between the gate and the source of the anti-fuse transistor, complete programming for the first anti-fuse capacitor formed by the gate and the source of the anti-fuse transistor;
In an optional implementation, when the anti-fuse transistor is a P-type MOSFET, the voltages V1, V3, and V4 are controlled to be a high voltage, and the voltage V2 is controlled to be a low voltage or a zero voltage, to form the first voltage difference between the gate and the source of the anti-fuse transistor. Or, V1, V2, V4 are controlled to be a high voltage, and the voltage V3 is controlled to be a low voltage or a zero voltage, to form the second voltage difference between the gate and the drain of the anti-fuse transistor.
In another optional implementation, when the anti-fuse transistor is an N-type MOSFET, V1, V3, and V4 are controlled to be a low voltage, and V2 is controlled to be a high voltage or a zero voltage, to form the first voltage difference between the gate and the source of the anti-fuse transistor. Or, V1, V2, V4 are controlled to be a low voltage, and V3 is controlled to be a high voltage or a zero voltage, to form the second voltage difference between the gate and the drain of the anti-fuse transistor.
In this embodiment, the specific values of the high level and the low level are not limited, and the high level and the low level are a relative amount, the purpose of which is to form a voltage difference between the gate and the source of the anti-fuse transistor. By controlling the first voltage difference to be greater than the breakdown voltage of the oxide dielectric layer between the gate and the source of the anti-fuse transistor, and by maintaining the voltage difference for a period of time, the oxide dielectric layer between the gate and the source of the anti-fuse transistor is partially broken down. After the oxide dielectric layer between the gate and the source of the anti-fuse transistor is partially broken down, a conductive path will be formed between the gate and the source of the anti-fuse transistor, thereby changing the state of the first anti-fuse capacitor formed by the gate and the source of the anti-fuse transistor, and achieving the effect of programming the first anti-fuse capacitor.
In this embodiment, the specific values of the high level and the low level are not limited, and the high level and the low level are a relative amount, the purpose of which is to form a voltage difference between the gate and the drain of the anti-fuse transistor. By controlling the second voltage difference to be greater than the breakdown voltage of the oxide dielectric layer between the gate and the drain of the anti-fuse transistor, and by maintaining the voltage difference for a period of time, the oxide dielectric layer between the gate and the drain of the anti-fuse transistor is partially broken down. After the oxide dielectric layer between the gate and the drain of the anti-fuse transistor is partially broken down, a conductive path will be formed between the gate and the drain of the anti-fuse transistor, thereby changing the state of the second anti-fuse capacitor formed by the gate and the drain of anti-fuse transistor, and achieving the effect of programming the second anti-fuse capacitor.
In this embodiment, the voltages V1, V2, V3, and V4 are respectively applied to the gate, the source, the drain, and the base of the anti-fuse transistor; by controlling the magnitude of the voltages V1, V2, V3, and V4, the first voltage difference between the gate and the source of the anti-fuse transistor is formed, or the second voltage difference between the gate and the drain of the anti-fuse transistor is formed; the first voltage difference is controlled to be greater than the breakdown voltage of the oxide dielectric layer between the gate and the source of the anti-fuse transistor, to perform a programming operation for the first anti-fuse capacitor formed by the gate and the source of the anti-fuse transistor; the second voltage difference is controlled to be larger than the breakdown voltage of the oxide dielectric layer between the gate and the drain of the anti-fuse transistor, to perform the programming for the second anti-fuse capacitance formed by the gate and the drain of the anti-fuse transistor. Compared with the existing memory cell structure with one gate tube plus one anti-fuse capacitor, one MOSFET can directly form two anti-fuse capacitors in this embodiment, so that the memory capacity of the memory on the same integration area is greatly increased. Using the method in this embodiment, programming operations can be performed on any one or two of the two anti-fuse capacitors formed by the MOSFET, and the programming mode is flexible and the efficiency is high.
S201, apply a gate voltage V1 to the gate of an anti-fuse transistor through a gate tube, so that the anti-fuse transistor is in an On state; and apply a source voltage V2, a drain voltage V3, a base voltage V4 to the source, the drain and the base of the anti-fuse transistor, respectively.
In this embodiment, the anti-fuse transistor may be a P-type MOSFET or an N-type MOSFET, for both of which V1 is controlled to be a high voltage, so that the anti-fuse transistor is in the On state.
S202, acquire an electrical signal of the source or the drain of the anti-fuse transistor; where the electrical signal of the source of the anti-fuse transistor corresponds to a programming result for the first anti-fuse capacitor; and the electrical signal of the drain of the anti-fuse transistor corresponds to a programming result for the second anti-fuse capacitor.
In an optional implementation, when the anti-fuse transistor is a P-type MOSFET, V1 is controlled to be a high voltage, V2 and V4 are controlled to be a zero voltage or the same low voltage, and no voltage is applied to V3, so as to acquire a voltage or current signal at the source of the anti-fuse transistor; where a voltage difference between V1 and V2 is much smaller than the oxide layer dielectric breakdown voltage of the anti-fuse transistor. Or, V1 is controlled to be a high voltage, V3 and V4 are controlled to be a zero voltage or the same low voltage, and no voltage is applied to V2, so as to acquire a voltage or current signal at the drain of the anti-fuse transistor; where a voltage difference between V1 and V3 is much smaller than the oxide layer dielectric breakdown voltage of the anti-fuse transistor. It should be noted that the first anti-fuse capacitor and the second anti-fuse capacitor share a power end of an external circuit, therefore, neither the writing process nor the reading process can be performed in parallel. Specifically, the operations of reading data or writing data need to be performed on the first anti-fuse capacitor and the second anti-fuse capacitor successively.
In another optional implementation, when the anti-fuse transistor is an N-type MOSFET, V1 is controlled to be a high voltage, V2 and V4 are controlled to be a zero voltage or the same low voltage, and no voltage is applied to V3, so as to acquire a voltage or current signal at the source of the anti-fuse transistor; where a voltage difference between V1 and V2 is much smaller than the oxide layer dielectric breakdown voltage of the anti-fuse transistor. Or, V1 is controlled to be a high voltage, V3 and V4 are controlled to be a zero voltage or the same low voltage, and no voltage is applied to V2, so as to acquire a voltage or current signal at the drain of the anti-fuse transistor; where a voltage difference between V1 and V3 is much smaller than the oxide layer dielectric breakdown voltage of the anti-fuse transistor.
In this embodiment, the voltage V1 is applied to the gate of the anti-fuse transistor through the gate tube; the voltages V2, V3, and V4 are respectively applied to the source, the drain, and the base of the anti-fuse transistor; by controlling the magnitude of the voltages V1, V2, V3 and V4, the electrical signal of the source or the drain of the anti-fuse transistor is required; where the electrical signal of the source of the anti-fuse transistor corresponds to the programming result for the first anti-fuse capacitor; the electrical signal of the drain of the anti-fuse transistor corresponds to the programming result for the second anti-fuse capacitor. Compared with the existing memory cell structure with one gate tube plus one anti-fuse capacitor, one MOSFET can directly form two anti-fuse capacitors in this embodiment, so that the memory capacity of the memory on the same integration area is greatly increased. The states in the two anti-fuse capacitors formed by the MOSFET can be flexibly read using the method in this embodiment, thereby conveniently acquiring the programming result for the memory cell.
Optionally, the memory device shown in
The memory device of this embodiment can perform the methods shown in
Specifically,
As shown in
Specifically, the storing process of the anti-fuse capacitor TR1 is taken as an example, and the operation methods of other anti-fuse capacitors are similar, which will not be repeated. When the array structure of the memory cells is not programmed, the oxide dielectric layers of all of the anti-fuse transistors stay intact and are not broken down. When programming, first, a voltage is applied to the first gate tube T1 through the first control signal WL1 and the third control signal SL1, so that the first gate tube T1 is turned on (if the first gate tube T1 is an NMOS device, a certain positive voltage is provided to the first control signal WL1 such that the first gate tube T1 is turned on, meanwhile the third control signal SL1 provides a high voltage, and this high voltage is used as a programming voltage of the anti-fuse capacitor TR1); then the control tube BL1 is turned on to provide a current path for programming for the anti-fuse capacitor TR1, meanwhile making the voltages of the base control signal G1 and the third control signal SL1 are same or similar, thereby improving programming rate. This voltage state is maintained for a certain period of time such that the oxide dielectric layer of the anti-fuse capacitor TR1 is broken down, thereby achieving programming for the anti-fuse capacitor TR1.
Specifically, the reading process of the anti-fuse capacitor TR1 is taken as an example, and the operation methods of other anti-fuse capacitors are similar, which will not be repeated. First, a voltage is applied to the first gate tube T1 through the first control signal WL1 and the third control signal SL1, so that the first gate tube T1 is turned on. (If the first gate tube T1 is an NMOS device, the voltage of the first control signal WL1 may be the same as or different from the one for programming, the purpose of which is to provide a certain positive voltage so that the first gate tube T1 is turned on; meanwhile the third control signal SL1 is controlled to be a positive voltage smaller than the programming voltage, and this positive voltage is to read the breakdown or un-breakdown state of the anti-fuse capacitor TR1, so it is much smaller than the breakdown voltage so that it does not affect the state of TR1.) Let the G1 end be grounded, then the control tube BL1 is turned on, providing a current path for programming for the anti-fuse capacitor TR1, and the state of the anti-fuse capacitor TR1 is read at the reading end RL1. (If the anti-fuse capacitor TR1 has been programmed, a high level can be read at RL1, and if the anti-fuse capacitor TR1 is not programmed, a low level is read at RL1).
Optionally, the memory 42 can be either independent or integrated with the processor 41.
When the memory 42 is a device independent from the processor 41, the programming device 40 for the memory cell can further include: a bus 43 for connecting the memory 42 and the processor 41.
Optionally, the memory 52 can be either independent or integrated with the processor 51.
When the memory 52 is a device dependent from the processor 51, the reading device 50 for the memory cell can further include: a bus 53 for connecting the memory 52 and the processor 51.
An embodiment of the present disclosure further provides a computer readable memory medium, including: instructions, which when executed on a computer, cause the computer to execute the operation method of a memory cell of
An embodiment of the present disclosure further provides a computer readable memory medium, including: instructions, which when executed on a computer, cause the computer to execute the operation method of a memory cell of
The computer readable medium includes a computer memory medium and a communication medium, where the communication medium includes any medium that is convenient for transferring the computer program from one location to another. A memory medium may be any available media that can be accessed by a general purpose or special purpose computer. An exemplary memory medium is coupled to the processor to enable the processor to read information from the memory medium, and write information to the memory medium. Of course, the memory medium can also be a part of the processor. The processor and the memory medium may be located in an application specific integrated circuit (ASIC). Additionally, the application specific integrated circuit may be located in the user equipment. Of course, the processor and the memory medium may also exist in a communication device as discrete components.
After considering the specification and practicing the disclosures herein, it will be easy for those skilled in the art to think of other implementations of the present disclosure. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure, which are in accordance with the general principles of the present disclosure and include common knowledge or conventional technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are regarded as illustrative only, the true scope and spirit of the present disclosure are pointed out by the following claims.
It should be understood that the present disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the appended claims.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2018/103223 | Aug 2018 | US |
| Child | 16683140 | US |
