Patent Application
20070258307
This application claims foreign priority benefits under 35 U.S.C. § 119 to co-pending German patent application number DE 10 2006 020 098.5-55, filed 29 Apr. 2006. This related patent application is herein incorporated by reference in its entirety.
A memory cell array of a DRAM memory circuit has word lines and bit lines. In the case of a memory access, first one of the word lines is activated and, as a result, the memory cells arranged on the word line are in each case conductively connected to an associated bit line. During this process, a charge flows from a memory cell capacitance of the memory cell into the bit line. This leads to a deflection of the bit line voltage which can be detected with the aid of a read amplifier.
The memory cell capacitance of a dynamic memory chip is usually formed by means of a memory capacitor which is arranged in the substrate of the memory chip. However, a charge stored in the memory capacitor weakens with time since charges leak off into the surrounding substrate. This can lead to a loss of data in the memory cell. To be able to read out the memory cell with the correct data content, the charge must not drop below a residual charge in the memory cell. The leaking off of the memory cell charge is compensated for by refreshing the memory cell within a defined period of time, i.e. recharging it with the corresponding charge so that an adequate residual charge is permanently present in the memory cell.
Apart from other operating modes, a memory chip can also be operated in a self-refreshing mode in which the memory chip itself arranges for the memory cells to be refreshed. This does not require any commands or addresses to be applied to the memory chip from the outside. Maintaining the charges in the memory capacitances is ensured by internally generated refresh commands, the time intervals between the refresh commands being defined in such a manner that an adequate residual charge is permanently present in the memory cells which leads to a correct reading-out of the content of the memory cell. The interval between the refresh events for refreshing a memory cell significantly determines the current consumption in the self-refresh mode. If the time intervals between the refresh events are short, the risk of a loss of data in the memory cells drops but the current consumption rises. If the intervals between the refresh events are extended for reducing the current consumption, there is a risk of reducing the stored charge below a minimum charge so that a loss of data may occur.
Therefore, a memory circuit should be provided, the current consumption of which is reduced in the self-refresh mode. Further, a method for refreshing memory cells should be provided in which the current consumption is minimized.
A memory circuit is provided which comprises a memory cell array with dynamic memory cells arranged on word lines and bit lines, a selection unit for providing selection information and a refresh circuit for selecting the memory cells in each case in dependence on the selection information and refreshing or not refreshing the selected memory cells so that a respective information item stored therein is maintained.
The memory circuit makes it possible to refresh only those memory cells which are determined by the selection information. Due to the selection information, the refreshing can thus be restricted to the relevant memory cells, e.g. to the memory cells which have previously actually been written to by an application. This can lead to considerable current saving since memory applications frequently only access parts of the memory cell array so that only some of the memory cells need to be refreshed. Since the refreshing of the contents of the memory cells requires a certain current, current can be correspondingly saved by avoiding refreshing memory areas.
A method for refreshing dynamic memory cells in a memory cell array is provided, wherein the memory cells are arranged on word lines and bit lines. The method comprises the steps of providing selection information, selecting memory cells in dependence on the selection information and refreshing the selected memory cells in dependence on the selection information.
The selection unit can have a status memory for storing the selection information. In particular, the selection unit can also have a programming circuit configured to write a first status to the status memory in dependence on a write command on an address of the memory cell array in such a manner that the refresh circuit during a subsequent refresh refreshes the memory cells at the address. The programming circuit may be further configured to write a second status to the status memory in dependence on an enable signal with respect to an address of the memory cell array in such a manner that the refresh circuit suppresses the refreshing of the memory cells at the address during a subsequent refresh. In this manner, a memory area used once can also be enabled again during the operation of the memory circuit so that the information contained therein is discarded by not performing any further refreshing of the relevant memory cells.
Furthermore, a word line decoder can be provided for selecting one of the word lines for activation in dependence on an address information item, the refresh circuit having an address generator which successively provides an address information item for addressing each one of the word lines.
The refresh circuit can also have selection switches which are in each case arranged between the word line decoder and each one of the word lines in order to allow or to prevent an activation of the corresponding word line by the refresh circuit in dependence on the selection information provided by the selection unit.
Further selection switches can be provided which are arranged in parallel with the selection switches, the refresh circuit being arranged for opening the further selection switches in a refresh mode and closing them in a normal operating mode.
In one embodiment, the status memory may have status memory elements which are in each case allocated to one of the word lines, each of the selection switches being connected to an associated status memory element so that the switching state of each of the selection switches depends on a data item stored in the status memory element.
In particular, each of the status memory elements can have a programming circuit for placing the associated status memory element into a first state when writing to a memory cell on one of the word lines and for placing the associated status memory element into a second state when the memory circuit is switched on or an enable signal is provided. For memory elements in the first state, the associated selection switches are closed, and for memory elements in the second state the associated selection switches are opened.
The status memory elements may be provided as dynamic memory cells along one or more bit lines in the memory cell array so that a status memory cell is arranged on each of the word lines and can be read out by activating the word line, wherein first read out amplifiers are provided which are in each case connected to at least one of the bit lines which are connected to the dynamic memory cells and wherein a second read out amplifier is provided which is connected to one of the several bit lines which are connected to the status memory cells, wherein the first and second read out amplifiers can be activated for refreshing, wherein the refresh circuit successively activates the read out amplifiers so that the state of the status memory cell on the activated word line can be detected by the second read out amplifier and the first read out amplifiers can be activated or deactivated in dependence on the state in the status memory cell for amplifying the charge on the associated bit line or the several associated bit lines.
A programming circuit can be provided for writing a first state of a refresh data item which specifies that refreshing is to take place, or a second state which specifies that no refreshing is to take place, to the status memory cells, wherein the first state corresponds to a potential level in the direction of which the status memory cells discharge due to leakage currents in the unaddressed state.
It can be provided that the status memory cell is formed by a number of dynamic memory cells in order to provide a greater charge for storing the first or second state in the status memory cell.
The word lines can be provided with a number of local word line drivers in order to activate in each case sections of the corresponding word line, wherein the word line drivers can be activated in dependence on the content of the status memory cell associated with the corresponding word line.
Each section of the respective word line can be associated with a corresponding status memory cell so that a word line can be refreshed section by section in dependence on the selection information.
The refresh circuit can also have a selection circuit for forwarding the address information to the word line decoder in dependence on the selection information provided by the selection unit. In particular, a number of word line decoders can be provided for a number of memory cell arrays, the selection unit being arranged for forwarding the address information to each of the word line decoders in dependence on the selection information provided by the selection unit.
The features of the embodiments will become clear from the following description, taking in conjunction with the accompanying drawings. It is to be noted, however, that the accompanying drawings illustrate only typical embodiments and are, therefore, not to be considered limiting of the scope of the invention. It may admit other equally effective embodiments.
In the case of dynamic memory cells, the charge is stored in the capacitor 4. In the non-addressed state, however, the capacitor 4 loses its charge in the course of time so that, after some time, the information stored in the memory cell 3 cannot be read out correctly. For this reason, the memory cells are refreshed at regular intervals in familiar manner by successively addressing and activating the word lines 5 so that the charges of the memory cells located on the word line flow to the associated bit lines 6 and are there written back into the corresponding memory cells 3 by means of an amplification process with the aid of the read out amplifier 8 so that the information stored therein is refreshed and, as a result, is protected against loss of information.
The read out amplifiers 8 are usually connected, in each case, to two bit lines, only one memory cell 3 being provided per word line 5 for each of the bit line pairs. A charge in the capacitor 4 of the memory cell 3 is detected by carrying out a charge comparison on the bit lines 6 of the bit line pair with the aid of one of the read out amplifiers 8 since, after the corresponding word line 5 has been addressed on one of the two memory cells located on both bit lines 6 of the bit line pair, the charge of the relevant bit line changes with respect to the charge of the other bit line of the bit line pair.
In a self refresh mode, the memory circuit 1 automatically refreshes the memory cells 3. For this purpose, a refresh counter 10 is provided which generates a refresh address in a refresh address decoder 11 and applies it to the word line decoder 7. In the simplest case, the refresh address decoder 11 generates successive word line addresses X-ADR so that each of the word lines 5 is successively activated for a particular period of time, e.g. 40 ns, and is subsequently deactivated so that the charge of the corresponding memory cell 3 can flow to the bit line, can be amplified there by the read out amplifier 8 and, as a result, due to the selection transistor T completely switched to conduct, the corresponding charge is written back to the capacitors 4 of the relevant memory cells. Following this, the word lines are deactivated again and the bit lines are brought to a common equalizing potential. Following this, the refresh counter 10 is incremented so that a further refresh address is generated in the refresh address decoder 11. If the refresh address decoder reaches the highest possible word line address X-ADR, the next refresh on the word line is carried out with the lowest X address. The self refresh mode is determined by an external self refresh signal SFR with which a first switch 12 and a second switch 13 are driven. With an active self refresh signal SFR, the refresh counter 10 is connected to the refresh address decoder 11 and the latter is connected to the word line decoder 7.
If the word lines 5 are not activated at regular intervals in order to refresh the memory cells located on them, the capacitors 4 of the memory cells 3 lose their charge so that any information stored therein is lost. The status memory elements 19 are part of a status memory 20 wherein, when the operating voltage is applied to the memory circuit, the status memory elements 19 are first loaded with a logical “0” which specifies that the refresh switches 17 are opened so that, when the memory circuit is in the self refresh mode, there can be no refreshing of the memory cells 3 by activating the word lines 5. It is only by writing to memory cells of the memory cell array 2 for the first time that individual word lines on which these memory cells are arranged are selected in that a logical “1” is written into the status memory element 19 associated with the corresponding word line so that the associated selection switch 17 is closed. As a result, the corresponding word line 5 can be activated for refreshing within a short time in the self refresh mode.
To save chip area, a status memory element 19 can be provided for a number of word lines, i.e. the status memory element 19 is used for opening and closing a number of refresh switches 17 for a corresponding number of word lines 5. If previously at least one of the memory cells of the corresponding word lines 5 was written to, a logical “1” is stored in the status memory element 19 associated with the word lines so that the corresponding word lines 5 are regularly refreshed in the self refresh mode. In addition, a status memory element 19 can select word lines of different memory cell arrays 2 (memory banks) so that these are noted for refreshing when there has been writing into a corresponding memory area of one of the memory cell arrays.
Referring to
A second input of the OR gate 32 is connected to an output of a second AND gate 33, at the first input of which the associated decoder output of the word line decoder 7 and of the further word line decoder 20, respectively, is applied. At a second input of the second AND gate 33, an enable signal or UNWRITE is applied which specifies that the memory cells arranged on the word line specified by the word line address hereafter no longer need to be taken into consideration during a refresh process since the data stored therein can be discarded. The release signal UNWRITE enables memory areas of the memory circuit needed once to be released, i.e. to be excepted from the subsequent refresh in order to reduce the current consumption for refreshing the released memory cells.
Where there is a number of banks of the memory circuit, the respective bank address must either be taken into consideration for distinguishing between the several banks during the activation of the corresponding word lines, or the corresponding word lines of all banks are activated in parallel by applying the word line address X-ADR so that during a subsequent write command WRITE or release signal UNWRITE, the state of the flip-flops 30 of all status memory elements 19, 21 allocated to the corresponding word lines is set.
If, as described before, a number of word lines are allocated to one status memory element, the status memory element 19, 21 is set, instead of by a specific word line address X-ADR by an arbitrary word line address X-ADR in the word line address area associated with the status memory element, in conjunction with the write command WRITE. For the implementation, further OR circuits are provided at the first inputs of the first and second AND gate 31, 33, at the respective inputs of which all corresponding decoder outputs of the word line address area of the word line decoder 7 and of the further word line decoder 20, respectively, are applied.
Since the status memory cells on word lines with an even-numbered word line address are arranged on a first bit line of the bit line pair and status memory cells on word lines with an odd-numbered word line address are arranged on a second bit line of the bit line pair, either the data item from the first or second bit line of the bit line pair at which the status memory cells are arranged must be read out depending on via which one of the word lines, i.e. even- or odd-numbered, the status memory cell is read out. In the same manner, attention must be paid to the fact that the status memory cells are written to in dependence on the write command, the release signal UNWRITE and the word line address in the correct manner via the CSL switches 41 depending on word line address. To correctly output the content of the relevant addressed status memory cell, the outputs of the further read out amplifier 40 are connected to a demultiplexer 42 in order to output either the signal level of the first bit line or of the second bit line of the bit line pair at which the status memory cells are arranged and to provide it in a suitable manner to the read out amplifiers 8 so that these only perform a read out if, e.g. a logical “1” is applied.
The read out amplifiers 8 are slightly delayed, at least after the activation of the corresponding word line, so that first the relevant status memory cell can be evaluated by the further read out amplifier 40 and then the read out amplifiers 8 are activated or deactivated in dependence on the status memory value of the status memory cell. On activation of the read out amplifiers 8, a charge difference on the bit line pair connected to them is amplified and, as a result, the memory cell addressed by the activated word line is charged again, i.e. the charge of the capacitor of the memory cell is refreshed. If a logical “0” is read from the status memory cell and a corresponding control signal SS is applied to the read out amplifiers 8, the read out amplifiers 8 do not or do not completely evaluate the charge difference on the corresponding bit line pairs, thus saving the evaluation current. The potential difference of approx. 200 mV due to connecting the memory cells to the bit lines of the respective bit line pair are then equalized by an equalizing circuit (not shown) and, as a result, a medium potential is loaded into the relevant memory cells. If a word line is activated in normal operating mode, the corresponding status memory cell is also read out via the further read out amplifier 40. If then a write command WRITE is received (with the same bank address), a WRITE switch 42 is closed. Depending on whether an even- or odd-numbered word line is activated (indicated by a corresponding signal applied to the switches 45, 46), the write signal is inverted in the inverter 43 and the resultant signal is forwarded to the further read out amplifier 40 as a differential signal via the CSL switches 41. Only a release command UNWRITE, which leads to the provision of a logical “0” via a release switch 44, can lead to a logical “0” being stored in the relevant memory cell. For this purpose, the fact is also taken into consideration whether the status memory cell of the relevant word line is located on an even- or odd-numbered word line and the correct status is written into the status memory cell with the aid of the inverter 43.
Writing to and evaluating the status memory cells can also be carried out when the bit lines are twisted together. In this case, the circuit of the further read out amplifier 40 must be correspondingly adapted.
Since the status memory cells are not predefined after the memory circuit has been switched on, the reading out of the status memory cells can initially lead to arbitrary evaluation results. However, it is necessary to unambiguously predefine the status memory cells after the switch-on of the memory cells so that the status memory cells must first be written to with a logical “0”. This can be done, for example, by means of a suitable test mode in which all word lines are simultaneously activated and when all status memory cells can be simultaneously predefined with a corresponding release command UNWRITE. For this reason, it is appropriate to provide the user of the memory circuit with an additionally corresponding release command for completely releasing all memory cells, i.e. for setting all status memory cells to a state in which none of the word lines are refreshed in a self refresh mode. To distinguish a command for the complete release compared with a release command for an individual word line address, an arbitrary address bit of the bit line address transferred with the release command can be used.
Generally, dynamic memory cells have a preferred potential state which occurs when the memory cells have not been refreshed for a relatively long time or the leakage current is too high. A high potential level as a charge in the capacitors of the memory cell is usually the unstable potential state so that the memory cells typically discharge to a low potential state, i.e. to a physical “0”. First, a stored physical “1” was selected as status memory value for a word line already written, i.e. to be refreshed, and a physical “0” was selected as status memory value for a word line not to be refreshed. This initially arbitrary definition of the status memory values is justifiable as long as it is ensured that the status memory cells are tested for at least the same retention specification as the regular memory cells, i.e. can store the stored information without refreshing for at least as long as the regular memory cells. Otherwise, losing the charge of a status memory cell could lead to a change in the status memory value until the next refresh process. Such a change in status memory value takes place in a memory cell array of the above mentioned type typically from a physical “1” to a physical “0” which, with the present definition, would have the consequence of the status memory value of a used word line changing to the status memory value for an unused word line, i.e. a word line which is not to be refreshed. As a result, a necessary refreshing of one of the word lines could be suppressed and the data in all memory cells actually used for storing data on this word line could be destroyed. For this reason, extensive testing of the status memory cells is necessary for guaranteeing a reliable memory effect.
If the allocation is inverted, i.e. a physical “0” corresponds to a word line which is to be refreshed and a physical “1” corresponds to a word line in which no refreshing needs to take place, a poor retention time of a status memory cell is uncritical for the further operation in the self refresh mode. If the status memory cell is weak, i.e. it loses its stored charge very rapidly from a high charge potential to a low charge potential (from a physical “1” to a physical “0”), memory cells allocated to this actually unused word line are evaluated which results in a slight but unnecessary increase in current in the self refresh mode. Thus, a functional disturbance in the case of poor status memory cells, i.e. status memory cells with a short retention is prevented by a reduction in the current consumption in the self refresh mode which may be less optimized. It is possible to completely dispense with the testing of the status memory cells by a further test mode with such an allocation of the status signals.
In general, a first status of a status memory value which specifies that refreshing is to take place, and a second status of the refresh data item which specifies that no refreshing is to take place is defined in the status memory cells, wherein the first status corresponds to a potential level in the direction of which the status memory cell discharges due to leakage currents in the unaddressed state. If the charge in the status memory cells changes in the direction of a high charge potential, i.e. in the direction of a physical “1”, the physical “1” is correspondingly defined in such a manner that the corresponding word line is taken into consideration during refreshing and a physical “0” corresponds to a word line which is to remain unconsidered during refreshing.
In the embodiment shown in
It can also be provided that in the case of a number of local word line drivers which subdivides a word line into a number of word line sections, separate status memory cells can be provided for each of the word line sections so that it is possible to define for each word line section whether refreshing is to take place or to be prevented. For this purpose, status memory cells are provided on a number of bit line pairs, the number of bit line pairs with status memory cells corresponding to the number of at least the word line sections which can be refreshed separately from one another. Naturally, it is also conceivable to provide a common status memory cell for a number of word line sections.
The above embodiments were described with reference to the exemplary embodiments with internally generated refresh signals. However, it is also possible to apply the concept to memory circuits in which refresh signals are applied externally to the memory circuit. The concepts for implementing a reduced current consumption in the memory circuit as described in the embodiments can also be combined with one another in order to obtain further embodiments.
The preceding description describes advantageous exemplary embodiments. The features disclosed therein and the claims and the drawings can, therefore, be useful for realizing various embodiments, both individually and in any combination. While the foregoing is directed to specific embodiments, other and further embodiments may be devised without departing from the basic scope, the scope being determined by the claims that follow.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102006020098.5-55 | Apr 2006 | DE | national |
