Memory construction apparatus

Abstract

A memory construction apparatus for automatically forming a logical memory space, thereby making it possible to design an integrated circuit efficiently. A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical conditions defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied. A circuit description-processing section executes circuit description by using the physical memories and the registers that construct each of the extracted optimum logical memories, to thereby generate a circuit description file.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram useful in explaining the principles of a memory construction apparatus;

FIG. 2 is a diagram showing a construction of the table storage section:

FIG. 3 is a diagram showing a logical condition list table;

FIG. 4 is a diagram showing a physical RAM list table;

FIG. 5 is a diagram showing a usable physical RAM/FF limit number table;

FIG. 6 is a flow diagram showing the operation of a logical memory construction-processing section;

FIG. 7 is a diagram showing respective constructions of candidates for a logical memory (candidate logical memories);

FIG. 8 is a diagram showing respective constructions of candidate logical memories;

FIG. 9 is a diagram showing respective constructions of candidate logical memories;

FIG. 10 is a diagram showing respective constructions of candidate logical memories;

FIGS. 11A and 11B are diagrams showing logical memory construction combination list tables;

FIGS. 12A and 12B are diagrams showing logical memory construction combination list tables;

FIGS. 13A and 13B are diagrams showing logical memory construction combination list tables;

FIG. 14 is a diagram showing a logical memory construction list table;

FIG. 15 is a diagram showing a candidate logical memory list table;

FIG. 16 is a diagram showing a candidate logical memory list table;

FIG. 17 is a flow diagram showing process steps of the operation of the optimum construction extraction-processing section;

FIG. 18 is a diagram showing an optimum logical memory construction combination list table;

FIG. 19 is a diagram showing a step in a sequence of changes in the circuit configuration information in the logical memory construction list table;

FIG. 20 is a diagram showing a step in the sequence of changes in the circuit configuration information in the logical memory construction list table;

FIG. 21 is a diagram showing a step in the sequence of changes in the circuit configuration information in the logical memory construction list table;

FIG. 22 is a flow diagram showing the operation of a circuit description-processing section;

FIG. 23 is a diagram showing an example of circuit configuration generated by circuit description transformed into variables;

FIG. 24 is a diagram showing examples of parameters;

FIG. 25 is a diagram showing examples of values of the FIG. 24 parameters;

FIG. 26 is a diagram showing locations for setting the parameters;

FIG. 27 is a diagram showing an example of the arrangement of a logical memory comprised of a single physical RAM;

FIG. 28 is a diagram showing an example of the arrangement of a logical memory comprised of a plurality of physical RAMs;

FIG. 29 is a diagram showing an example of the arrangement of a logical memory comprised of physical RAMs, bit-complementing FFs, and word-complementing FFs;

FIG. 30 is a diagram showing an example of the arrangement of a logical memory comprised of physical RAMs, and word-complementing FFs;

FIG. 31 is a diagram showing an example of the arrangement of a logical memory comprised of physical RAMs, and bit-complementing FFs; and

FIG. 32 is a diagram showing an example of the arrangement of a logical memory formed of word-complementing FFs alone.

Claims

1. A memory construction apparatus that constructs logical memories in designing an integrated circuit, comprising: a logical memory construction-processing section that reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, so as to construct the logical memory that satisfies a logical condition defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities;an optimum construction extraction-processing section that extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that a limit number of usable physical memories and a limit number of usable registers are satisfied; anda circuit description-processing section that describes a circuit using the physical memories and the registers that construct each of the extracted optimum logical memories, to thereby generate a circuit description file.

2. The memory construction apparatus according to claim 1, wherein when generating the candidates for each logical memory, said logical memory construction-processing section compares a bit number of the logical memory and a bit number of a physical memory, and when the bit number of the logical memory is smaller, said logical memory construction-processing section judges that no division in a bit direction is required, whereas when the bit number of the logical memory is larger, said logical memory construction-processing section divides the bit number of the logical memory by the bit number of the physical memory to thereby calculate a number of divisions in the bit direction and a bit number of registers.

3. The memory construction apparatus according to claim 1, wherein when generating the candidates for each logical memory, said logical memory construction-processing section compares a word number of the logical memory and a word number of a physical memory, and when the word number of the logical memory is smaller, said logical memory construction-processing section judges that no division in a bit direction is required, whereas when the word number of the logical memory is larger, said logical memory construction-processing section divides the word number of the logical memory by the word number of the physical memory to thereby calculate a number of divisions in the word direction and a word number of registers.

4. The memory construction apparatus according to claim 1, further comprising a table storage section that stores logical memory construction combination list tables made on a logical condition-by-logical condition basis, for having written therein information on circuit configuration of each candidate logical memory, a logical memory construction list table for having written therein circuit configuration information on each candidate logical memory corresponding to a no bit-complementing and no word-complementing state as a complementing state of the registers that complement an unfilled memory space, a logical memory candidate list table for having written therein circuit configuration information on each candidate logical memory corresponding to a no bit-complementing and word-complementing state, a bit-complementing and no word-complementing state, or a bit-complementing and word-complementing state, as a complementing state of the registers that complement the unfilled memory space, an optimum logical memory construction combination list table for having written therein circuit configuration information on the optimum logical memories each formed by a combination of the physical memories and the registers.

5. The memory construction apparatus according to claim 4, wherein said logical memory construction-processing section writes, in the logical memory construction combination list tables made on a logical condition-by-logical condition basis, the circuit configuration information on each candidate logical memory, the circuit configuration information comprising items of with-or-without bit complement, with-or-without word complement, a name of physical memories, a number of bits and a number of words of each physical memory, a number of the physical memories as counted in a bit direction, a number of the physical memories as counted in a word direction, a total number of the physical memories, a number of bit-complementing registers, a number of word-complementing registers, and a total number of the registers, and each of the logical memory construction combination list tables contains circuit configuration information on all the candidate logical memories which are capable of satisfying an associated one of the logical conditions.

6. The memory construction apparatus according to claim 5, wherein each logical memory construction combination list table contains the candidate logical memories in a state classified into four groups corresponding to the no bit-complementing and no word-complementing state, the no bit-complementing and word-complementing state, the bit-complementing and no word complementing state, and the bit-complementing and word-complementing state, and wherein said logical memory construction-processing section rearranges, in each group, candidate logical memories from an upper row of the table in an increasing order of the total number of physical memories, candidate logical memories having the same total number of physical memories from an upper row of the table in an increasing order of the number of physical memories in the word direction, and candidate logical memories having the same number of physical memories in the word direction from an upper row of the table in an increasing order of the total number of the registers.

7. The memory construction apparatus according to claim 6, wherein from the logical memory construction combination list tables subjected to the rearrangement, said logical memory construction-processing section extracts the candidate logical memories corresponding to the no bit-complementing and no word-complementing state, on a logical condition-by-logical condition basis, and writes the extracted candidate logical memories in the logical memory construction list table, and extracts the candidate logical memories corresponding to the no bit-complementing and word-complementing state, the bit-complementing and no word-complementing state, and the bit-complementing and word-complementing state, on a logical condition-by-logical condition basis, and writes the extracted candidate logical memories in the logical memory candidate list table.

8. The memory construction apparatus according to claim 7, wherein said logical memory construction-processing section rearranges the candidate logical memories from a top of the logical memory candidate list table in an increasing order of the total number of the registers, and candidate logical memories having the same total number of the registers from an upper row of the table in a decreasing order of the number of the physical memories.

9. The memory construction apparatus according to claim 8, wherein said optimum construction extraction-processing section determines a total sum of physical memories in use from a total number of physical memories of each candidate logical memory associated with a corresponding one of the logical conditions in the logical memory construction list table, compares the total sum of physical memories in use and the limit number of usable physical memories, and when the total sum of logical memories in use is smaller, sets the circuit configuration information written in the logical memory construction list table, as the circuit configuration information on the optimum logical memories, and said circuit description-processing section executes circuit description based on the circuit configuration information on the optimum logical memories, whereas when the total sum of physical memories in use is larger, said optimum construction extraction-processing section extracts the circuit configuration information on the optimum logical memories using the logical memory candidate list table subjected to the rearrangement.

10. The memory construction apparatus according to claim 9, wherein said optimum construction extraction-processing section extracts the circuit configuration information on the optimum logical memories using the logical memory candidate list table subjected to the rearrangement, such that a number of registers in use in each highest priority candidate is smaller than a value of the limit number of usable registers for realizing an associated one of the logical conditions, and at the same time a total number of registers used in all the highest priority candidates is smaller than a value of the limit number of usable registers for realizing a construction of logical memories satisfying the logical conditions, and said circuit description-processing section executes circuit description based on the extracted circuit configuration information.