Claims
- 1. A memory system comprising:
- a memory array for storing a plurality of data unit groups, each data unit group comprising one or more data units, each data unit having a relative position within its data unit group and comprising one or more data bits;
- an array reader coupled to the memory array for selectively reading data unit groups from a source area therein, the array reader including a masking circuit for read-filtering the selectively-read data unit groups by masking data units at selected relative positions therein;
- a data aligner coupled to the array reader for aligning the read-filtered data unit groups with a destination area in the memory array by selectively shifting the relative positions of data units in the read-filtered data unit groups; and
- an array writer coupled to the data aligner and the memory array for write-filtering the aligned data unit groups by masking data units at selected relative positions therein and for writing the write-filtered data unit groups to the destination area in the memory array, whereby the memory system may effect a data transfer between the source and destination areas in the memory array.
- 2. The memory system of claim 1 wherein the data units comprise pixels and the data unit groups comprise pixel words.
- 3. The memory system of claim 1 wherein the memory array comprises a Dynamic Random Access Memory (DRAM).
- 4. The memory system of claim 3 wherein the memory array comprises a Triple-Ported Dynamic Random Access Memory (TPDRAM).
- 5. The memory system of claim 1 wherein the array reader comprises a Serial Access Memory (SAM) for storing the selectively read data unit groups, wherein the array reader's masking circuit read-filters data unit groups stored in the SAM by generating a serial clock mask directing the SAM to retain data units having selected relative positions within their data unit groups and to clock out data units having non-selected relative positions within their data unit groups.
- 6. The memory system of claim 1 wherein the data aligner comprises a plurality of multiplexers (MUX's).
- 7. The memory system of claim 1 wherein the data aligner includes a pipeline register for outputting aligned data unit groups to the array writer and aligning subsequent read-filtered data unit groups received from the array reader at substantially the same time.
- 8. The memory system of claim 1 wherein the array writer comprises:
- a write circuit for receiving the aligned data unit groups and writing to the memory array; and
- a write control logic circuit coupled to the write circuit for write-filtering the aligned data unit groups by generating a write enable mask directing the write circuit to retain data units having selected relative positions within their aligned data unit groups and to write data units having non-selected relative positions within their aligned data unit groups to the memory array.
- 9. The memory system of claim 1 wherein the memory array, array reader, data aligner, and array writer are all implemented on a single die.
- 10. The memory system of claim 1 further comprising a controller coupled to the memory array, array reader, data aligner, and array writer for selecting the data unit groups to be read from the source area in the memory array, selecting the data units to be masked in order to read-filter the selectively-read data unit groups, selecting the shift in relative positions of data units within the read-filtered data unit groups in order to align the read-filtered data unit groups with the destination area in the memory array, and selecting the data units to be masked in order to write-filter the aligned data unit groups.
- 11. An integrated circuit die comprising:
- a memory array for storing a plurality of data unit groups, each data unit group comprising one or more data units, each data unit having a relative position within its data unit group and comprising one or more data bits;
- an array reader coupled to the memory array for selectively reading data unit groups from a source area therein, the array reader including a masking circuit for read-filtering the selectively-read data unit groups by masking data units at selected relative positions therein;
- a data aligner coupled to the array reader for aligning the read-filtered data unit groups with a destination area in the memory array by selectively shifting the relative positions of data units in the read-filtered data unit groups; and
- an array writer coupled to the data aligner and the memory array for write-filtering the aligned data unit groups by masking data units at selected relative positions therein and for writing the write-filtered data unit groups to the destination area in the memory array, whereby the integrated circuit die may effect a data transfer between the source and destination areas in the memory array.
- 12. The integrated circuit die of claim 11 wherein the array reader comprises a Serial Access Memory (SAM) for storing the selectively read data unit groups, wherein the array reader's masking circuit read-filters data unit groups stored in the SAM by generating a serial clock mask directing the SAM to retain data units having selected relative positions within their data unit groups and to clock out data units having non-selected relative positions within their data unit groups.
- 13. The integrated circuit die of claim 11 wherein the data aligner comprises a plurality of multiplexers (MUX's).
- 14. The integrated circuit die of claim 11 wherein the data aligner includes a pipeline register for outputting aligned data unit groups to the array writer and aligning subsequent read-filtered data unit groups received from the array reader at substantially the same time.
- 15. The integrated circuit die of claim 11 wherein the array writer comprises:
- a write circuit for receiving the aligned data unit groups and writing to the memory array; and
- a write control logic circuit coupled to the write circuit for write-filtering the aligned data unit groups by generating a write enable mask directing the write circuit to retain data units having selected relative positions within their aligned data unit groups and to write data units having non-selected relative positions within their aligned data unit groups to the memory array.
- 16. The integrated circuit die of claim 11 further comprising a controller coupled to the memory array, array reader, data aligner, and array writer for selecting the data unit groups to be read from the source area in the memory array, selecting the data units to be masked in order to read-filter the selectively-read data unit groups, selecting the shift in relative positions of data units within the read-filtered data unit groups in order to align the read-filtered data unit groups with the destination area in the memory array, and selecting the data units to be masked in order to write-filter the aligned data unit groups.
- 17. An electronic system comprising:
- an input device;
- an output device;
- a processor coupled to the input and output devices; and
- a memory device coupled to the processor, the memory device comprising:
- a memory array for storing a plurality of data unit groups, each data unit group comprising one or more data units, each data unit having a relative position within its data unit group and comprising one or more data bits;
- an array reader coupled to the memory array for selectively reading data unit groups from a source area therein, the array reader including a masking circuit for read-filtering the selectively-read data unit groups by masking data units at selected relative positions therein;
- a data aligner coupled to the array reader for aligning the read-filtered data unit groups with a destination area in the memory array by selectively shifting the relative positions of data units in the read-filtered data unit groups; and
- an array writer coupled to the data aligner and the memory array for write-filtering the aligned data unit groups by masking data units at selected relative positions therein and for writing the write-filtered data unit groups to the destination area in the memory array, whereby the memory device may effect a data transfer between the source and destination areas in the memory array.
- 18. The electronic system of claim 17 wherein the array reader comprises a Serial Access Memory (SAM) for storing the selectively read data unit groups, wherein the array reader's masking circuit read-filters data unit groups stored in the SAM by generating a serial clock mask directing the SAM to retain data units having selected relative positions within their data unit groups and to clock out data units having non-selected relative positions within their data unit groups.
- 19. The electronic system of claim 17 wherein the data aligner comprises a plurality of multiplexers (MUX's).
- 20. The electronic system of claim 17 wherein the data aligner includes a pipeline register for outputting aligned data unit groups to the array writer and aligning subsequent read-filtered data unit groups received from the array reader at substantially the same time.
- 21. The electronic system of claim 17 wherein the array writer comprises:
- a write circuit for receiving the aligned data unit groups and writing to the memory array; and
- a write control logic circuit coupled to the write circuit for write-filtering the aligned data unit groups by generating a write enable mask directing the write circuit to retain data units having selected relative positions within their aligned data unit groups and to write data units having non-selected relative positions within their aligned data unit groups to the memory array.
- 22. The electronic system of claim 17 further comprising a controller coupled to the memory array, array reader, data aligner, and array writer for selecting the data unit groups to be read from the source area in the memory array, selecting the data units to be masked in order to read-filter the selectively-read data unit groups, selecting the shift in relative positions of data units within the read-filtered data unit groups in order to align the read-filtered data unit groups with the destination area in the memory array, and selecting the data units to be masked in order to write-filter the aligned data unit groups.
- 23. A graphical electronic system comprising:
- a video memory array for storing a plurality of pixel words, each pixel word comprising one or more pixels, each pixel having a relative position within its pixel word and comprising one or more data bits;
- an array reader coupled to the video memory array for selectively reading pixel words from a source area therein, the array reader including a masking circuit for read-filtering the selectively-read pixel words by masking pixels at selected relative positions therein;
- a pixel aligner coupled to the array reader for aligning the read-filtered pixel words with a destination area in the video memory array by selectively shifting the relative positions of pixels in the read-filtered pixel words;
- an array writer coupled to the pixel aligner and the video memory array for write-filtering the aligned pixel words by masking pixels at selected relative positions therein and for writing the write-filtered pixel words to the destination area in the video memory array, whereby the graphical electronic system may effect a Bit-Block Transfer (BitBlT) between the source and destination areas in the video memory array; and
- a video output device coupled to the video memory array for displaying images represented by pixels stored therein.
- 24. The graphical electronic system of claim 23 wherein the video memory array comprises a Dynamic Random Access Memory (DRAM).
- 25. The graphical electronic system of claim 24 wherein the video memory array comprises a Triple-Ported Dynamic Random Access Memory (TPDRAM).
- 26. The graphical electronic system of claim 23 wherein the array reader comprises a Serial Access Memory (SAM) for storing the selectively read pixel words, wherein the array reader's masking circuit read-filters pixel words stored in the SAM by generating a serial clock mask directing the SAM to retain pixels having selected relative positions within their pixel words and to clock out pixels having non-selected relative positions within their pixel words.
- 27. The graphical electronic system of claim 23 wherein the pixel aligner comprises a plurality of multiplexers (MUX's).
- 28. The graphical electronic system of claim 23 wherein the pixel aligner includes a pipeline register for outputting aligned pixel words to the array writer and aligning subsequent read-filtered pixel words received from the array reader at substantially the same time.
- 29. The graphical electronic system of claim 23 wherein the array writer comprises:
- a write circuit for receiving the aligned pixel words and writing to the video memory array; and
- a write control logic circuit coupled to the write circuit for write-filtering the aligned pixel words by generating a write enable mask directing the write circuit to retain pixels having selected relative positions within their aligned pixel words and to write pixels having non-selected relative positions within their aligned pixel words to the video memory array.
- 30. The graphical electronic system of claim 23 further comprising a controller coupled to the video memory array, array reader, pixel aligner, and array writer for selecting the pixel words to be read from the source area in the video memory array, selecting the pixels to be masked in order to read-filter the selectively-read pixel words, selecting the shift in relative positions of pixels within the read-filtered pixel words in order to align the read-filtered pixel words with the destination area in the video memory array, and selecting the pixels to be masked in order to write-filter the aligned pixel words.
- 31. A method of performing a data transfer in a memory array, the method comprising:
- storing a plurality of data unit groups in a source area in the memory array, each data unit group comprising one or more data units, each data unit having a relative position within its data unit group and comprising one or more data bits;
- reading the data unit groups from the source area in the memory array;
- read-filtering the data unit groups by selectively masking data units at relative positions therein;
- aligning the data unit groups with a destination area in the memory array by selectively shifting the relative positions of the data units in the data unit groups;
- write-filtering the aligned data unit groups by selectively masking data units at relative positions therein; and
- writing the data unit groups to the destination area in the memory array, thereby effecting a data transfer between the source and destination areas in the memory array.
- 32. The method of claim 31 wherein the step of read-filtering the data unit groups includes storing the data unit groups in a Serial Access Memory (SAM) and generating a serial clock mask directing the SAM to retain data units having selected relative positions within their data unit groups and to clock out data units having non-selected relative positions within their data unit groups.
Parent Case Info
This is a continuation of application Ser. No. 08/360,865, filed Dec. 20, 1994 now U.S. Pat. No. 5,623,624, and a continuation of application Ser. No. 08/012,094, filed Feb. 1, 1993 now abandoned.
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Kind |
5475631 |
Parkinson et al. |
Dec 1995 |
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Continuations (2)
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Number |
Date |
Country |
Parent |
360865 |
Dec 1994 |
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Parent |
12094 |
Feb 1993 |
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