Claims
- 1. A memory access architecture which comprises:
- a random access memory (RAM) array;
- a random access port for accessing said RAM;
- a first serial access memory register (SAM) for reading said RAM, said first SAM having a dedicated first serial port;
- a controller having means for clocking data into and out of components in said architecture;
- a frame buffer implemented within said RAM comprising means for holding an array of data-words wherein each data-word comprises a specified number of data-units wherein each data-unit comprises a specified number of bits;
- means for performing a Bit-block transfer (BitBLT) comprising:
- means for choosing from said frame buffer a subset of data to be transferred;
- said subset comprising a plurality of said data-units in said frame buffer;
- said subset having a leftmost data-unit;
- said leftmost data-unit having a source address;
- means for choosing a destination address;
- said source address corresponding to a first memory location in said frame buffer;
- said destination address corresponding to a second memory location in said frame buffer;
- means for loading said first SAM register with said subset;
- means for calculating a left shift from said source and destination addresses;
- means for transferring said subset from said SAM to said frame buffer beginning at said destination address;
- wherein said means for transferring said subset from said SAM to said frame buffer comprises:
- means for clocking out specific data-units from said SAM into a transfer word;
- a serial clock mask having control of said means for clocking out data-units from said SAM, wherein a first of said data-units occupying a portion of said SAM will or will not be clocked out according to a value of a corresponding portion of said serial clock mask;
- means for shifting the data-units within said transfer word by said left shift;
- means for generating a write enable mask;
- means for writing those data-units enabled by said write enable mask within said transfer word to a destination word.
- 2. The architecture of claim 1, wherein said means for shifting the data-units within said transfer word comprises:
- means for generating a shift field according to said left shift; and
- means for applying said shift field to said transfer word.
- 3. The architecture of claim 2, wherein said means for applying said shift field comprises:
- an alignment unit connected in series between said first SAM register and said random access port.
- 4. The architecture of claim 3, wherein said means for calculating a left shift comprises:
- means for comparing a number of least significant bits (LCB's) of said source and destination addresses, said number of least significant bits being a function of said specified number of bits and said specified number of data-units.
- 5. The architecture of claim 4 wherein said data-word comprises four data-units, wherein each data-unit comprises 8 bits.
- 6. The architecture of claim 5, wherein each of said data-units represents a color/intensity value for a specific pixel in a graphical user interface subsystem.
- 7. The architecture of claim 1, wherein said architecture is implemented on a single integrated circuit chip.
- 8. The architecture of claim 1, wherein said RAM array and said SAM are implemented using a Triple-Ported Dynamic RAM (TPDRAM) assembly.
- 9. The architecture of claim 1, wherein said RAM array and said SAM are implemented using a dual ported RAM assembly.
- 10. The architecture of claim 4, wherein said controller comprises:
- a state machine;
- means for being interrupted during performance of said BitBLT; and
- means for restarting said BitBLT at a point of interruption.
- 11. The architecture of claim 4, wherein said specified number of data-units is variable and said specified number of bits is variable.
- 12. The architecture of claim 1, wherein said means for transferring said subset further comprises:
- a number of transfer cycles;
- means for determining the number of transfer cycles; and
- means for enacting said number of transfer cycles.
- 13. The architecture of claim 12, wherein said means for determining the number of transfer cycles required comprises:
- means for comparing said destination address with the number of data-units in said subset.
- 14. The architecture of claim 13, wherein said means for generating a write enable mask comprises:
- means for comparing during each of said transfer cycles, LSB's of the source and destination addresses, the number of data-units in said subset, and which of said transfer cycles currently being enacted.
- 15. A method of performing a Bit-block transfer in Random Access Memory (RAM) comprising the steps of:
- storing data in said RAM;
- arranging data stored in said RAM into an array of data-units grouped into data-words, each of said data-words comprising a specified number of data-units, each of said data-units comprising a specified number of bits;
- choosing a subset of said data within said array to be transferred,
- said subset comprising a plurality of said data-units adjacent in the array;
- said subset having a left most data-unit;
- assigning to said left most data-unit a source address and a destination address, both of said addresses corresponding to memory locations in said array;
- determining the length in data-words of said subset;
- loading a serial access memory (SAM) register with said subset;
- calculating a left shift from said source and destination addresses;
- transferring said subset from said SAM to said array beginning at said destination address;
- wherein said step of transferring said subset from said SAM to said array comprises:
- generating a serial clock mask;
- clocking out specific data-units corresponding to said serial clock mask from said SAM into a transfer word;
- shifting the data-units within said transfer word by said left shift;
- generating a write enable mask; and,
- writing those data-units enabled by said write enable mask within said transfer word to a destination word within said array.
- 16. The method of claim 15, wherein said step of determining the length in data-words of said subset comprises:
- comparing the destination address with the number of data-units in said subset.
- 17. The method of claim 16, wherein said step of shifting the data-units within said transfer word comprises:
- generating a shift field; and
- applying said shift field to said transfer word.
- 18. The method of claim 17, wherein said step of transferring said subset from said SAM to said array comprises:
- implementing four stages wherein:
- a first and second of said stages comprise writing a first destination data-word to said array,
- a third of said stages comprises writing all middle destination-data-words of said subset to said array, and
- a fourth of said stages comprises writing a last destination word of said subset to said array.
PRIOR APPLICATION
This is a continuation application of Ser. No. 08/012,094 filed Feb. 1, 1993, now abandoned.
US Referenced Citations (6)
Non-Patent Literature Citations (1)
Entry |
Zimmerman et al., Fastbus Readout Controller Card for High Speed Data Acquisition, 1991 Nuclear Science Symposium and Medical Imaging Conference, pp. 794-798. |
Continuations (1)
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Number |
Date |
Country |
Parent |
12094 |
Feb 1993 |
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