Claims
- 1. A multimedia system having an audio/video decoding/decompressing circuit for decoding an encoded/compressed data stream comprising frames of encoded/compressed audio/video data, the circuit comprising:
- a parser for separating the encoded/compressed data stream into encoded/compressed audio data and frames of encoded/compressed video data;
- a memory having addressable storage, coupled to the parser, wherein the memory is address partitioned into a first region for temporary storage of the encoded/compressed audio data and the encoded/compressed video data and a second region comprising a plurality of slots for selectively storing frames of decoded/decompressed video data; and
- a decoder, coupled to the memory, for receiving encoded/compressed video data from the first region of the memory, generating decoded/decompressed video data from the encoded/compressed video data, selectively storing frames of decoded/decompressed video data into corresponding ones of the plurality of slots in the memory, retrieving stored decoded/decompressed video data from the plurality of slots of the memory, and outputting decoded/decompressed video data as a video data stream.
- 2. The audio/video decoding circuit of claim 1, wherein the second region of the memory comprises three slots for storing decoded/decompressed video frames.
- 3. The audio/video decoding circuit of claim 1, wherein the second region of the memory comprises four slots for storing decoded/decompressed video frames.
- 4. The audio/video decoding circuit of claim 2, further comprising:
- a graphics controller, coupled to the decoder and a video monitor, said graphics controller generating graphics data from the video data and displaying the graphics data as an image on the video monitor.
- 5. The audio/video decoding circuit of claim 3, further comprising:
- a graphics controller, coupled to the decoder and a video monitor, said graphics controller generating graphics data from the video data and displaying the graphics data as an image on the video monitor.
- 6. The audio/video decoding circuit of claim 2, further comprising:
- a graphics controller, coupled to the decoder and a digital display, said graphics controller generating graphics data from the video data and displaying the graphics data as an image on the digital display.
- 7. The audio/video decoding circuit of claim 3, further comprising:
- a graphics controller, coupled to the decoder and a digital display, said graphics controller generating graphics data from the video data and displaying the graphics data as an image on the digital display.
- 8. The audio/video decoding circuit of claim 2, further comprising:
- a television signal encoder, coupled to the decoder and a television display, said television signal encoder generating a television signal from the video data and displaying the television signal as an image on the television display.
- 9. The audio/video decoding circuit of claim 3, further comprising:
- a television signal encoder, coupled to the decoder and a television display, said television signal encoder generating a television signal from the video data and displaying the television signal as an image on the television display.
Parent Case Info
This application is a divisional application of application Ser. No. 08/372,794, now U.S. Pat. No. 5,838,380 which is a continuation-in-part of application Ser. No. 08/316,015, filed on Sep. 30, 1994, now U.S. Pat. No. 5,594,660.
US Referenced Citations (6)
Foreign Referenced Citations (1)
Number |
Date |
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2083579 |
Mar 1990 |
JPX |
Divisions (1)
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Number |
Date |
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Parent |
372794 |
Dec 1994 |
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Continuation in Parts (1)
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Number |
Date |
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Parent |
316015 |
Sep 1994 |
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