Patent Application
20250231849
The present application is based on, and claims priority from Taiwan Application Ser. No. 113101796, filed Jan. 17, 2024, the disclosure of which is hereby incorporated by reference herein in its entirety.
The present disclosure relates to an integrated circuit, and in particular, to a memory controller, a solid-state storage device, and a method for monitoring temperature information thereof.
In today's computer systems, a host and a solid-state storage device can be electrically connected to each other through a Peripheral Component Interconnect Express (PCIe) bus. Although data transmission between the host and the conventional solid-state storage device can be performed through the PCIe bus, the conventional solid-state storage device often needs to use other buses other than the PCIe bus to transmit temperature information of one or more components, which is detected by a thermal sensor in the solid-state storage device, to the host in real time. This approach not only increases complexity and manufacturing costs of circuit design and maintenance, but also may cause the host to misjudge the temperature information.
Therefore, the present disclosure provides a memory controller, a solid-state storage device, and a method for monitoring temperature information thereof to resolve the foregoing problems.
An aspect of the present disclosure provides a memory controller. The memory controller includes a Peripheral Component Interconnect Express (PCIe) physical layer, a PCIe media access control (MAC) layer, a Non-Volatile Memory Express (NVMe) conversion circuit, a flash memory control circuit, and a temperature-information calculating circuit. The PCIe physical layer is configured to electrically connect the memory controller to a host through a PCIe bus. The PCIe physical layer includes a first thermal sensor, configured to detect first temperature information of the PCIe physical layer. The PCIe MAC layer is electrically connected to the PCIe physical layer, and configured to convert an access command from the host into a PCIe signal. The NVMe conversion circuit is configured to convert the PCIe signal from the PCIe MAC layer into an NVMe signal. The flash memory control circuit is configured to control data access of the flash memory according to the NVMe signal. The flash memory control circuit includes a second thermal sensor, configured to detect second temperature information of the flash memory control circuit. The temperature-information calculating circuit is configured to calculate average temperature information of the memory controller within a predetermined period according to the first temperature information and the second temperature information. In response to a configuration read packet from the host, the temperature-information calculating circuit loads the average temperature information into a register of the PCIe MAC layer, and the PCIe media access control layer reports the average temperature information stored in the register to the host through the PCIe bus.
Another aspect of the present disclosure provides a method for monitoring temperature information of a solid-state storage device. The solid-state storage device is electrically connected to a host through a Peripheral Component Interconnect Express (PCIe) bus. A memory controller of the solid-state storage device includes a PCIe physical layer, a PCIe media access control (MAC) layer, a flash memory control circuit, and a temperature-information calculating circuit. The method includes the following steps: utilizing a first thermal sensor disposed on the PCIe physical layer and a second thermal sensor disposed on the flash memory control circuit to detect first temperature information of the PCIe physical layer of the memory controller and second temperature information of the flash memory control circuit, respectively; utilizing the temperature-information calculating circuit to calculate average temperature information of the memory controller according to the first temperature information and the second temperature information; utilizing the temperature-information calculating circuit to load the average temperature information into a register of the PCIe media access control layer in response to a configuration read packet from the host; and utilizing the PCIe MAC layer to report the average temperature information stored in the register to the host through the PCIe bus.
Yet another aspect of the present disclosure provides a solid-state storage device, which includes a flash memory and a memory controller. The memory controller includes a PCIe physical layer, a PCIe media access control (MAC) layer, a Non-Volatile Memory Express (NVMe) conversion circuit, a flash memory control circuit, and a temperature-information calculating circuit. The PCIe physical layer is configured to electrically connect the memory controller to a host through a PCIe bus. The PCIe physical layer includes a first thermal sensor, configured to detect first temperature information of the PCIe physical layer. The PCIe MAC layer is electrically connected to the PCIe physical layer, and configured to convert an access command from the host into a PCIe signal. The NVMe conversion circuit is configured to convert the PCIe signal from the PCIe media access control layer into an NVMe signal. The flash memory control circuit is configured to control data access of the flash memory according to the NVMe signal. The flash memory control circuit includes a second thermal sensor, configured to detect second temperature information of the flash memory control circuit. The temperature-information calculating circuit is configured to calculate average temperature information of the memory controller within the predetermined period according to the first temperature information and the second temperature information. In response to a configuration read packet from the host, the temperature-information calculating circuit loads the average temperature information into a register of the PCIe MAC layer. The PCIe MAC layer reports the average temperature information stored in the register to the host through the PCIe bus.
The following description is preferred implementations for completing the disclosure and is intended to describe the basic spirit of the present disclosure, but is not intended to limit the present disclosure. The actual content of the disclosure needs to be referred to the scope of the patent application that follows.
It should be understood that terms such as “include” and “comprise” in the specification are used to indicate the presence of particular technical features, values, method steps, job processing, elements, and/or components, but do not exclude the addition of more other technical features, values, method steps, job processing, elements, components, or any combination thereof.
The use of terms such as “first”, “second”, and “third” in the scope of the patent application are used to modify the elements in the scope of the patent application, and are not used to indicate an order of priority or a precedence relationship between the elements, or a chronological order in execution of the method steps, but are only used to differentiate between elements with the same name.
The term “configured to” may describe or claim that various units, circuits, or other components are “configured to” perform one or more tasks. In such contexts, the term “configured to” is used to imply a structure by indicating that units/circuits/components include a structure (for example, a circuit system) that performs other (one or more) tasks during operation. Therefore, even when a specified unit/circuit/component does not currently operate (for example, is not turned on), it may still be described that the unit/circuit/component is configured to perform the task. Such units/circuits/components used in conjunction with the term “configured to” include hardware, for example, circuits and memories (storing program instructions that can be executed to perform an operation). In addition, the term “configured to” may include a generic structure (for example, a general-purpose circuit system) that is manipulated by using software and/or firmware (for example, an FPGA or a general-purpose processor that executes the software), to operate in a manner capable of executing the (one or more) task to be resolved. The term “configured to” may also include adapting a manufacturing program (for example, a semiconductor manufacturing device) to manufacture a device (for example, an integrated circuit) that is adapted to implement or perform one or more tasks.
As shown in
In some embodiments, the solid-state storage device 20 may include a memory controller 200 and a flash memory 30. The memory controller 200 may be electrically connected to the flash memory 30, and configured to control data access of the flash memory 30. The memory controller 200 is, for example, an integrated circuit, supporting a PCIe protocol and a Non-Volatile Memory Express (NVM Express, NVME). The flash memory 30 is, for example, a NAND flash memory. The memory controller 200 includes a PCIe physical layer 210, a PCIe media access control (MAC) layer 220, an NVMe conversion circuit 230, a flash memory control circuit 240, and a temperature-information calculating circuit 250. The PCIe physical layer 210 may include a physical interface configured for data transmission, for example, the transmitter terminal TX1 and the receiver terminal RX1. The PCIe media access control layer 220 is, for example, a collective term for various circuits and registers with different functions, including a PCIe configuration space 221 and other general control circuits (not shown). The PCIe media access control layer 220 may convert a control signal and data of the host 10 received by the PCIe physical layer 210 through link 16 into a PCIe signal 21. The NVMe conversion circuit 230 is configured to convert the PCIe signal 21 from the PCIe MAC layer 220 into an NVMe signal 22, or convert an NVMe signal 22 from the flash memory control circuit 240 into a PCIe signal 21. The flash memory control circuit 240 is configured to generate a flash memory interface signal 23 according to the NVMe signal 22, to control data access of the flash memory 30. The temperature-information calculating circuit 250 is, for example, configured to calculate average temperature information TA of the memory controller 200 according to temperature information TEMP1 detected by a thermal sensor 211 and temperature information TEMP2 detected by a thermal sensor 241, the details of which will be described later.
In some embodiments, as shown in
Referring to
The data output terminal Q of each of the D flip flops 2501 to 250N is connected to one input terminal of a corresponding AND gates 2511 to 251N. In addition, the other input terminal of each of the AND gates 2511 to 251N receives a corresponding bit of the sampling period signal SP. For example, the AND gate 2511 receives the least significant bit (e.g., SP [0]) of the sampling period signal SP, the AND gate 2512 receives the second least significant bit (e.g., SP [1]) of the sampling period signal SP, and so on. The AND gates 2511 to 251N may generate individual temperature signals S1 to SN, and the adder 2520 may sum up the temperature signals S1 to SN to obtain a sum value SUM. The divider 2530 divides the sum value SUM by a valid number M, where the valid number M is equal to a number of bits in the sampling period signal SP that are equal to 1.
The following examples illustrates the operation of the temperature-information calculating circuit 250 by using several examples. In Examples 1 to 3, it is assumed that the period length of the clock signal CLK is 1 ms, and the number N is 8, indicating that the temperature-information calculating circuit 250 includes 8 D flip flops, which can form a delay chain with a delay of 8 ms, to record temperature information in 8 clock periods. In addition, the width of the sampling period signal SP is 8 bits, and it can be represented by SP [7:0].
In Example 1, the sampling period signal SP [7:0] is set to a binary value of 1111_1111, and the valid number M=8. For these eight valid sampling points, the sampling interval between two adjacent valid sampling points is 1 ms. In other words, the temperature-information calculating circuit 250 uses 1 ms as the sampling interval, and calculates the average temperature information TA of the memory controller 200 within 8 ms.
In Example 2, the sampling period signal SP [7:0] is set to a binary value of 1010_1010, and the valid number M=4. For these four sampling valid sampling points, the sampling interval between two adjacent valid sampling points is 2 ms. In other words, the temperature-information calculating circuit 250 uses 2 ms as the sampling interval, and calculates the average temperature information TA of the memory controller 200 within 8 ms.
In Example 3, the sampling period signal SP [7:0] is set to a binary value of 1000_1000, and the valid number M=2. The sampling interval between these two valid sampling points is 4 ms. In other words, the temperature-information calculating circuit 250 uses 4 ms as the sampling interval, and calculates the average temperature information TA of the memory controller 200 within 8 ms.
In Examples 4 and 5, it is assumed that the clock cycle of the clock signal CLK is 1 ms, and a number N=16, indicating that the temperature-information calculating circuit 250 includes 16 D flip flops, which may form a delay chain with a delay of 16 ms, to record temperature information within 16 clock cycles. In addition, the width of the sampling period signal SP is also 16 bits, and it can be represented by SP [15:0].
In Example 4, the sampling period signal SP [15:0] is set to a binary value of 1111_1111_1111_1111, and the valid quantity M=16. For these 16 sampling valid sampling points, the sampling interval between two adjacent valid sampling points is 1 ms. In other words, the temperature-information calculating circuit 250 uses 1 ms as the sampling interval, and calculates the average temperature information TA of the memory controller 200 within 16 ms.
In Example 5, the sampling period signal SP [15:0] is set to a binary value of 1000_1000_1000_1000, and the valid number M=4. For the 4 sampling valid sampling points, the sampling interval between two adjacent valid sampling points is 4 ms. In other words, the temperature-information calculating circuit 250 uses 4 ms as the sampling interval, and calculates the average temperature information TA of the memory controller 200 within 16 ms.
In some embodiments, when the sampling interval between two adjacent valid sampling points is M clock periods, there will be (M-1) zeros between two adjacent valid bits (e.g., bit value=1) in the sampling period signal SP, where M is a positive integer and M<N. For example, in Example 1, the sampling interval between two valid sampling points is 1 ms=1 clock cycle (e.g., M=1). In this case, the sampling period signal SP [7:0] is a binary value of 1111_1111, indicating that there is no zero between two adjacent bits that are equal to 1 (e.g., M-1=0). In Example 3, the sampling interval between two valid sampling points is 4 ms=4 clock cycles (e.g., M=4). In this case, the sampling period signal SP [7:0] is a binary value of 1000_1000, indicating that there are three zeros between two bits that are equal to 1 (e.g., M-1=3).
In some embodiments, when calculating the sum value SUM of the temperature signals S1 to SN, the adder 2520 separately sums up the first half (e.g., upper half including the 16 most significant bits) and the second half (e.g., lower half including the 16 least significant bits) of the temperature signals S1 to SN, to obtain the sum value SUM. That is, the first half and the second half of the sum value SUM represent the sum value of the temperature information TEMP1 and the sum value of the temperature information TEMP2, respectively. Therefore, the average temperature information TA calculated by the divider 2530 also includes the first half and the second half, representing the average value of the temperature information TEMP1 and the average value of the temperature information TEMP2, respectively.
In some embodiments, the PCIe MAC layer 220 of the solid-state storage device 20 has a register file (not shown) to store the PCIe configuration space 221. The PCIe configuration space 221 may be, for example, represented by a PCIe configuration space 300 shown in
For example, the PCIe configuration space 300 includes a PCI configuration space 312 and a PCIe extension configuration space 310, as shown in
When the solid-state storage device 20 supports the vendor-specific capability, a status register in the configuration space header 302 associated with a capability list is set to 1, and a capability pointer 3021 in the configuration space header 302 records a start address offset of a specific PCIe capability structure (e.g., the PCIe capability structure 306). The specific PCIe capability structure may also include a next capability pointer to provide a start address offset of a next specific PCIe capability structure. The PCIe capability structure 306 is, for example, a memory space of 8 bytes, and its address offset range is between 0xF0 and 0xF7. For convenience of description, the capability pointer 3021 of the configuration space header 302 points to the PCIe capability structure 306 with the start address offset of 0xF0, that is, the address offset range of the PCIe capability structure 306 is between 0xF0 and 0xF7.
In some embodiments, the PCIe capability structure 306 may be represented as a PCIe capability structure 400 in
For convenience of description, the values recorded in fields 402 and 406 are 0x9 and 0x4, respectively. When the value recorded in field 402 is 0x9, it indicates that the solid-state storage device 20 supports the vendor-specific capability, and in this case, the PCIe capability structure 400 can also be referred to as a vendor-specific capability structure. When the value recorded in field 406 is 0x4, it indicates that the length of the vendor-specific capability is 4 bytes. In addition, if the value recorded in field 404 is 0, it indicates that the capability structure 400 does not point to other PCIe capability structures. If the set value recorded in field 404 is not 0, it indicates that the PCIe capability structure 400 points to a next PCIe capability structure with a value recorded in field 404 as the start address offset. Therefore, the host 10 may send a configuration read packet with the address of the value to the solid-state storage device 20, to read a setting value of the next PCIe capability structure.
Therefore, after the host 10 checks the setting values stored in fields 402, 404, and 406 to determine that the solid-state storage device 20 supports the vendor-specific capability and its the capability length, and whether the vendor-specific capability structure points to a next PCIe capability structure, the host 10 rechecks the setting value stored in field 408 to determine the type of the vendor-specific capability supported by the solid-state storage device 20. In this case, when the setting value stored in field 408 is equal to a specific value (e.g., 0x2), the host 10 may determine that the vendor-specific capability supported by the solid-state storage device 20 can report the average temperature information TA of the memory controller 200.
In some embodiments, the host 10 may know, from the setting value of the configuration space header 302, that the start address offset of the PCIe capability structure 306 is 0xF0, and obtain a double-word setting value starting from the start address offset 0xF0 of the PCIe capability structure 306, that is, 4 bytes (including fields 402 to 408) starting from +000h in
In step 502, the host 10 sends a configuration read packet with a specific address to the solid-state storage device 20. For example, the specific address is 0xF4, that is, the start address offset of the average temperature information TA of the PCIe capability structure 306.
In step 504, in response to the configuration read packet, the PCIe MAC layer 220 sends the request signal REQ to the temperature-information calculating circuit 250. For example, the request signal REQ is used to notify the temperature-information calculating circuit 250 to load the currently calculated average temperature information TA of the memory controller 200 into register 222 of the PCIe media access control layer 220. Register 222, for example, corresponds to field 410 of the PCIe capability structure 400.
In step 506, the temperature-information calculating circuit 250 loads the currently calculated average temperature information TA of the memory controller 200 into register 222.
In step 508, the PCIe MAC layer 220 packages the average temperature information TA stored in register 222 into data completion packet, and transmits the data completion packet to the host 10. The data completion packet is, for example, a completion with data transaction layer packet defined in the PCIe standard.
A computer system 6 in
However, in the computer system 6, both the host 50 and memory controller 60 require separate transmission interfaces and related control circuits (e.g., bus controller 650) for bus 58, which increases design complexity and manufacturing costs. When either host 50 or the memory controller 60 has a damaged transmission interface or the control circuit related to the bus 58, the host 50 is unable to obtain the temperature information TEMP3 of the flash memory control circuit 640 (or the solid-state storage device 20). In addition, transmitting the temperature information TEMP3 of the flash memory control circuit 640 to host 50 in real time through bus 58 may cause host 50 to misjudge that the instantaneous temperature of the flash memory control circuit 640 is too high and immediately take relevant cooling measures, thereby affecting the performance of the solid-state storage device 600.
Step 710: utilizing a first thermal sensor and a second thermal sensor to detect first temperature information of a PCIe physical layer and second temperature information of a flash memory control circuit, respectively. For example, the first thermal sensor and the second thermal sensor are, for example, the thermal sensor 211 disposed on the PCIe physical layer 210 and the thermal sensor 241 disposed in the flash memory control circuit 240, respectively. Additionally, the first temperature information and the second temperature information correspond to the temperature information TEMP1 and TEMP2 shown in
Step 720: utilizing the temperature-information calculating circuit 250 to calculate average temperature information TA of the memory controller 200 within a predetermined period according to the first temperature information and the second temperature information. For example, the temperature information TEMP1 detected by the thermal sensor 211 and the temperature information TEMP2 detected by the thermal sensor 241 may be merged into temperature information TEMP, e.g., TEMP=(TEMP1, TEMP2). In addition, the temperature-information calculating circuit 250 may calculate, according to a clock period of a clock signal CLK, a sampling period signal SP, and a number of D flip flops 2501 to 250N, average temperature information within the predetermined period as the average temperature information TA of the memory controller 200, the details of which can be referred to the embodiment of
Step 730: utilizing the temperature-information calculating circuit 250 to load the average temperature information TA into the register 222 of the PCIe media access control layer 220 in response to a configuration read packet from the host 10. For example, step 730 can be divided into the following steps: utilizing the PCIe MAC layer 220 to send a request signal REQ to the temperature-information calculating circuit 250 in response to the configuration read packet from the host 10; and utilizing the temperature-information calculating circuit 250 to load the average temperature information TA into the register 222 of the PCIe media access control layer 220 in response to the request signal REQ. The request signal REQ is used to notify the temperature-information calculating circuit 250 to load the currently calculated average temperature information TA of the memory controller 200 into the register 222. The register 222, for example, corresponds to field 410 of the PCIe capability structure 400.
Step 740: utilizing the PCIe MAC layer 220 to report the average temperature information TA stored in the register 222 to the host 10 through the PCIe bus 15. For example, the PCIe MAC layer 220 packages the average temperature information TA stored in the register 222 into a data completion packet, and transmits the data completion packet to the host 10. The data completion packet is, for example, a completion with data transaction layer packet defined in the PCIe standard.
In view of the above, the memory controller, the solid-state storage device, and the method for monitoring temperature information of a solid-state storage device provided in the present disclosure are capable of storing temperature information of different elements detected by one or more thermal sensors in the memory controller within the predetermined period using the delay chain of the D flip flops within the temperature-information calculating circuit, and the sampling period can be adjusted with the design of the sampling period signal. In addition, the average temperature information of the memory controller calculated by the temperature-information calculating circuit can be stored in the register of a vendor-specific capability structure of the PCIe configuration space, and the host can obtain the average temperature information from the memory controller through the PCIe bus using the configuration read packet of the PCIe protocol. This design allows the memory controller to report its average temperature information within the predetermined period to the host through the PCIe bus, which not only prevents the host from making incorrect judgments and taking cooling measures that restrict the performance of the solid-state storage device but also eliminates the need to use other buses other than the PCIe bus to report the average temperature information to the host, thereby increasing the efficiency of the computer system and reducing the complexity and cost of design and maintenance.
Although the present disclosure is described above with preferred embodiments, the preferred embodiments are not intended to limit the scope of the present disclosure. Any person of ordinary skill in the art may make variations and modifications without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure should be subject to the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 113101796 | Jan 2024 | TW | national |
