Claims
- 1. A system for detecting errors in a memory device, the system comprising:
a memory sub-system comprising:
a plurality of memory cartridges configured to store data words; and a device configured to initiate an internal READ command to the plurality of memory cartridges in response to an event; and a host controller operably coupled to the memory sub-system and comprising error detection logic configured to detect errors in a data word which has been read from the plurality of memory cartridges.
- 2. The system for detecting errors in a memory device, as set forth in claim 1, wherein each of the plurality of memory cartridges comprises a plurality of memory modules.
- 3. The system for detecting errors in a memory device, as set forth in claim 2, wherein each of the plurality of memory modules comprises a Dual Inline Memory Module (DIMM).
- 4. The system for detecting errors in a memory device, as set forth in claim 2, wherein each of the plurality of memory modules comprises a plurality of memory devices configured to store data words.
- 5. The system for detecting errors in a memory device, as set forth in claim 4, wherein each of the plurality of memory devices comprises a Synchronous Dynamic Random Access Memory (SDRAM) device.
- 6. The system for detecting errors in a memory device, as set forth in claim 1, wherein the memory sub-system comprises five memory modules.
- 7. The system for detecting errors in a memory device, as set forth in claim 1, wherein each of the plurality of memory cartridges comprises a memory control device configured to control access to one of the plurality of memory cartridges.
- 8. The system for detecting errors in a memory device, as set forth in claim 7, wherein each of the memory control devices comprises error detection logic configured to detect errors in a data word which has been read from the plurality of memory cartridges.
- 9. The system for detecting errors in a memory device, as set forth in claim 1, wherein the memory controller comprises error detection logic configured to detect errors in a data word during a READ operation.
- 10. The system for detecting errors in a memory device, as set forth in claim 1, wherein the event comprises an operator instruction.
- 11. The system for detecting errors in a memory device, as set forth in claim 1, wherein the event comprises a hot-plug operation.
- 12. The system for detecting errors in a memory device, as set forth in claim 1, wherein the event comprises the expiration of a timer.
- 13. The system for detecting errors in a memory device, as set forth in claim 1, wherein the error detection logic comprises Error Code Correction (ECC) logic.
- 14. The system for detecting errors in a memory device, as set forth in claim 1, wherein the host controller comprises an arbiter configured to schedule accesses to the memory sub-system.
- 15. The system for detecting errors in a memory device, as set forth in claim 14, wherein the device is configured to request an internal READ command in the arbiter.
- 16. A memory sub-system comprising:
a plurality of memory cartridges configured to store data words; and a device configured to initiate an internal READ command to the plurality of memory cartridges in response to an event.
- 17. The memory sub-system, as set forth in claim 16, wherein each of the plurality of memory cartridges comprises a plurality of memory modules.
- 18. The memory sub-system, as set forth in claim 17, wherein each of the plurality of memory modules comprises a Dual Inline Memory Module (DIMM).
- 19. The memory sub-system, as set forth in claim 17, wherein each of the plurality of memory modules comprises a plurality of memory devices configured to store data words.
- 20. The memory sub-system, as set forth in claim 19, wherein each of the plurality of memory devices comprises a Synchronous Dynamic Random Access Memory (SDRAM) device.
- 21. The memory sub-system, as set forth in claim 16, wherein the memory sub-system comprises five memory modules.
- 22. The memory sub-system, as set forth in claim 16, wherein each of the plurality of memory cartridges comprises a memory control device configured to control access to one of the plurality of memory cartridges.
- 23. The memory sub-system, as set forth in claim 22, wherein each of the memory control devices comprises error detection logic configured to detect errors in a data word which has been read from the plurality of memory cartridges.
- 24. The memory sub-system, as set forth in claim 16, wherein the memory controller comprises error detection logic configured to detect errors in a data word during a READ operation.
- 25. The memory sub-system, as set forth in claim 16, wherein the event comprises an operator instruction.
- 26. The memory sub-system, as set forth in claim 16, wherein the event comprises a hot-plug operation.
- 27. The memory sub-system, as set forth in claim 16, wherein the event comprises the expiration of a timer.
- 28. A system for correcting errors detected in a memory device, the system comprising:
a memory sub-system comprising:
a plurality of memory cartridges configured to store data words; and a device configured to initiate an internal READ command to the plurality of memory cartridges in response to an event; and a host controller operably coupled to the memory sub-system and comprising:
an arbiter configured to schedule accesses to the memory sub-system; error detection logic configured to detect errors in a data word which has been read from the plurality of memory cartridges; a memory engine configured to correct the errors detected in the data word which has been read from the plurality of memory cartridges in response to the internal READ command initiated by the device and configured to produce a corrected data word corresponding to the data word in which an error has been detected; scrubbing control logic configured to request a write-back to each memory location in which the error detection logic has detected an error in a data word which has been read from the memory sub-system; and one or more memory buffers configured to store the corrected data word.
- 29. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein each of the plurality of memory cartridges comprises a plurality of memory modules.
- 30. The system for correcting errors detected in a memory device, as set forth in claim 29, wherein each of the plurality of memory modules comprises a Dual Inline Memory Module (DIMM).
- 31. The system for correcting errors detected in a memory device, as set forth in claim 29, wherein each of the plurality of memory modules comprises a plurality of memory devices configured to store data words.
- 32. The system for correcting errors detected in a memory device, as set forth in claim 31, wherein each of the plurality of memory devices comprises a Synchronous Dynamic Random Access Memory (SDRAM) device.
- 33. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein the memory sub-system comprises five memory modules.
- 34. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein each of the plurality of memory cartridges comprises a memory control device configured to control access to one of the plurality of memory cartridges.
- 35. The system for correcting errors detected in a memory device, as set forth in claim 34, wherein each of the memory control devices comprises error detection logic configured to detect errors in a data word which has been read from the plurality of memory cartridges.
- 36. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein the memory controller comprises error detection logic configured to detect errors in a data word during a READ operation.
- 37. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein the event comprises an operator instruction.
- 38. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein the event comprises a hot-plug operation.
- 39. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein the event comprises the expiration of a timer.
- 40. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein the device is configured to request an internal READ command in the arbiter.
- 41. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein the error detection logic comprises Error Code Correction (ECC) logic.
- 42. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein the host controller comprises an arbiter configured to schedule accesses to the memory sub-system.
- 43. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein the memory engine comprises a Redundant Array of Industry Standard Dynamic Integrated Memory Modules (RAID) memory engine configure to detect and correct failures in a memory device.
- 44. The system for correcting errors detected in a memory device, as set forth in claim 28, wherein the host controller comprises one or more logic devices configured to deliver a scrub request to the arbiter.
- 45. The system for correcting errors detected in a memory device, as set forth in claim 44, wherein the arbiter is configured to schedule a scrub of the address location corresponding to the data word in which an error is detected.
- 46. The system for correcting errors detected in a memory device, as set forth in claim 45, comprising a Content Addressable Memory (CAM) controller configured to compare outstanding WRITE requests in the queue of the arbiter with outstanding scrub requests in the queue of the arbiter.
- 47. The system for correcting errors detected in a memory device, as set forth in claim 46, wherein the scrub request is canceled if an address location of a scrub request contained in the queue is the same as the address location of one of the WRITE requests scheduled prior to the scrub request in the queue.
- 48. A method for correcting errors detected in a memory sub-system comprising the acts of:
(a) initiating an internal READ command from a device in the memory sub-system in response to an event, the internal READ command comprising an address corresponding to a specific location in a memory sub-system; (b) transmitting a first set of data, corresponding to the address issued in the internal READ command, from the memory sub-system to a host controller; (c) detecting errors in the first set of data; (d) correcting the errors detected in the first set of data; (e) producing a second set of data from the first set of data, wherein the second set of data comprises corrected data and corresponds to the address in the first set of data; (f) storing the second set of data and corresponding address in a temporary storage device; (g) scheduling a scrub of the address corresponding to the second set of data; and (h) writing the second set of data to the corresponding address location to replace the first set of data in the memory sub-system.
- 49. The method for correcting errors detected in a memory sub-system, as set forth in claim 48, wherein the memory sub-system comprises a plurality of memory cartridges.
- 50. The method for correcting errors detected in a memory sub-system, as set forth in claim 49, wherein each of the plurality of memory cartridges comprises a plurality of memory modules.
- 51. The method for correcting errors detected in a memory sub-system, as set forth in claim 50, wherein each of the plurality of memory modules comprises a plurality of memory devices configured to store data words.
- 52. The method for correcting errors detected in a memory sub-system, as set forth in claim 48, wherein the memory controller comprises a plurality of memory control devices, each of plurality of memory control devices corresponding to one of the plurality of memory cartridges.
- 53. The method for correcting errors detected in a memory sub-system, as set forth in claim 52, wherein each of the plurality of memory cartridges comprises a corresponding memory control device.
- 54. The method for correcting errors detected in a memory sub-system, as set forth in claim 48, wherein the internal READ command is a verify op era t ion request.
- 55. The method for correcting errors detected in a memory sub-system, as set forth in claim 48, wherein the event comprises an operator instruction.
- 56. The method for correcting errors detected in a memory sub-system, as set forth in claim 48, wherein the event comprises a hot-plug operation.
- 57. The method for correcting errors detected in a memory sub-system, as set forth in claim 48, wherein the event comprises the expiration of a timer.
- 58. The method for correcting errors detected in a memory sub-system, as set forth in claim 48, wherein act (c) comprises the act of using ECC methods to detect errors in the first set of data.
- 59. The method for correcting errors detected in a memory sub-system, as set forth in claim 48, wherein act (d) comprises the act of correcting the errors detected in the first set of data using a Redundant Array of Industry Standard Dual Inline Memory Modules (RAID) memory engine configured to detect and correct failures in a memory device.
- 60. The method for correcting errors detected in a memory sub-system, as set forth in claim 59, wherein the second set of data is produced by the RAID memory engine.
- 61. The method for correcting errors detected in a memory sub-system, as set forth in claim 48, wherein the temporary storage device is a buffer.
- 62. The method for correcting errors detected in a memory sub-system, as set forth in claim 48, wherein the scrub is scheduled in an arbitration queue residing in the host controller.
- 63. The method for correcting errors detected in a memory sub-system, as set forth in claim 62, comprising:
comparing outstanding WRITE requests in the arbitration queue with outstanding internal READ command in the arbitration queue; and canceling the scrub request if an address location corresponding with a scrub request contained in the queue is the same as the address location of one of the WRITE requests scheduled prior to the scrub request in the arbitration queue.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application claims priority under 35 U.S.C §119(e) to provisional application 60/178,108 filed on Jan. 26, 2000.
Provisional Applications (1)
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Number |
Date |
Country |
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60178108 |
Jan 2000 |
US |