Patent Application
20090327586
This Application also claims priority of Taiwan Patent Application No. 097123673, filed on Jun. 25, 2008, the entirety of which is incorporated by reference herein.
1. Field of the Invention
The invention relates to a memory device, and in particular relates to a memory device with a forward storing mechanism.
2. Description of the Related Art
An NAND memory can comprise single-level cells (SLC) or multi-level cells (MLC). A single-level cell can store two different digital values, 0 or 1. A multi-level cell can store four different digital values.
The advantages of the single-level cell are that it is stable and fast and the disadvantages thereof are that it has a relatively small storage capacity and high per storage capacity costs. The advantages of the multi-level cell are that it has a large storing capacity and low per storage capacity costs and the disadvantages thereof are that it is unstable and slow. Recently, embedded systems, such as digital cameras or cell phones, use NAND memories as storing media, for example, SD cards, MMC cards, MicroSD cards and CF cards. Due to ever increasing demand for larger storage space, most of the NAND memories use multi-level cells to store data. However, a high level embedded system, such as a laptop, needs to store operating system data to the NAND memories. If laptops use NAND memories comprising multi-level cells to store operating system data, the operating system data may be easily lost, thus making system operation during such a condition, a high risk operation. Meanwhile, laptop costs would increase if laptops use NAND memories comprising single-level cells to store operating system data for safety. Thus, a method for fully utilizing the advantages of SLC and MLC flash to store data is desired.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
An embodiment of a memory device is provided. The memory device comprises a single-level cell memory unit, a multi-level cell memory unit and a control unit. The single-level cell memory unit comprises a first link table. The first link table records link relationships between logic addresses and physical addresses of the single-level cell memory unit. The multi-level cell memory unit comprises a second link table. The second link table records link relationships between logic addresses and physical addresses of the multi-level cell memory unit. The control unit directs data which normally belongs to the single-level cell memory unit to the multi-level cell memory unit or directs data which normally belongs to multi-level cell memory unit to the single-level cell memory unit according to a control signal.
An embodiment of a data storing method is provided. The data storing method comprises receiving a logic address and a data, detecting a flag, and directing the data to a single-level cell memory unit or a multi-level cell memory unit according to the flag and the logic address.
An embodiment of a data storing method is provided. The data storing method comprises sending a control signal to establish a flag, storing a data to a single-level cell memory unit or a multi-level cell memory unit according to the flag, and sending the control signal to unestablish the flag.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The control signal is established by a vendor command from the host 110 or by a switch 131. The single-level cell memory unit 141 comprises a first link table 151 and stores data according to physical addresses of the first link table 151 of the single-level cell memory unit 141. The multi-level cell memory unit 142 comprises a second link table 152 and stores data according to physical addresses of the second link table 152 of the multi-level cell memory unit 142. According to an embodiment of the invention, the control unit 130 directs data which normally belongs to the single-level cell memory unit 141 to the multi-level cell memory unit 142 or directs data which normally belongs to multi-level cell memory unit 142 to the single-level cell memory unit 141 according to the control signal. In addition, the logic addresses are used to determine where data belongs to.
According to another embodiment of the invention, the memory device 120 is a solid state drive (SSD) or a memory card, such as a CF card. The computer system conventionally uses a hard disk to store operation system data. However, the access speed of the hard disk is slower than that of the memory device 120. If the memory device 120 is a solid state drive for storing operation data or important data, the computer system can be faster, because the single-level cell memory unit 141 is more stable and has a longer operating life (more accessing times). For this embodiment, first, the host 110 transmits a vendor command to the control unit 130 to establish a flag as one. Next, the control unit 130 directs storage of important data or operation system data to the single-level cell memory unit 141 to avoid data lost while the data originally belongs to the multi-level memory unit.
According to another embodiment of the invention, a user manually controls the switch 131 to transmit the control signal to establish the flag as one. When the flag is established as one, the control unit 130 directs storage of important data or operation system data to the single-level cell memory unit 141 to avoid data lost.
The invention is not limited to directing storage of data to the single-level cell memory unit 141. Data can be also directed to be stored to the multi-level cell memory unit 142 under constraint.
In addition, when the control signal sets up the flag as one, the control unit 130 will direct data which normally belongs to the MLC memory unit 142 to the SLC memory unit 141. Thus, the SLC link table (first link table) 151 of the SLC memory unit 141 comprises a MLC sub-link table 154 which means some logic addresses of the SLC link table 151 originally directed to physical addresses of the SLC memory unit 141 are now directed to the physical addresses of the MLC memory unit 142. On the other hand, the MLC link table (second link table) 152 of the MLC memory unit 142 also comprises an SLC sub-link table 153 which means some logic addresses of the MLC link table 152 originally directed to physical addresses of the MLC memory unit 142 are now directed to the physical address of the SLC memory unit 141, as shown in
Since the SLC memory unit 141 is more stable and has longer operating life, the invention uses the control signal to establish the flag as a particular value and detects whether the flag equals to the particular value or not to direct data which normally belongs to the MLC memory unit 142 to the SLC memory unit 141 to avoid data lost.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited to thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 97123673 | Jun 2008 | TW | national |
