Patent Application
20250156544
This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0154767 filed in the Korean Intellectual Property Office on Nov. 9, 2023, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to a memory device and a refresh method thereof.
Volatile memory devices, such as dynamic random-access memory (DRAM), store data by storing charges in the capacitor of a memory cell, and read data by determining the charge stored in the capacitor. Since the charge stored in the capacitor may leak over time, the memory device periodically performs a refresh operation.
The memory controller accesses the addresses of the memory device randomly, and may often focus access to particular addresses. As the density of memory cells in memory devices increases, the charge of memory cells in adjacent rows may be affected by the voltage distribution in a certain row. In particular, when a row is attacked by intensive access, data stored in memory cells of adjacent rows of the attacked row may be changed due to the voltage of the activated state of the attacked row. This phenomenon is called rowhammer. Therefore, the effective refresh on the adjacent rows may be needed for a rowhammer care.
The present disclosure attempts to provide a memory device and a refresh method thereof capable of responding to attacks.
A memory device may include an attack row selector configured to receive an activation signal at a first time point, and generate an update signal based on an accumulation value, an attack row register configured to receive an activation row address corresponding to the activation signal, and determine an attack row address based on the update signal and the activation row address, and a victim row determiner configured to determine a victim row address based on the attack row address. The accumulation value may be the number of activation signals received from a second time point before the first time point to the first time point.
A memory device may include a memory cell array including a plurality of memory cells, and a refresh control circuit configured to receive a first activation signal and a first activation row address corresponding to the first activation signal from an external device at a first time point, and determine a victim row address to be refreshed on a victim row in the memory cell array based on an accumulation value. The accumulation value may be the number of activation signals received from a time point of receiving a refresh command from the external device to the first time point.
A refresh method of a memory device may include receiving a first activation signal and a first activation row address corresponding to the first activation signal at a first time point, generating a random number when the first activation signal is received, generating a reference value based on the number of activation signals received from an immediately previous first target row refresh (TRR) time point to the first time point, determining an attack row address based on a magnitude relationship between the random number and the reference value, determining a victim row address based on the attack row address, and performing a refresh operation on a victim row corresponding to the victim row address at a second TRR time point subsequent to the first time point.
In the following detailed description, only certain embodiments of the present disclosure have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.
Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. In a flowchart described with reference to the drawings, an order of operations may be changed, several operations may be merged, some operations may be divided, and specific operations may not be performed.
In addition, expressions written in the singular may be construed in the singular or plural unless an explicit expression such as “one” or “single” is used. Terms including ordinal numbers such as first, second, and the like will be used only to describe various components, and are not to be interpreted as limiting these components. These terms may be used for the purpose of distinguishing one constituent element from other constituent elements.
Referring to
The memory device 110 may include a memory cell array 111 and a refresh control circuit 112. The memory cell array 111 may include a plurality of memory cells defined by a plurality of rows and a plurality of columns. In an embodiment, rows may be defined by wordlines, and columns may be defined as bitlines. The refresh control circuit 112 may detect an attack row (or aggressor row) among the plurality of rows, determine a row address (referred to as a “victim row address”) of a victim row to be refreshed based on a row address (referred to as an “attack row address”) of the attack row, and output the victim row address. In an embodiment, the attack row may be a rowhammer attack row, and the victim row may be a row that is a target of a rowhammer care. In an embodiment, the refresh control circuit 112 may select the attack row address, and may output the victim row address at a refresh time point.
The memory controller 120 may provide signals to the memory device 110 so as to control the memory operation of the memory device 110. The signals may include a command CMD and an address ADDR. In an embodiment, the memory controller 120 may further provide a clock signal to the memory device 110, and may control the operation of the memory device 110 by providing the command CMD and the address ADDR to the memory device 110 synchronously to the clock signal.
In an embodiment, the memory controller 120 may provide the command CMD and the address ADDR to the memory device 110, so as to control memory operations of the memory cell array 111 such as access, read, or write. According to a read operation, data may be transferred from the memory cell array 111 to the memory controller 120, and according to a write operation, data may be transferred from the memory controller 120 to the memory cell array 111.
The command CMD may include an activation command, a read/write command and a refresh command. In an embodiment, the command CMD may further include a precharge command. The activation command may be a command for converting a target row of the memory cell array 111 to an activated state in order to write data in the memory cell array 111 or read data from the memory cell array 111. The memory cell of the target row may be activated (e.g., driven) in response to the activation command. The read/write command may be a command for performing read or write operation in a target memory cell in the row converted to the activated state. The refresh command may be a command for performing the refresh operation in the memory cell array 111. In an embodiment, a control logic circuit (shown in
In an embodiment, the memory controller 120 may access the memory device 110 according to a request from an external host of the memory system 100. The memory controller 120 may communicate with the host by using various protocols.
The memory device 110 may be a storage device based on semiconductor devices. In an embodiment, the memory device 110 may include a dynamic random-access memory (DRAM) device. For example, the memory device 110 may be double data rate synchronous dynamic random-access memory (DDR SDRAM), low-power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus dynamic random-access memory (RDRAM), and the like.
In an embodiment, the memory device 110 may include other volatility or non-volatile memory devices in which refresh operation is used.
Referring to
The memory cell array 210 may include a plurality of memory cells MC. In an embodiment, the memory cell array 210 may include a plurality of memory banks 210a to 210h. Although
The control logic circuit 220 may generate control signals ICS such that the memory device 200 may perform a read operation, a write operation, or a refresh operation. A command decoder included in the control logic circuit 220 may decode the command CMD received from a memory controller (e.g., 120 of
The address buffer 230 may receive the address ADDR provided from the memory controller 120. The address ADDR may include a row address RA indicating a row of the memory cell array 210 and a column address CA indicating a column. The row address RA is provided to the row decoder 250, and the column address CA is provided to the column decoder 260. The row address RA may be provided to the refresh control circuit 290 through the control logic circuit 220, or directly provided to the refresh control circuit 290. In an embodiment, the row address RA may be provided to the row decoder 250 through a row address multiplexer (RA MUX) 251. In an embodiment, the address ADDR may further include a bank address BA indicating a memory bank.
In an embodiment, the memory device 200 may further include the row address multiplexer 251. The row address multiplexer 251 may receive the row address RA from the address buffer 230, and receive a row address REF_RA to be refreshed from the refresh control circuit 290. The row address multiplexer 251 may selectively output the row address RA received from the address buffer 230 and the row address REF_RA received from the refresh control circuit 290 to the row decoder 250. In an embodiment, the row address multiplexer 251 may output the row address REF_RA to be refreshed in response to the internal command signal ICS (e.g., the refresh signal) from the control logic circuit 220.
Although
The row decoder 250 may select a row to be activated from among the plurality of rows of the memory cell array 210 based on a row address RA or REF_RA. For example, the row decoder 250 may apply a driving voltage to the wordline corresponding to the row to be activated. In an embodiment, a plurality of row decoders 250a to 250h corresponding respectively to the plurality of memory banks 210a to 210h may be provided.
The column decoder 260 may select a column to be activated from among the plurality of columns of the memory cell array 210 based on a column address. For example, the column decoder 260 may activate the sense amplifier 211 corresponding to the column address CA through the I/O gating circuit 270. In an embodiment, a plurality of column decoders 260a to 260h corresponding respectively to the plurality of memory banks 210a to 210h may be provided. In an embodiment, the I/O gating circuit 270 gates input/output data, and may include a data latch for storing data read from the memory cell array 210, and a write driver for writing data in the memory cell array 210. Data read from the memory cell array 210 may be detected by the sense amplifier 211, and may be stored in the I/O gating circuit 270 (e.g., the data latch). In an embodiment, plurality of sense amplifier (211a to 211h) corresponding respectively to the plurality of memory banks 210a to 210h may be provided.
In an embodiment, the memory device 200 may further include a bank control logic 240 that generates a bank control signal in response to the bank address BA. In response to the bank control signal, the row decoder 250 corresponding to the bank address BA among the plurality of row decoders 250a to 250h may be activated, and the column decoder 260 corresponding to the bank address BA among the plurality of column decoders 260a to 260h may be activated. The activated row decoder may apply a driving voltage to the wordline corresponding to the row to be activated.
In an embodiment, data read from the memory cell array 210 (e.g., data stored in the data latch) may be provided to the memory controller 120 through the data I/O buffer 280. Data to be written to the memory cell array 210 may be provided from the memory controller 120 to the data I/O buffer 280, and data provided in the data I/O buffer 280 may be provided to the I/O gating circuit 270.
The memory controller 120 may periodically transmit the command CMD related to the refresh operation to the memory device 110. The control logic circuit 220 may schedule the refresh based on the command CMD. Scheduling the refresh may be understood as determining the normal refresh and a ratio of TRR, and periodically generating the normal refresh command and the TRR command based on the determined ratio.
The refresh control circuit 290 may transfer the row address REF_RA to be refreshed to the row decoder 250 in response to the refresh signal among the internal command signal ICS. In an embodiment, the refresh control circuit 290 may include a TRR control circuit 291, a normal refresh control circuit 292 and a refresh row address selector 293. The TRR control circuit 291 and the normal refresh control circuit 292 may generate a row address VRA to which the TRR is to be performed and a row address NRA to which the normal refresh is to be performed based on a predetermined refresh ratio.
The TRR control circuit 291 may output the row address VRA in response to the TRR command among the internal command signal ICS. In an embodiment, the TRR command may be a rowhammer refresh command. The row address VRA may mean the victim row address. The TRR control circuit 291 may detect the attack row address in response to the activation signal among the internal command signal ICS. In an embodiment, the TRR control circuit 291 may determine one of an at least one activation row address corresponding to at least one the activation signal received between temporally adjacent two TRR commands (referred to as a “TRR interval”) as the attack row address. The TRR control circuit 291 may calculate the row address VRA based on the attack row address.
The normal refresh control circuit 292 may output the row address NRA in response to the normal refresh command among the internal command signal ICS. The normal refresh control circuit 292 may calculate the row address NRA to which the normal refresh operation is to be performed, and output the row address NRA in response to the normal refresh command. The normal refresh control circuit 292 may sequentially increase or decrease the row address NRA whenever the normal refresh operation is performed.
The refresh row address selector 293 may selectively output the row address VRA from the TRR control circuit 291 or the row address NRA from the normal refresh control circuit 292. In an embodiment, the refresh row address selector 293 may output the row address NRA from the normal refresh control circuit 292 as the row address REF_RA in response to the normal refresh command, and may output the row address VRA from the TRR control circuit 291 as the refresh the row address REF_RA in response to the TRR command. In an embodiment, the control logic circuit 220 may randomly generate the TRR command or the normal refresh command in response to the refresh command. In an embodiment, the control logic circuit 220 may generate the TRR command and the normal refresh command based on the predetermined refresh ratio, in response to the refresh command.
For example, the memory device 200 may perform TRR based on the TRR command and the row address VRA, and perform the normal refresh based on the normal refresh command and the row address NRA. As such, the memory device 200 may always perform the refresh at the refresh time point, and by selecting one of the activation row addresses with a substantially equivalent probability, may provide robust defense performance with respect to various attack patterns.
Referring to
The attack row selector 310 may receive the activation signal ACT and the TRR command FREF_EN. The attack row selector 310 may generate an update signal CUP based on the activation signal ACT. For example, the attack row selector 310 may generate a first value that is a random number when the activation signal ACT is received. In addition, upon receiving the activation signal ACT, the attack row selector 310 may generate a second value based on the number of received activation signals ACT. The attack row selector 310 may calculate the number of received activation signals ACT from a time point of receiving the TRR command FREF_EN to a current time point. In an embodiment, the attack row selector 310 may calculate the number of received activation signals ACT until the current time point after performing the TRR in response to the TRR command FREF_EN. The number of activation signals ACT may be understood as an accumulation value. In an embodiment, the attack row selector 310 may include a counter for counting the activation signal ACT. The counter may be initialized based on the TRR command FREF_EN. For example, the counter may set to ‘0’ in response to the TRR command FREF_EN of the first level. In an embodiment, the first level of the TRR command FREF_EN may be a high level, but embodiment is not limited thereto.
The attack row selector 310 may compare the first value with the second value, and generate the update signal CUP based on the comparison result. For example, when the first value is smaller than (or smaller than or equal to) the second value, the attack row selector 310 may generate the update signal CUP of a first level. When the first value is greater than or equal to (or greater than) the second value, the attack row selector 310 may generate the update signal CUP of a second level. In an embodiment, the first level of the update signal CUP may be a high level and the second level of the update signal CUP may be a low level, but embodiment is not limited thereto.
The attack row selector 310 may transfer the update signal CUP to the attack row register 320. The attack row selector 310 may perform initialization based on the TRR command FREF_EN.
The attack row register 320 may receive the TRR command FREF_EN, the row address RA, and the update signal CUP. The row address RA may be an address corresponding to the activation signal ACT. The attack row register 320 may store the row address RA based on the update signal CUP. For example, upon receiving the update signal CUP of the first level, the attack row register 320 may store the row address RA. Upon receiving the update signal CUP of the second level, the attack row register 320 may not store the row address RA.
In an embodiment, the attack row register 320 have a queue size of 1, and may store only one row address RA. In this case, upon receiving the update signal CUP of the first level, the attack row register 320 may replace the stored row address with the row address RA.
The attack row register 320 may output the attack row address ARA in response to the TRR command FREF_EN of the first level (e.g., high level). The attack row register 320 may transfer the attack row address ARA to the victim row determiner 330.
The victim row determiner 330 may determine the victim row address VRA based on the attack row address ARA. For example, the victim row determiner 330 may determine an address corresponding to at least one row adjacent to a row corresponding to the attack row address ARA as the victim row address VRA. In an embodiment, the victim row determiner 330 may determine at least one address among rows at ±1 positions based on the attack row address ARA as the victim row address VRA. In an embodiment, the victim row determiner 330 may determine at least one address among rows belonging to a range of ±x (x is an integer larger than 1) based on the attack row address ARA as the victim row address VRA. The victim row determiner 330 may output the victim row address VRA.
Referring to
The counter 311 may receive the TRR command FREF_EN and the activation signal ACT. The counter 311 may count the number of received activation signals ACT and output a counting value CNT. The number of activation signals ACT may be understood as the accumulation value. For example, the counter 311 may count the number of received activation signals ACT from the time point of receiving the TRR command FREF_EN of the first level to a current time point. The counter 311 may transfer the counting value CNT to a reference value generator 313. Upon receiving the TRR command FREF_EN of the first level, the counting counter 311 may initialize the value CNT. The counter 311 may count the number of activation signals ACT received after the TRR command FREF_EN.
The random number generator 312 may receive the activation signal ACT. The random number generator 312 may generate the first value VAL1 that is a random number when the activation signal ACT is received. Depending on the embodiment, the random number generator 312 may be a true random number generator (TRNG), or a pseudo random number generator (PRNG). For example, the random number may be a true random number or a pseudo random number. In an embodiment, when the random number generator 312 is PRNG, the random number generator 312 may be implemented as a linear feedback shift register (LFSR). In an embodiment, the random number generator 312 may generate the first value VAL1, which is a real number in the range of 0 to 1. In an embodiment, the random number generator 312 may generate the first value VAL1, which is an integer in a range of 0 to the maximum value. In an embodiment, when the random number generator 312 is n-bit LFSR, the maximum value may be 2n−1 (n is an integer larger than 1).
The reference value generator 313 may generate the second value VAL2 that is a reference value based on the counting value CNT. In an embodiment, the reference value generator 313 may generate the reciprocal 1/CNT of the counting value CNT as the second value VAL2. For example, the reference value generator 313 may generate ‘1’ as the second value VAL2 upon receiving a first activation signal ACT, and generate ‘ 1/9’ as the second value VAL2 upon receiving a ninth activation signal ACT. For example, the second value VAL2 may have a range of above 0 and below 1. In an embodiment, the reference value generator 313 may generate ‘(a maximum value that may be generated from the random number generator 312)/the counting value CNT’ as the second value VAL2.
The comparator 314 may receive the first value VAL1 and the second value VAL2. The comparator 314 may compare magnitudes of the first value VAL1 with the second value VAL2. In an embodiment, the comparator 314 may compare the first value VAL1 in the range of 0 to 1 with the second value VAL2 of 1/the counting value CNT. In an embodiment, the comparator 314 may compare the first value VAL1 in a range of 0 to the maximum value with the second value VAL2 of ‘(a maximum value that may be generated from the random number generator 312)/the counting value CNT’.
The comparator 314 may generate the update signal CUP based on the comparison result. For example, when the first value VAL1 is smaller than (or smaller than or equal to) the second value VAL2, the comparator 314 may generate the update signal CUP of the first level. When the first value is greater than or equal to (or greater than) the second value, the comparator 314 may generate the update signal CUP of the second level. The comparator 314 may transfer the update signal CUP to the attack row register 320
Referring to
The linear feedback shift register 400 may determine a feedback bit based on a characteristic polynomial having a coefficient of 0 or 1. In the linear feedback shift register 400, the register circuit 410 and the logical operation circuit 420 may be designed based on the characteristic polynomial. For example, when the characteristic polynomial is x10+x7+x2+1, the register circuit 410 may include first to tenth registers, and the logical operation circuit 420 may include first and second logic circuits. For example, in
The register circuit 410 may output feedback bits (bN) bT1 to bT2 based on an input bit. The register circuit 410 may output the feedback bits (bN) bT1 to bT2 to a feedback path of the linear feedback shift register 400. The logical operation circuit 420 may perform logical operation based on the feedback bits (bN) bT1 to bT2 and generate calculation bits (bX) bO1 to bO2. A calculation bit bX finally generated by the logical operation circuit 420 may be input to the register circuit 410 as the input bit. The linear feedback shift register 400 may perform the shift operation based on the bit input to an input terminal, to generate a pseudo-random number sequence.
The register circuit 410 may include first to N-th registers REG1 to REGN (N is an integer larger than 1). The first to N-th registers REG1 to REGN may each store first to N-th bits b1 to bN. Bit values of the first to N-th bits b1 to bN may vary depending on the shift operation.
The logical operation circuit 420 may receive the feedback bits (bN) bT1 to bT2 from the register circuit 410, and perform logical operation based on the feedback bits (bN) bT1 to bT2. The logical operation circuit 420 may include first to M-th logic circuits XOR1 to XORM (M is an integer larger than 1). The first to M-th logic circuits XOR1 to XORM may perform an exclusive OR (XOR) calculation.
An output terminal of a M-th logic circuit XORM may be connected to an M−1-th logic circuit, and the first logic circuit XOR1 may be connected to an output terminal of the second logic circuit. For example, the first logic circuit XOR1 among the first to M-th logic circuits XOR1 to XORM may perform the calculation last, and the calculation result of the first logic circuit XOR1 may be input to the first register REG1.
The first to M-th logic circuits XOR1 to XORM may be connected along the feedback path, and may transfer the calculation result to a front-side logic circuit. For example, the M-th logic circuit XORM may be connected to an output terminal of a N-th register REGN. The M-th logic circuit XORM may be further connected to an output terminal of one of the first to N−1-th registers. An output terminal of the N−1-th register may be connected to the N-th register REGN.
The M-th logic circuit XORM may receive a feedback bit bN from the N-th register REGN, and receive a feedback bit bT2 from one of the first to N−1-th registers. The M-th logic circuit XORM may perform a logical operation on the feedback bit bN and the feedback bit bT2, and generate a calculation bit bO2. The first logic circuit XOR1 may receive a calculation bit bO1 from a back-side logic circuit, and receive a feedback bit bT1 from one of the first to N−1-th registers. The calculation bit bO1 may be a bit generated by a logical operation based on the calculation bit bO2. The first logic circuit XOR1 may perform a logical operation on the calculation bit bO1 and the feedback bit bT1, and generate the calculation bit bX. The first logic circuit XOR1 may transfer the calculation bit bX to the first register REG1.
The first register REG1 may store the calculation bit bX input through the feedback path as a first bit b1. The bit input through the feedback path may be shifted through the first to N-th registers REG1 to REGN based on a control signal.
The linear feedback shift register 400 may output the first value VAL1 through the register circuit 410. Upon receiving the activation signal ACT, the linear feedback shift register 400 may output the first value VAL1. The first value VAL1 may be a random binary code having a predetermined number of bits. For example, the linear feedback shift register 400 may output a random binary code having N bits based on the first to N-th bits b1 to bN stored in the first to N-th registers REG1 to REGN.
Referring to
The attack row register 320 may receive the TRR command FREF_EN, the row address RA, and the update signal CUP. For example, the attack row register 320 may receive the TRR command FREF_EN through a first terminal 321, receive the row address RA through a second terminal 322, and receive the update signal CUP through a third terminal 323. The row address RA may be an address corresponding to the activation signal ACT of
The attack row register 320 may determine whether to store the row address RA based on the update signal CUP. In an embodiment, upon receiving the update signal CUP of the first level (e.g., high level), the attack row register 320 may store the row address RA. Upon receiving the update signal CUP of the second level (e.g., low level), the attack row register 320 may not store the row address RA. Upon receiving the update signal CUP of the second level, the attack row register 320 may maintain the stored register address.
The attack row register 320 may determine whether to output the register address in response to the TRR command FREF_EN. In an embodiment, upon receiving the TRR command FREF_EN of the first level (e.g., high level), the attack row register 320 may output the register address. Upon receiving the TRR command FREF_EN of the second level (e.g., low level), the attack row register 320 may not output the register address. In an embodiment, the second level of the TRR command FREF_EN may be a low level, but embodiment is not limited thereto. For example, the attack row register 320 may continue to maintain or change (update) the register address until the TRR command FREF_EN of the first level is received.
The attack row register 320 may output the register address as the attack row address ARA through a fourth terminal 324. The attack row register 320 may transfer the attack row address ARA to the victim row determiner 330 of
Referring to
The memory device may perform the refresh FREF at the time point t1, and then receive an activation signal and a row address corresponding to the activation signal. For example, the memory device may receive first to P-th activation signals (P is an integer larger than 1) and first to P-th row addresses R1 to RP at time points t2 to t4, respectively.
The memory device may determine a row address (i.e., the victim row address) that is a target of the refresh FREF at the time point t5. For example, the memory device may determine one of first to P-th row addresses R1 to RP as the attack row address. The memory device may determine the victim row address based on the attack row address. The memory device may determine an address corresponding to at least one row adjacent to a row corresponding to the attack row address as the victim row address.
In an embodiment, the memory device may determine the attack row address when receiving the activation signal. For example, the memory device may determine the attack row address at each of the time points t2 to t4. The memory device may determine the row address received first after performing the refresh FREF as the attack row address. For example, the memory device may determine a first row address R1 at the time point t2 as the attack row address. The memory device may determine one among first and second row addresses R1 and R2 as the attack row address at the time point t3. For example, the memory device may determine whether the attack row address shall be changed to a second row address R2 at the time point t3. The memory device may determine whether the attack row address shall be changed to a P-th row address RP at the time point t4.
The memory device may generate a random number and a reference value at each of the time points t2 to t4. The memory device may compare magnitudes of the random number with the reference value at each of the time points t2 to t4, and determine the attack row address based on the comparison result. For example, the memory device may determine a reference value based on the number of activation signals received after the refresh FREF. The memory device may generate a random number by using a random number generator. In an embodiment, the random number generator may be implemented as a linear feedback shift register. Magnitude comparison of the memory device will be later described with reference to
The memory device may determine the victim row address based on the attack row address the time point t5. The memory device may perform the refresh FREF based on the victim row address.
The memory device may perform the refresh FREF at the time point t5, and then receive a Q-th activation signal and a Q-th row address RQ corresponding to the Q-th activation signal at a time point t6 (Q is an integer larger than P). The memory device may determine the Q-th row address RQ of the time point t6 as the attack row address.
In an embodiment, the memory device may determine the attack row address at the time point t5. The memory device may store all row addresses received within the time interval ITV1. For example, the memory device may store the first to P-th row addresses R1 to RP respectively received at the time points t2 to t4. For example, the memory device may store the first to P-th row addresses R1 to RP to the register. The size of the register may be determined based on a maximum value of the number of row addresses which the memory device may receive within the time interval ITV1 (or the number of activation signals).
The memory device may determine one among the first to P-th row addresses R1 to RP stored in the register at the time point t5 as the attack row address. The memory device may output the attack row address and initialize the register after outputting the attack row address.
The memory device may determine the victim row address based on the attack row address at the time point t5. The memory device may perform the refresh FREF based on the victim row address.
The memory device may perform the refresh FREF at the time point t5, and then receive the Q-th activation signal and the Q-th row address RQ corresponding to the Q-th activation signal at the time point t6. The memory device may store the Q-th row address RQ in the register at the time point t6. Herein, each of the time points t1 and t5 may be referred to as a period of time during which the refresh FREF is performed, or a time point at which the TRR command FREF_EN is received.
Referring to
In an embodiment, the memory device may generate the TRR command FREF_EN at a period of the time interval ITV1, and perform the refresh FREF based on the TRR command FREF_EN. The memory device may generate the TRR command FREF_EN based on a command from a memory controller. For example, the memory controller may transmit the refresh command to the memory device at the time point t1, and the memory device may generate the TRR command FREF_EN from the time point t1 at the period of the time interval ITV1. The memory device may perform the refresh FREF based on the TRR command FREF_EN of the high level.
A memory device according to an embodiment may include an attack row selector configured to select an attack row, an attack row register REG (e.g., 320 of
The counter may operate based on the TRR command FREF_EN and the activation signal. The counter may count the number of activation signals, so as to generate the counting value CNT. For example, the counter may set the counting value CNT as ‘1’ based on the first activation signal at a time point t2. In the same way, the counter may increase the counting value CNT whenever receiving the activation signal at time points t3 to t4. The counter may initialize the counting value CNT based on the TRR command FREF_EN of the high level.
The random number generator may generate the first value VAL1 that is a random number when the activation signal is received. The random number generator may generate ‘76’ upon receiving the activation signal at the time point t2, generate ‘81’ upon receiving the activation signal at the time point t3, and generate ‘2’ upon receiving the activation signal at the time point t4.
The random number generator may set a maximum value of the random number that may be generated. For example, the random number generator may generate an integer in the range of 0 to the maximum value. In an embodiment, the maximum value of the random number may be determined based on a length of the time interval ITV1. For example, when the time interval ITV1 is long, the maximum value of the random number may be relatively large, and when the time interval ITV1 is short, the maximum value of the random number may be relatively small. The memory device may determine the maximum value of the number of activation signals that may be processed within the time interval ITV1. The memory device may set the maximum value of the random number based on the maximum value of the number of activation signals. In an embodiment, the memory device may set the maximum value of the number of activation signals as the maximum value of the random number.
In an embodiment, the random number generator may be implemented as a linear feedback shift register (LFSR). When the random number generator is n-bit LFSR, the maximum value of the random number generator may be 2n−1. The memory device may determine n based on the maximum value of the random number, and implement the n-bit LFSR.
The reference value generator may generate the second value VAL2 based on the counting value CNT. For example, the reference value generator may generate ‘(the maximum value of the random number)/the counting value CNT’ as the second value VAL2. In
The comparator may compare the first value VAL1 with the second value VAL2. The comparator may generate the update signal CUP according to the comparison result. For example, when the first value VAL1 is smaller than (or smaller than or equal to) the second value VAL2, the comparator may generate the update signal CUP of the high level. When the first value VAL1 is greater than or equal to (or greater than) the second value VAL2, the comparator may generate the update signal CUP of the low level. The comparator may compare ‘76’ with ‘100’ at the time point t2, and output ‘1’. The comparator may compare ‘81’ with ‘50’ at the time point t3, and output ‘0’. The comparator may compare ‘2’ with ‘100/P’ at the time point t4 and output ‘1’.
The attack row register REG may receive a row address (R1 to RP and RQ) corresponding to the activation signal. In an embodiment, the attack row register REG may have a queue size of 1 and may store only one row address. The attack row register REG may store a row address based on the update signal CUP. When the row address is stored in the queue, the attack row register REG may replace an existing row address with a newly received row address.
Upon receiving the update signal CUP of the high level, the attack row register REG may store the row address of the time point at which the update signal CUP of the high level is received. Upon receiving the update signal CUP of the low level, the attack row register REG may maintain the existing row address. For example, the attack row register REG may store the row address R1 in response to the update signal CUP of the high level at the time point t2. The attack row register REG may maintain the row address R1 in response to the update signal CUP of the low level at the time point t3. The attack row register REG may store the row address RP in response to the update signal CUP of the high level at the time point t4. For example, the attack row register REG may replace the existing row address with the row address RP at the time point t4.
The attack row register REG may output the attack row address ARA in response to the TRR command FREF_EN of the high level. For example, the attack row register REG may output the row address RP stored in response to the TRR command FREF_EN of the high level at the time point t5 as the attack row address ARA.
In an embodiment, when the attack row address ARA is output at the time point t5, the attack row register REG may initialize the stored row address. In an embodiment, when the attack row address ARA is output at the time point t5, the attack row register REG may maintain the stored row address. The attack row register REG may receive the row address RQ and the update signal CUP at a time point t6. The attack row register REG may store the row address RQ in response to the update signal CUP of the high level at the time point t6. Herein, each of the time points t1 and t5 may be referred to as a period of time during which the refresh FREF is performed, or a time point at which the TRR command FREF_EN is received.
Referring to
In an embodiment, the memory device may generate the TRR command FREF_EN at a period of the time interval ITV1, and perform the refresh FREF based on the TRR command FREF_EN. The memory device may generate the TRR command FREF_EN based on a command from a memory controller. For example, the memory controller may transmit the refresh command to the memory device at the time point t1, and the memory device may generate the TRR command FREF_EN from the time point t1 at the period of the time interval ITV1. The memory device may perform the refresh FREF based on the TRR command FREF_EN of the high level.
A memory device according to an embodiment may include the attack row selector configured to select an attack row, the attack row register REG (e.g., 320 of
The counter may operate based on the TRR command FREF_EN and the activation signal. The counter may count the number of activation signals, so as to generate the counting value CNT. For example, the counter may set the counting value CNT as ‘1’ based on the first activation signal at a time point t2. In the same way, the counter may increase the counting value CNT whenever receiving the activation signal at time points t3 to t4. The counter may initialize the counting value CNT based on the TRR command FREF_EN of the high level.
The random number generator may generate the first value VAL1 that is a random number when the activation signal is received. The random number generator may generate the first value VAL1, which is a real number in the range of 0 to 1. The random number generator may generate ‘ 1/53’ upon receiving the activation signal at the time point t2, generate ‘⅖’ upon receiving the activation signal at the time point t3, and generate ‘ 1/117’ upon receiving the activation signal at the time point t4.
In an embodiment, the random number generator may generate the first value VAL1 based on the maximum value of the number of activation signals. The memory device may determine the maximum value of the number of activation signals that may be processed within the time interval ITV1. The random number generator may set ‘1/(the maximum value of the number of activation signals)’ as a minimum value. For example, the random number generator may generate a random number in the range of ‘1/(the maximum value of the number of activation signals)’ to 1.
The reference value generator may generate the second value VAL2 based on the counting value CNT. For example, the reference value generator may generate ‘1/the counting value CNT’ as the second value VAL2. For example, the reference value generator may generate ‘1’ at the time point t2, generate ‘½’ at the time point t3, and generate ‘1/P’ at the time point t4 (P is an integer larger than 1).
The comparator may compare the first value VAL1 with the second value VAL2. The comparator may generate the update signal CUP according to the comparison result. For example, when the first value VAL1 is smaller than (or smaller than or equal to) the second value VAL2, the comparator may generate the update signal CUP of the high level. When the first value VAL1 is greater than or equal to (or greater than) the second value VAL2, the comparator may generate the update signal CUP of the low level. The comparator may compare ‘ 1/53’ with ‘1’ at the time point t2 and output ‘1’. The comparator may compare ‘⅖’ with ‘½’ at the time point t3 and output ‘1’. The comparator may compare ‘ 1/117’ with ‘1/P’ at the time point t4 and output ‘1’.
The attack row register REG may receive the row address (R1 to RP and RQ) corresponding to the activation signal. In an embodiment, the attack row register REG may have a queue size of 1 and may store only one row address. The attack row register REG may store row address based on the update signal CUP. When the row address is stored in the queue, the attack row register REG may replace an existing row address with a newly received row address.
Upon receiving the update signal CUP of the high level, the attack row register REG may store the row address of the time point at which the update signal CUP of the high level is received. Upon receiving the update signal CUP of the low level, the attack row register REG may maintain the existing row address. For example, the attack row register REG may store the row address R1 in response to the update signal CUP of the high level at the time point t2. The attack row register REG may store the row address R2 in response to the update signal CUP of the high level at the time point t3. The attack row register REG may store the row address RP in response to the update signal CUP of the high level at the time point t4. That is, the attack row register REG may replace the existing row address at the time point t3, and t4.
The attack row register REG may output the attack row address ARA in response to the TRR command FREF_EN of the high level. For example, the attack row register REG may output the row address RP stored in response to the TRR command FREF_EN of the high level at the time point t5 as the attack row address ARA.
In an embodiment, when the attack row address ARA is output at the time point t5, the attack row register REG may initialize the stored row address. In an embodiment, when the attack row address ARA is output at the time point t5, the attack row register REG may maintain the stored row address. The attack row register REG may receive the row address RQ and the update signal CUP at a time point t6. The attack row register REG may store the row address RQ in response to the update signal CUP of the high level at the time point t6. Herein, each of the time points t1 and t5 may be referred to as a period of time during which the refresh FREF is performed, or a time point at which the TRR command FREF_EN is received.
Referring to
The attack row register REG may receive a row address RY at a time point tm. When the first value VAL1 is greater than or equal to (or greater than) the second value VAL2, the attack row register REG may receive the conversion signal of the low level, and maintain the previously stored the row address RZ. When the first value VAL1 is smaller than (or smaller than or equal to) the second value VAL2, the attack row register REG may receive the conversion signal of the high level, and replace the previously stored row address RZ with the row address RY.
The attack row register REG may maintain the row address with a probability PS(m) at the time point tm. The probability PS(m) may be associated with the number of activation signals received from an immediately previous TRR time point to the time point tm. For example, when m activation signals are received until the time point tm, the probability PS(m) may be ‘1−(1/m)’.
The attack row register REG may replace the row address with a probability PU(m) at the time point tm. The probability PU(m) may be associated with the number of activation signals received from the immediately previous TRR time point to the time point tm. For example, when m activation signals are received until the time point tm, the probability PU(m) may be ‘1/m’.
The sum of the probability PS(m) and the probability PU(m) may be 1. For example, the attack row register REG may maintain or replace the row address RZ at the time point tm.
Referring to
The memory device may determine one among the row addresses R1 to RV as the attack row address at the time points t1 to t4, and include an attack row register storing the attack row address. The attack row register may store one row address. Hereinafter, a configuration in which the memory device determines and stores the attack row address will be described by using a trellis analysis technique.
The memory device may receive the row address R1 at the time point t1. The memory device may determine the row address R1 as the attack row address at the time point t1. The memory device may receive the row address R2 at the time point t2. The memory device may maintain the attack row address as the row address R1 with a probability PS(2) at the time point t2. The memory device may replace the attack row address with the row address R2 with a probability PU(2) at the time point t2. At this time, the probability PS(2) and the probability PU(2) may be ½ for both. For example, at the time point t2, the probability P(R1) that the attack row address is the row address R1 may be ½, and the probability P(R2) that the attack row address is the row address R2 may be ½.
The memory device may receive the row address R3 at the time point t3. The memory device may maintain the existing attack row address (e.g., R1 or R2) with a probability PS(3) at the time point t3. The memory device may replace the attack row address with the row address R3 with a probability PU(3) at the time point t3. At this time, the probability PS(3) may be ⅔, and the probability PU(3) may be ⅓. For example, at the time point t3, the probability P(R1) that the attack row address is the row address R1 may be ⅓ (i.e., PS(2)*PS(3)), the probability that the attack row address is the row address R2 may be ⅓ (i.e., PU(2)*PS(3)), and the probability P(R3) that the attack row address is the row address R3 may be ⅓ (i.e., PS(2)*PU(3)+PU(2)*PU(3)).
As such, the memory device may receive a row address RV corresponding to a V-th activation signal at the time point t4. The memory device may maintain the existing the attack row address with a probability PS(V), and may replace the existing attack row address with the row address RV with a probability PU(V). Accordingly, the probability P(R1) to P(RV) that the memory device determines each row address as the attack row address at the time point t4 may be all the same as 1/V.
For example, when the row addresses R1 to RV are all different, the memory device may determine each row addresses R1 to RV as the attack row address based on the same probability at each of the time points t1 to t4. When at least two of the row addresses R1 to RV are the same, the memory device may determine the same address as the attack row address with a relatively high probability. For example, when the row address R1 and the row address R3 are the same, the memory device may determine the row address R1 as the attack row address with a probability of 2/V at the time point t4.
As such, the memory device may always perform the refresh at the refresh time point by determining the received row address as the attack row address even if only one row address is received. In addition, the memory device may provide robust defense performance with respect to various attack patterns by selecting one of the received row addresses with a substantially equivalent probability.
Referring to
The attack row circuit 510 may receive the TRR command FREF_EN, the activation signal ACT and the row address RA. The time point at which the attack row circuit 510 receives the TRR command FREF_EN and the row address RA may vary. For example, the attack row circuit 510 may receive the TRR command FREF_EN at a first time point, and receive the row address RA at a second time point. Depending on the embodiment, the first time point may be earlier or later than the second time point. The row address RA may be an address corresponding to the activation signal.
The attack row circuit 510 may include a plurality of queues 515. The plurality of queues 515 may include first to P-th queues 511 to 513. The attack row circuit 510 may have a queue size of P. The queue size of the attack row circuit 510 may be determined based on the maximum value of the number of activation signals that may be received within the TRR interval. In an embodiment, the queue size may be substantially equivalent to the maximum value of the number of activation signals that may be received within the TRR interval. In an embodiment, the queue size may be larger than the maximum value of the number of activation signals that is received within the TRR interval.
The attack row circuit 510 may respectively store the row addresses R1 to RP in the first to P-th queues 511 to 513.
The attack row circuit 510 may determine the attack row address ARA in response to the TRR command FREF_EN of the first level. For example, upon receiving the TRR command FREF_EN of the first level, the attack row circuit 510 may determine one of the row addresses R1 to RP stored in the first to P-th queues 511 to 513 as the attack row address ARA. The attack row circuit 510 may transfer the attack row address ARA to the victim row determiner 520.
The attack row circuit 510 may perform initialization based on the TRR command FREF_EN of the first level. For example, when the attack row address ARA is transferred to the victim row determiner 520 the attack row circuit 510 may erase the row addresses R1 to RP stored in the first to P-th queues 511 to 513.
The victim row determiner 520 may determine the victim row address VRA based on the attack row address ARA. For example, the victim row determiner 520 may determine an address corresponding to at least one row adjacent to a row corresponding to the attack row address ARA as the victim row address VRA. In an embodiment, the victim row determiner 520 may determine at least one address corresponding to a victim row among rows at ±1 positions based on the attack row address ARA as the victim row address VRA. In an embodiment, the victim row determiner 520 may determine at least one address corresponding to a victim row among rows belonging to a range of ±x (x is an integer larger than 1) based on the attack row address ARA as the victim row address VRA. The victim row determiner 520 may output the victim row address VRA.
Referring to
In an embodiment, the memory device may generate the TRR command FREF_EN at a period of the time interval ITV1, and perform the refresh FREF based on the TRR command FREF_EN. The memory device may generate the TRR command FREF_EN based on a command from a memory controller. For example, the memory controller may transmit the refresh command to the memory device at the time point t1, and the memory device may generate the TRR command FREF_EN from the time point t1 at the period of the time interval ITV1. The memory device may perform the refresh FREF based on the TRR command FREF_EN of the high level.
A memory device according to an embodiment may include an attack row circuit (e.g., 510 of
The attack row register may receive the row address (R1 to RP and RQ) corresponding to the activation signal. In an embodiment, the attack row register may have a queue size of P and may store P row addresses. The queue size may be determined based on the maximum value of the number of activation signals that may be processed within the time interval ITV1. The attack row register may store the row address (R1 to RP and RQ).
The attack row register may include the plurality of queues 515 storing the row address R1 to RP and RQ. The attack row register may store the row addresses R1 to RP respectively received at the time point t1 and time points t2 to t4 in the plurality of queues 515.
The attack row register may output the attack row address ARA in response to the TRR command FREF_EN of the high level. For example, the attack row register may output one (e.g., the row address R2) of the row addresses R1 to RP stored in the plurality of queues 515 as the attack row address ARA, in response to the TRR command FREF_EN of the high level at a time point t5. Herein, each of the time points t1 and t5 may be referred to as a period of time during which the refresh FREF is performed, or a time point at which the TRR command FREF_EN is received.
When the attack row address ARA is output, the attack row register may initialize the plurality of queues 515. The attack row register may store the row address RQ received at a time point t6 in the plurality of queues 515.
Referring to
In an embodiment, the memory device may determine a ratio of the refresh NREF and the refresh FREF. For example, the memory device may determine the refresh ratio between the refresh FREF and the refresh NREF to be 1:1. The memory device may perform the refresh FREF or the refresh NREF at a period of a time interval REFI. The time interval REFI may correspond to a maximum average refresh interval tREFI of Joint Electron Device Engineering Council (JEDEC) standard. The memory device may perform the refresh FREF at a period of a time interval ITV2. The time interval ITV2 may be determined based on the time interval REFI and refresh ratio. For example, when the refresh ratio between the refresh FREF and the refresh NREF is 1:a (a is an integer greater than or equal to 1), the time interval ITV2 may be larger than ‘(the time interval REFI)×a+1’. In the example of
The memory device may perform the refresh FREF at the time point t1, and then receive an activation signal and a row address corresponding to the activation signal. For example, the memory device may receive first and second activation signals and the first and second row addresses R1 and R2 at time points t2 and t3.
The memory device may perform the refresh NREF at the time point t4. For example, the memory device may perform the refresh NREF based on the row address NRA generated from the normal refresh control circuit 292 of
The memory device may perform the refresh NREF at the time point t4, and then receive an activation signal and a row address corresponding to the activation signal. For example, the memory device may receive third to fifth activation signals and third to fifth row addresses R3 to R5 at time points t5 to t7.
The memory device may determine a row address (i.e., the victim row address) that is a target of the refresh FREF at a time point t8. For example, the memory device may determine one of the activation row addresses R1 to R5 received from an immediately previous refresh FREF to a current refresh FREF (i.e., in a period within the time interval ITV2) as the attack row address. The memory device may determine the victim row address based on the attack row address. The memory device may determine an address corresponding to at least one row adjacent to a row corresponding to the attack row address as the victim row address.
In an embodiment, the memory device may determine the attack row address when receiving the activation signal. For example, the memory device may determine the attack row address at each of the time points t2, t3, and t5-t7. The memory device may determine the row address received first after the refresh FREF as the attack row address. The memory device may determine the first row address R1 at the time point t2 as the attack row address. The memory device may determine one among the first and second row addresses R1 and R2 as the attack row address at the time point t3. For example, the memory device may determine whether the attack row address shall be changed to the second row address R2 at the time point t3. In the same way, the memory device may determine whether the attack row address shall be changed to the row addresses R3 to R5 at each of the time points t5 to t7.
The memory device may generate a random number and a reference value at each of the time points t2, t3, and t5-t7. The memory device may generate a random number based on the time interval ITV2. For example, the memory device may determine the maximum value of the number of activation signals that may be received in an operation range within the time interval ITV2 excluding the refresh NREF (i.e., ‘(the time interval REFI)×2’). In an embodiment, the memory device may determine a maximum value based on a count of the refresh NREF within the time interval ITV2. For example, when the count of the refresh NREF within the time interval ITV2 is e (e is an integer larger than 1), the memory device may determine the maximum value of the number of activation signals based on ‘(the time interval REFI)×(e+1)’.
The memory device may determine a minimum value or maximum value of a random number based on the maximum value of the number of activation signals. Regarding the configuration in which the memory device determines the minimum value or maximum value of the random number, the contents described with reference to
The memory device may compare magnitudes of the random number with the reference value at each of the time points t2, t3, and t5-t7, and determine the attack row address based on the comparison result. For example, the memory device may determine the reference value based on the number of activation signals received after the refresh FREF. The memory device may generate a random number by using the random number generator. In an embodiment, the random number generator may be implemented as a linear feedback shift register. Regarding the magnitude comparison of the memory device, the contents described with reference to
The memory device may determine the victim row address based on the attack row address at the time point t8. The memory device may perform the refresh FREF based on the victim row address.
The memory device may perform the refresh FREF at the time point t8, and then receive a sixth activation signal and the sixth row address R6 corresponding to the sixth activation signal at a time point t9. The memory device may determine the sixth row address R6 of the time point t9 as the attack row address.
In an embodiment, the memory device may determine the attack row address at the time point t8. The memory device may store all row addresses received within the time interval ITV2. For example, the memory device may store the first to fifth row addresses R1 to R5 received at the time points t2, t3, and t5-t7, respectively. For example, the memory device may store the first to fifth row addresses R1 to R5 to the register. The size of the register may be determined based on a maximum value of the number of row addresses which the memory device may receive within the time interval ITV2 (or the number of activation signals).
The memory device may determine one of the first to fifth row addresses R1 to R5 stored in the register at the time point t8 as the attack row address. The memory device may output the attack row address and initialize the register.
The memory device may determine the victim row address based on the attack row address at the time point t8. The memory device may perform the refresh FREF based on the victim row address.
The memory device may perform the refresh FREF at the time point t8, and then receive the sixth activation signal and the sixth row address R6 corresponding to the sixth activation signal at the time point t9. The memory device may store the sixth row address R6 in the register at the time point t9. Herein, each of the time points t1 and t8 may be referred to as a period of time during which the refresh FREF is performed, or a time point at which the TRR command FREF_EN is received.
Referring to
In an embodiment, the memory device may determine a ratio of the refresh FREF and the refresh NREF. For example, the memory device may determine a refresh ratio between the refresh FREF and the refresh NREF to be 1:2. The memory device may perform the refresh FREF or the refresh NREF at a period of the time interval REFI. The time interval REFI may correspond to the maximum average refresh interval tREFI of the JEDEC standard. The memory device may perform the refresh FREF at a period of a time interval ITV3. The time interval ITV3 may be determined based on the time interval REFI and refresh ratio. For example, when the refresh ratio between the refresh FREF and the refresh NREF is 1:a (a is an integer greater than or equal to 1), the time interval ITV3 may be larger than ‘(the time interval REFI)×(a+1)’. In the example of
The memory device may perform the refresh FREF at the time point t1, and then receive an activation signal and a row address corresponding to the activation signal. For example, the memory device may receive first and second activation signals and the first and second row addresses R1 and R2 at time points t2 and t3.
The memory device may perform the refresh NREF at the time points t4 and t8. For example, the memory device may perform the refresh NREF based on the row address NRA generated from the normal refresh control circuit 292 of
The memory device may perform the refresh NREF at the time points t4 and t8, and then receive an activation signal and a row address corresponding to the activation signal. Herein, each of the time points t4 and t8 may be referred to as a period of time during which the refresh NREF is performed, or a time point at which the normal refresh command is received. For example, the memory device may receive the third to the sixth activation signals and the third to sixth row addresses R3 to R6 at time points t5 to t7 and t9.
The memory device may determine a row address (i.e., the victim row address) that is a target of the refresh FREF at a time point t10. For example, the memory device may determine one of the activation row addresses R1 to R6 received from the immediately previous refresh FREF to the current refresh FREF (i.e., in a period within the time interval ITV3) as the attack row address. The memory device may determine the victim row address based on the attack row address. The memory device may determine an address corresponding to at least one row adjacent to a row corresponding to the attack row address as the victim row address.
In an embodiment, the memory device may determine the attack row address when receiving the activation signal. For example, the memory device may determine the attack row address at each of the time points t2, t3, t5-t7, and t9. The memory device may determine the row address received first after the refresh FREF as the attack row address. The memory device may determine the first row address R1 at the time point t2 as the attack row address. The memory device may determine one among the first and second row addresses R1 and R2 as the attack row address at the time point t3. For example, the memory device may determine whether the attack row address shall be changed to the second row address R2 at the time point t3. In the same way, the memory device may determine whether the attack row address shall be changed to the row address R3 to R6 at each of the time points t5 to t7, and t9.
The memory device may generate a random number and a reference value at each of the time points t2, t3, t5-t7, and t9. The memory device may generate a random number based on the time interval ITV3. For example, the memory device may determine the maximum value of the number of activation signals that may be received in an operation range within the time interval ITV3 excluding the refresh NREF (i.e., ‘(the time interval REFI)×3’).
In an embodiment, the memory device may determine a maximum value based on count of the refresh NREF within the time interval ITV3. For example, when the count of the refresh NREF within the time interval ITV3 is e (e is an integer larger than 1), the memory device may determine a maximum value based on ‘(the time interval REFI×(e+1)’.
The memory device may determine a minimum value or maximum value of a random number based on the maximum value of the number of activation signals. Regarding the configuration in which the memory device determines the minimum value or maximum value of the random number, the contents described with reference to
The memory device may compare magnitudes of the random number with the reference value at each of the time points t2, t3, t5-t7, and t9, and determine the attack row address based on the comparison result. For example, the memory device may determine a reference value based on the number of activation signals received after the refresh FREF. The memory device may generate a random number by using the random number generator. In an embodiment, the random number generator may be implemented as a linear feedback shift register. Regarding magnitude comparison of the memory device, the contents described with reference to
The memory device may determine the victim row address based on the attack row address at the time point t10. The memory device may perform the refresh FREF based on the victim row address.
The memory device may perform the refresh FREF at the time point t10, and then receive a seventh activation signal and a seventh row address R7 corresponding to the seventh activation signal at a time point t11. The memory device may determine the seventh row address R7 at the time point t11 as the attack row address.
In an embodiment, the memory device may determine the attack row address at the time point t10. The memory device may store all row addresses received within the time interval ITV3. For example, the memory device may store first to sixth row addresses R1 to R6 received at the time points t2, t3, t5-t7, and t9, respectively. For example, the memory device may store first to sixth row addresses R1 to R6 to the register. The size of the register may be determined based on a maximum value of the number of row addresses which the memory device may receive within the time interval ITV3 (or the number of activation signals).
The memory device may determine one among first to sixth row addresses R1 to R6 stored in the register at the time point t10 as the attack row address. The memory device may output the attack row address and initialize the register.
The memory device may determine the victim row address based on the attack row address at the time point t10. The memory device may perform the refresh FREF based on the victim row address.
The memory device may perform the refresh FREF at the time point t10, and then receive a seventh activation signal and a seventh row address R7 corresponding to the seventh activation signal at the time point t11. The memory device may store the seventh row address R7 in the register at the time point t11. Herein, each of the time points t1 and t10 may be referred to as a period of time during which the refresh FREF is performed, or a time point at which the TRR command FREF_EN is received.
Referring to
At this time, a wordline WLt among the wordlines WLt−1, WLt, and WLt+1 may correspond to the attack row address ARA that is intensively accessed. Being intensively accessed means that an activation (active) count of the wordline is large or an activation frequency is high. When a hammer wordline WLt is accessed and activated and pre-charged, that is, when the voltage of the hammer wordline WLt increased and decreased, due to coupling phenomenon occurring between adjacent wordlines WLt−1 and WLt+1, the voltages of the adjacent wordlines WLt−1 and WLt+1 also increase and decrease, such that the cell charge charged in the memory cells MC connected to the adjacent wordlines WLt−1 and WLt+1 is affected. As the hammer wordline WLt is accessed more frequently, the possibility that cell charges of the memory cells MC connected to victim wordlines WLt−1 and WLt+1 are lost and the stored data is damage may be increased.
The victim row determiner 330 of
Referring to
The victim row determiner 330 of
Referring to
At step S1810, the memory device may receive a first activation signal and a first activation row address corresponding to the first activation signal at a first time point. The memory device may calculate the number of activation row addresses (or activation signals) received from a time point at which the immediately previous TRR signal is received to the first time point. For example, the number of activation row addresses (or activation signals) may be calculated from a time point of receiving the TRR signal to the first time point. For example, the number of activation row addresses (or activation signals) may be calculated until the first time point after the previous TRR is performed.
At step S1820, upon receiving the first activation signal, memory device may generate the random number. In an embodiment, the maximum value of the random number may be determined based on an interval between two consecutive TRRs. For example, the memory device may determine the maximum value of the number of activation signals that may be received during the interval between the TRR. The memory device may set the maximum value of the random number to be substantially equivalent to the maximum value of the number of activation signals. The memory device may generate a random number by using a linear feedback shift register (LFSR). For example, if the random number generator includes n-bit LFSR, the maximum value of the random number generator may be 2n−1. In an embodiment, the memory device may generate a random number that is a real number in a range of 0 to 1.
At step S1830, the memory device may generate a reference value based on the number of activation signals received from the immediately previous TRR time point to the first time point. In an embodiment, the memory device may generate ‘(the maximum value of the number of activation signals)/(the number of activation signals)’ as a reference value. In an embodiment, the memory device may generate ‘1/(the number of activation signals)’ as a reference value.
At step S1840, the memory device may determine the attack row address based on a magnitude relationship between the random number and the reference value. For example, when the random number is smaller than (or smaller than or equal to) the reference value, the memory device may determine the first activation row address as the attack row address. When the random number is greater than (or greater than or equal to) the reference value, the memory device may maintain the existing attack row address.
At step S1850, the memory device may determine the victim row address based on the attack row address. The memory device may determine an address corresponding to a row (e.g., victim row) adjacent to a row (e.g., attack row) corresponding to the attack row address as the victim row address.
Referring to
The processor 1910 controls the overall operation of each component of the computing system 1900. The processor 1910 may be implemented as at least one of various processing units such as a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), and the like.
The memory 1920 stores various data and commands. The memory controller 1930 controls the transfer of data or commands to and from memory 1920. The memory 1920 and/or the memory controller 1930 may perform the refresh operation described with reference to
The storage device 1940 non-temporarily stores programs and data. In an embodiment, the storage device 1940 may be implemented as a non-volatile memory. The communication interface 1950 supports wired and wireless Internet communication of the computing system 1900. In addition, the communication interface 1950 may support various communication methods other than Internet communication. The bus 1960 provides a communication function between components of the computing system 1900. The bus 1960 may include at least one type of bus according to a communication protocol between components.
Referring to
The memory chips DRAM may transmit and receive data signals and data strobe signals through corresponding data transmission lines connected to the corresponding data buffers DB. Each of the memory chips DRAM may be connected to the data buffer DB through corresponding data transmission lines, and transmit and receive parity data and the data strobe signals DQS.
The memory module 2000 may further include a programmable read-only memory (EEPROM) (not shown). The EEPROM may include initial information or device information of the memory module 2000. For example, the EEPROM may include initial information or device information such as module type, module configuration, storage capacity, module type, execution environment, etc. of the memory module 2000. When the memory system including the memory module 2000 is booted, the memory controller may read device information from the EEPROM and recognize the memory module based on the read device information.
The memory module 2000 may include a plurality of ranks. In an embodiment, each rank may include eight bank groups. Each bank group may include four banks.
The memory module 2000 may perform the refresh operation described with reference to
Referring to
The stack semiconductor chip 3300 may include at least one memory chip 3320 stacked on a buffer chip 3310 such as a logic chip. The buffer chip 3310 and at least one memory chip 3320 may be connected to each other through a through substrate via (e.g., a through silicon via (TSV)). The buffer chip 3310 may perform a training operation on the memory chip 3320. For example, the stack semiconductor chip 3300 may be a high bandwidth memory (HBM) of 500 GB/sec to 1 TB/sec or more.
The at least one memory chip 3320 may perform the refresh operation described with reference to
In some embodiments, each component or combinations of two or more components described with reference to
While this disclosure has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the present invention as set forth in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0154767 | Nov 2023 | KR | national |
