Patent Grant
8627190
The present application claims the priority based on Japanese Patent Application No. 2009-088593 filed on Apr. 1, 2009, the disclosure of which is hereby incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to a memory device, to a circuit board, to a liquid receptacle, to a method of controlling a nonvolatile data memory section, and to a system including a memory device detachably connectable to a host circuit.
2. Description of the Related Art
An inkjet printer, which is one example of a liquid ejecting device, typically has one or more installed ink receptacles or ink containers which are detachable liquid receptacles. Some ink receptacles are provided with memory devices. The memory device stores information of various kinds, for example, the remaining ink level or the color of the ink in the ink receptacle. A control unit provided to the printer communicates with the memory device of the ink receptacle.
JP-A 2002-370383
JP-A 2004-299405
JP-A 2001-146030
JP-A 6-226989
JP-A 2003-112431
However, in conventional techniques, insufficient consideration is given to the issue of reduction of defects in a data memory section of a memory device. For example, when one of the memory cells in the data memory section, there is a possibility that the system including the printer and the ink receptacles does not operate properly. As a result, the yield rate of the memory device production is deteriorated. This issue is not limited to memory devices provided to ink receptacles, but is rather an issue common to all manner of memory devices that electrically connect to a host circuit.
An object of the present invention is to provide a technology for reducing failures with respect to memory devices that are electrically connected to a host circuit.
The present invention is addressed to attaining the above objects at least in part according to the following aspects or modes of the present invention.
A first aspect of the present invention is directed to memory device electrically connectable to a host circuit. The memory device includes a nonvolatile data memory section including a first memory area and a second memory area related to the first memory area; a data reception section that receives, from the host circuit, data including a first actual data to be written into the first memory area; a parity acquisition section that acquires first parity data associated with the first actual data; a data copy section that generates second actual data that is a copy of the first actual data, and second parity that is a copy of the first parity data; a read/write control section that writes the first actual data and the first parity data into the first memory area, and writes the second actual data and the second parity data into the second memory area; and a data transmission section that reads the first actual data, the first parity data, the second actual data, and the second parity data from the data memory section for transmission to the host circuit.
With this arrangement, even if the first actual data includes faulty data changes due to errors in the data memory section, the host circuit is able to detect the faulty data changes using the first parity data, and to continue normal operation using the second actual data. Accordingly, even if the data memory device includes some errors, the memory device may be deemed sufficiently good, thereby reducing failures with respect to memory devices. In a second aspect of the present invention, the read/write control section writes the first actual data and the first parity data into the first memory area if no defect is detected at least in the first memory area, and the read/write control section writes the second actual data and the second parity data into the second memory area if no defect is detected at least in the second memory area.
In a third aspect of the present invention, the first memory area has a first actual data area for writing of the first actual data, and a first parity area for writing of the first parity data, the read/write control section includes a first detection section that detects defects in the first memory area by determining consistency between actual data previously stored in the first actual data area and parity data previously stored in the first parity area, and the read/write control section writes the first actual data area and the first parity data into the first memory area only when no defect is detected in the first memory area. With this arrangement, it is possible to reducing possibility of writing to a memory area having faults.
In a fourth aspect of the present invention, if a defect is detected in the first memory area, the read/write control section writes again to the first memory area the data that is previously stored in the first memory area, in place of the first actual data and the first parity data. With this arrangement, it is possible to maintain the data contents in the defective memory area and prevent further data changes.
In a fifth aspect of the present invention, the second memory area has a second actual data area for writing of the second actual data, and a second parity area for writing of the second parity data, the read/write control section includes a second detection section that detects defects in the second memory area by determining consistency between actual data previously stored in the second actual data area and parity data previously stored in the second parity area, and the read/write control section writes the second actual data area and the second parity data into the second memory area only when no defect is detected in the second memory area. This arrangement further reduces the possibility of writing data into a defective memory area.
In a sixth aspect of the present invention, if a defect is detected in the second memory area, the read/write control section writes again to the second memory area the data that is previously stored in the second memory area, in place of the second actual data and the second parity data. With this arrangement, it is possible to maintain the data contents in the defective memory area and prevent further data changes.
In a seventh aspect of the present invention, the parity acquisition section acquires the first parity data by receiving the first parity data from the host circuit. With this arrangement, the configuration of the memory device is simplified because the parity data is generated by the host circuit.
In an eighth aspect of the present invention, the parity acquisition section acquires the first parity data by generating the first parity data from the first actual data. With this arrangement, the configuration of the host circuit is simplified because the parity data is generated by the host memory device.
It is possible for the present invention to be embodied in various modes, for example, a circuit board detachably and electrically connectable to a liquid ejecting device; a liquid receptacle detachably installable in a liquid ejecting device; a method of controlling a nonvolatile data memory section; a system that includes a host circuit and a memory device detachably installable in the host circuit; a computer program for accomplishing the functions of such methods or devices; or a recording medium having such a computer program recorded thereon.
A. Embodiment
Configuration of Printing System
The printer 20 is furnished with a sub-scanning feed mechanism, a main scanning feed mechanism, a head driving mechanism, and a main controller 40. The sub-scanning feed mechanism has a paper feed motor 22 and a platen 26, and conveys paper PA in the sub-scanning direction by transmitting rotation of the paper feed motor to the platen. The main scanning feed mechanism includes a carriage motor 32, a pulley 38, a drive belt 36 stretched between the carriage motor and the pulley, and a slide rail 34 disposed parallel to the axis of the platen 26. The slide rail 34 slidably retains a carriage 30 that is affixed to the drive belt 36. Rotation of the carriage motor 32 is transmitted to the carriage 30 via the drive belt 36, whereupon the carriage 30 undergoes reciprocating movement in the axial direction of the platen 26 (the main scanning direction) along the slide rail 34. The head driving mechanism includes a print head unit 60 installed on the carriage 30, and is designed to drive a print head and eject ink onto the paper PA. The main controller 40 controls the above mechanisms and carries out printing operations. The main controller 40 for example receives a print job from a user via the computer 90, and control the above mechanisms to carry out printing based on the content of the received print job. As will be discussed later, a plurality of ink cartridges are detachably installable in the print head unit 60. Specifically, ink cartridges for supplying ink to the print head are disposed in the print head unit 60 in such a way as to be attachable and detachable through user operation. The printer 20 also has a console portion 70 allowing the use to perform various printer settings, check printer status, and so on.
The configuration of the printer, together with the configuration of an ink cartridge (liquid receptacle), will be discussed further with reference to
The ink cartridge 100 has a main body 101 for containing the ink, a circuit board 120, and a sensor 110. On the base face of the main body 101 there is provided an ink delivery port 104 that, with the cartridge installed in the print head unit 60, delivers ink to the print head unit 60. An ink chamber 150 for containing the ink is formed in the main body 101. The ink delivery port 104 communicates with the ink chamber 150. The opening 104op of the ink delivery port 104 is sealed by a film 104f. By installing the ink cartridge 100 on the print head unit 60 (
The sensor 110 is secured to the inside of the main body 101. As will be discussed later, the sensor 110 includes a piezoelectric element composed of a piezoelectric body sandwiched between two opposed electrodes, and is used for detecting the remaining ink level. The main body 101 includes a front wall 101wf (wall lying in the −Y direction) and a base wall 101wb (wall lying in the +Z direction). The front wall 101wf intersects (in the present embodiment, at a substantially right angle) the base wall 101wb. The circuit board 120 is secured to the front wall 101wf. The outside surface of the circuit board 120 is provided with terminals 210 to 270.
Two projections P1, P2 are formed on the front wall 101wf. These projections P1, P2 project out in the −Y direction. A hole 122 and a notch 121 adapted to respectively receive these projections P1, P2 are formed in the circuit board 120 (
Additionally, a mating projection 101e is provided in the front wall 101wf. The ink cartridge 100 is prevented from inadvertently detaching from the holder 4 through mating of the mating projection 101e and a mating aperture 4e of a holder 4 (
The configuration of the print head unit 60, as well as installation of the ink cartridge 100 in the print head unit 60, is discussed with reference to
The ink cartridge 100 is installed in the holder 4 by inserting it in the Z-axis forward direction (the insertion direction R) in
The description of the circuit board 120 continues, returning to
The terminals on the front side of the circuit board 120 are formed with generally rectangular shape and placed so as to form two rows approximately orthogonal to the insertion direction R. Of these two rows, the row situated towards the insertion direction R (the distal edge side in the insertion direction when inserted), i.e. to the lower side in
The terminals which are arrayed to form the upper row are, in order from the left in
With this circuit board 120, the five terminals that are connected to the memory device 130 and the two terminals that are connected to the sensor 110 are situated in proximity to one another. Thus, in the connection mechanism 400 on the printer 20 side as well, the connection terminals 410, 420 and 440 to 460 that correspond to the five terminals connected to the memory device 130 and the connection terminals 430, 470 that correspond to the two terminals connected to the sensor 110 are likewise situated in proximity to one another.
With the ink cartridge 100 secured in the holder 4, the terminals of the circuit board 120 are electrically connected through contact with the connection terminals 410 to 470 of the connection mechanism 400. Additionally, the connection terminals 410 to 470 of the connection mechanism 400 are electrically connected through contact with the terminal group on the sub-control board 500; and the terminal group on the sub-control board 500 are in electrical connection with sub-controller (carriage circuit 50). Thus, when the ink cartridge 100 is secured in the holder 4, the terminals 210 to 270 of the circuit board 120 are in electrical connection with the sub-controller 50.
Electrical Configuration of Printer:
The memory device 130 of each ink cartridge 100 is assigned an 8-bit ID number (identification information) different from all the others. Because as shown in
The lines that electrically connect the sub-controller 50 with each ink cartridge 100 include the lines connecting the sub-controller 50 with the terminal group of the sub-control board 500; the connection terminals 410 to 470 of the connection mechanism 400; the terminal group on the front side of the circuit board 120; and the lines leading from the terminal group of the circuit board 120 to the memory device 130 and to the sensor 110. The lines that electrically connect the sub-controller 50 with each ink cartridge 100 include a reset signal line LR1, a clock signal line LC1, a data signal line LD1, a first ground line LCS, a first power line LCV, a first sensor drive signal line LDSN, and a second sensor drive signal line LDSP.
The reset signal line LR1 between the sub-controller 50 and the memory device 130 is a conductive line for sending a reset signal CRST from the sub-controller 50 to the memory device 130. The reset signal is a signal by which the sub-controller 50 may place the memory control circuit 136 (discussed later) of a memory device 130 in the initialized state, or in a standby state in which it can accept access. When a low level reset signal is presented to a memory control circuit 136 by the sub-controller 50, the memory control circuit 136 goes into the initialized state. The clock signal line LC1 between the sub-controller 50 and the memory device 130 is a conductive line for sending a clock signal CSCK from the sub-controller 50 to the memory device 130. The data signal line LD1 between the sub-controller 50 and the memory device 130 is a conductive line for sending data signals CSDA that are exchanged between the sub-controller 50 to the memory device 130. As shown in
The first ground line LCS is a conductive line for providing ground potential CVSS to the memory device 130, and is electrically connected to the memory device 130 via the ground terminal 210 of the circuit board 120. The first ground line LCS is a line having a single terminus at the sub-controller 50, and branched termini, corresponding in number to the number of ink cartridges 100, at the ink cartridge 100. The ground potential CVSS is connected to ground potential VSS (=CVSS potential) supplied to the sub-controller 50 by the main controller 40 via a second ground line LS, and is set to low level (0 V).
The first sensor drive signal line LDSN and the second sensor drive signal line LDSP are conductive lines adapted to apply a driving voltage to the piezoelectric element of the sensor 110, and after ceasing to apply the driving voltage, transmitting to the sub-controller 50 a voltage produced by the piezoelectric effect of the piezoelectric element. The first sensor drive signal line LDSN and the second sensor drive signal line LDSP are a plurality of lines that respectively are provided independently for each ink cartridge 100, and each of which is electrically connected at a first end to the sub-controller 50 as well as electrically connected at the other end to the first sensor drive terminal 230 and the second sensor drive terminal 270 of the circuit board 120, respectively. The first sensor drive signal line LDSN is electrically connected via the first sensor drive terminal 230 to one of the electrodes of the piezoelectric element of the sensor 110, while the second sensor drive signal line LDSP is electrically connected via the second sensor drive terminal 270 to the other electrode of the piezoelectric element of the sensor 110.
The first power line LCV is a conductive line for providing the power supply voltage CVDD, which represents the operating voltage of the memory device 130, to the memory device 130; and is connected to the memory device 130 via the power supply terminal 220 of the circuit board 120. The first power line LCV is a line having a single terminus at the sub-controller 50, and branched termini, corresponding in number to the number of ink cartridges 100, at the ink cartridge 100. The high level power supply voltage CVDD used to drive the memory device 130 uses potential of about 3.3 V versus the low level ground potential CVSS (0 V). Of course, depending on factors such as the generation of processor of the memory device 130, the potential level of the power supply voltage CVDD may be a different potential, such as 1.5 or 2.0 V for example.
The main controller 40 and the sub-controller 50 are electrically connected by several lines. These several lines include a bus BS, a second power supply line LV, a second ground line LS, and a third sensor drive signal line LDS. The bus BS is used for data communications between the main controller 40 and the sub-controller 50. The second power supply line LV and the second ground line LS are conductive lines for providing the main controller 40 and the sub-controller 50 with power supply voltage VDD and ground potential VSS respectively. The power supply voltage VDD uses potential of the same level as the power supply voltage CVDD provided to the memory device 130 mentioned previously, for example, of about 3.3 V versus the ground potential VSS and CVSS (0 V). Of course, depending on factors such as the generation of processor of the logic IC section of the sub-controller 50, the potential level of the power supply voltage VDD may be a different potential, such as 1.5 or 2.0 V for example. The third sensor drive signal line LDS is a conductive line for providing a sensor drive signal DS (described later) which is ultimately applied to each sensor 110, from the main controller 40 to the sub-controller 50.
The main controller 40 is provided with a control circuit 48, a drive signal generating circuit 42, and ROM, RAM, EEPROM or the like (not shown). Various programs for controlling the printer 20 are stored in the ROM.
The control circuit 48 is a CPU (central processing unit), and performs control of the printer 20 as a whole in concert with the ROM, RAM, EEPROM or other memory. The control circuit 48 is provided with the function blocks of a remaining ink level detection module M1, a memory access module M2, and a ink consumption estimation module M3.
The remaining ink level detection module M1 controls the sub-controller 50 and the drive signal generating circuit 42, drives the sensor 110 of the ink cartridge 100, and decides whether the ink in the ink cartridge 100 equals a prescribed value or greater. Through the sub-controller 50, the memory access module M2 accesses the memory device 130 of the ink cartridge 100 and either reads out the information stored in the memory device 130, or updates the information stored in the memory device 130. The ink consumption estimation module M3 is designed to count the dots that are jetted onto the printer paper in association with conditions of printing operations of the printer 20; and from this count value and the amount of ink consumed by each dot, estimates the amount of ink consumed by printing operations. The amount of ink consumed in head cleaning operations is estimated as well. On the basis of these estimates, a count is kept of the cumulative estimated value for ink consumption consumed from the ink cartridge since the ink cartridge 100 was first installed in the printer 20.
The EEPROM of the main controller 40 stores data representing a sensor drive signal DS for driving the sensor. In accordance with an instruction from the remaining ink level detection module M1 of the control circuit 48, the drive signal generating circuit 42 reads out from the EEPROM data that represents a waveform for the sensor drive signal DS, and generates a sensor drive signal DS having the desired waveform. The sensor drive signal DS includes a potential that is greater than the power supply voltage CVDD (in the present embodiment, 3.3 V); in the present embodiment for example, it includes a maximum potential of about 36 V. Specifically, the sensor drive signal DS is a trapezoidal pulse signal having maximum voltage of 36 V.
In the present embodiment, the drive signal generating circuit 42 can additionally generate a head drive signal for presentation to the print head 5. Specifically, in the present embodiment, during determination of the remaining ink amount, the control circuit 48 prompts the drive signal generating circuit 42 to generate a sensor drive signal, and during printing operations it prompts the drive signal generating circuit 42 to generate a head drive signal.
In terms of hardware configuration, the sub-controller 50 is provided with an ASIC (Application Specific IC). The ASIC has a communication process module 55 and a sensor process module 52 by way of functional features.
The communication process module 55 carries out communication processes with the memory device 130 of each of the ink cartridges 100 via the reset signal line LR1, the data signal line LD1, and the clock signal line LC1. The communication process module 55 also carries out communication processes with main controller 40 through the agency of the bus BS. By detecting the potentials on prescribed terminals of the terminal group of the circuit board 120, the communication process module 55 is able to detect whether the circuit board 120 of an ink cartridge 100 is electrically connected to the printer 20, that is, whether the ink cartridge 100 is installed in the printer 20. The communication process module 55 then notifies the main controller 40 that it has detected the installed ink cartridges 100. Through this process the main controller 40 is able to determine whether the ink cartridges 100 are mounted in the cartridge mounting section.
If the main controller 40 determines that the circuit boards 120 are electrically connected and that the ink cartridges 100 are installed in the printer 20, it then accesses the memory devices 130 of the installed ink cartridges 100 at prescribed timing, via the communication process module 55.
The communication process module 55 is a circuit that includes a logic circuit composed of an ASIC or the like, and that is driven by the power supply voltage VDD (in the present embodiment, 3.3 V). In the present embodiment the ASIC is composed of a memory cell area block (SRAM 551) and a logic area, with the logic area being provided with a sensor register 552 and an error code register 553. The SRAM 551 is a memory used to temporarily save data during operations of the communication process module 55, i.e. to temporarily save data received from the main controller 40, or data received from the sensors 110 or the memory devices 130, for example. After the printer 20 is powered on, in the SRAM 551 there is allocated memory space sufficient to store data corresponding to the original data and corresponding to inverted mirror data of the original data in the memory device 130 of each ink cartridge 100 (discussed later); and the data that is read out from the memory devices is then stored in this allocated memory space. Specifically, in the memory space in the SRAM 551 there is allocated a memory area sufficient to store the 16-bit original data and the inverted mirror data of the 16-bit original data, in the same number of rows as the memory cell array of each memory device 130. Then, the original data which is read out from the memory array of each memory device, together with the inverted mirror data thereof, is stored in the allocated memory area. The values which are read out to the memory area are subsequently updated in association with printing operations (in association with transmission of write data from the main controller 40 and reading of data from the memory devices). Communication errors and memory cell errors, discussed later, occurring in relation to rows in the rewritable memory area of each memory device 130 are written into the error code register 553.
The sensor register 552 is a register used by the sensor process module 52 to write process outcomes of sensor processes. A sensor process module 552 is provided for each ink cartridge, and is used to record results of determination of remaining ink level, discussed later.
The sensor process module 52 executes a remaining ink level determination process using the sensor (sensor process), discussed later. The sensor process module 52 includes a changeover switch. The changeover switch is used to present a sensor drive signal DS supplied by the drive signal generating circuit 42, to the sensor 110 of a single ink cartridge 100 that is targeted for the sensor process, doing so via either the first sensor drive signal line LDSN or the second sensor drive signal line LDSP.
Next, the electrical configuration of the ink cartridges 100 is described. Each ink cartridge 100 has as its electrical elements a memory device 130 and a sensor 110.
The memory device 130 is not designed to accept external input of address data that specifies the address of an access location. The memory device 130 does not accept direct input of address data; however, it is controllable in order to specify memory cells to be accessed, in response to an externally supplied clock signal and command data. The memory device 130 includes a ferroelectric memory cell array 132 provided as the data memory section; and a memory control circuit 136. As indicated by white circles on the broken lines that represent the memory device 130 in
The ferroelectric memory cell array 132 is a nonvolatile semiconductor memory cell array that uses ferroelectric memory elements, and provides a memory area having a data-rewritable feature.
The memory control circuit 136 is designed to control read and write operations to the ferroelectric memory cell array 132 in response to the command data from the sub-controller 50. The memory control circuit 136 analyses identification data and command data sent from the sub-controller 50. Also, during a write operation, on the basis of write content data received from the sub-controller 50 the memory control circuit 136 generates write data and write it to the ferroelectric memory cell array 132. Or, during a read operation, on the basis of read data from the ferroelectric memory cell array 132 the memory control circuit 136 generates data for transmission to the sub-controller 50. This will be discussed in detail later.
The memory control circuit 136 is furnished with an ID comparator module M11, a command parse module M12, an address counter M13, a read/write control module M14, a data send/receive module M15, a counter control module M16, a copy data generation module M17, an inverted data generation module M18, and a data determination module M19. The ID comparator module M11 is designed to compare ID data that is supplied from the sub-controller 50, and the ID number that is assigned to its own memory device; and to then decide whether the target of access is the memory device itself. The ID number of the memory device is stored in the memory cells that are connected to the word line which is selected on the basis of the output of the address counter M13 when access from the sub-controller 50 is initiated subsequent to initialization of the memory device 130. This ID number is used to distinguish a memory device 130 targeted for access by the sub-controller 50, from among the several memory devices 130 which are bus-connected to the sub-controller 50. This ID number may be chosen according to the color of the ink contained in the ink cartridge 100, for example. The command parse module M12 is designed to parse Start of Frame data (SOF), End of Frame (EOF) data, and command data sent from the sub-controller 50, and to decide the start of access and end of access from the sub-controller 50, as well as the type of access (read, write, etc.). When a low level reset signal CRST is input to the memory device 130 so that the memory device 130 is initialized, the address counter M13 resets the counter value. During reset the counter value is set to a value that selects the word line including the memory cells in which the ID number is stored. Subsequently, on the basis of control from the counter control module M16, a prescribed number of clock pulses are sequentially counted from among the clock pulses input to the memory device 130. When a memory cell is accessed through control by the read/write control module M14, the counter value of the address counter M13 is output from the address counter M13 to an address decoder of the memory cell array, not shown. Consequently, a prescribed row (word line) of the memory cell array 132 is selected in correspondence with the counter value. In the present embodiment, a “row” is selected by the address decoder on the basis of the counter value output by address counter M13. According to the content of the command data (indicative of the type of access) that was parsed by the command parse module M12, the read/write control module M14 performs a batch write operation into a single row and a batch read operation from a single row of the ferroelectric memory array 132 that is connected to the word line selected by the address counter M13. The read/write control module M14 is provided with a register, not shown, and is able to temporarily store original data, inverted data, and mirror data, discussed later in detail. The data send/receive module M15 synchronously with the clock signal CSCK receives a data signal CSDA sent from the sub-controller 50 via the data signal line LD1, or synchronously with the clock signal CSCK sends a data signal CSDA via the data signal line LD1. Specifically, the data send/receive module M15 sets the send/receive direction of data signals CSDA exchanged between the memory device 130 and the sub-controller 50. After initialization, when access to the memory device 130 by the sub-controller 50 is initiated, the send/receive direction of the data send/receive module M15 is set to the direction in which the memory device 130 receives data signals CSDA sent from the sub-controller 50, so that data read out from the memory cell array 132 is not sent from the memory device 130 to the sub-controller 50. The copy data generation module M17 is adapted to copy original data (discussed later) to generate mirror data (discussed later) equal in size to the original data. The inverted data generation module M18 is adapted to invert the value of each bit of the original data to generate inverted data (discussed later) equal in size to the original data. The data determination module M19 is designed to perform a parity check and exclusive OR operation of the original data and the mirror data, discussed later, to determine the consistency of the data. The counter control module M16 is furnished with a clock counter. After access to the memory device 130 by the sub-controller 50 is initiated after the memory device 130 is initialized, the counter control module M16 counts the number of clock pulses of the clock signal CSCK input to the memory device 130. After a prescribed counter value is reached, based on the outcome of command parsing by the command parse module M12, the counter control module M16 issues a control signal to the address counter M13 to cause the address counter M13 to either count up or count down the counter value. The data send/receive module M15 in the present embodiment corresponds to the data reception section and the data transmission section in the present invention.
In the identification information area and the rewriteable area, the upper 15 bits of the original data area of each row are used for storing actual data; while the last bit (the 16th bit) is used for storing parity data P that is associated with the actual data. In the present embodiment, actual data is data that is used by the main controller 40 of the printer 20 for controlling various aspects of printer 20 operation (e.g. printing operations, control of the user interface). In the present embodiment, the actual data includes, for example, data representing remaining ink level, the date and time that the ink cartridge was first placed in service, and so on. The upper 15 bits of the mirror data area are used for storing mirror data of the actual data of the original data, while the last bit (the 16th bit) is used for storing mirror data of the parity data P that is associated with the actual data of the original data. The parity data P is a redundant bit that is set to a value of either “1” or “0” in such a way that the number of bits of “1” value in 16-bit data consisting of the upper 15 bits and the parity data P is always an odd number. The parity data P may instead be set to either “1” or “0” in such a way that the number of bits of “1” value in 16-bit data consisting of the upper 15 bits and the parity data P is always an even number. The parity data P should not be construed as limiting, and any of various of types of redundancy data that provide redundancy of actual data may be used instead.
Of the (n−m) rows in the read-only area, rows except for the last row An−1 are used for actual data storage, while the last row is used for parity data storage. Specifically, for each of prescribed units of actual data (e.g. 8-bit or 16-bit units) of rows except for the last row, 1-bit parity data is assigned to a bit in the last row. In
As will be appreciated from the preceding discussion, in the identification information area and the rewriteable area, the original data consists of actual data and parity data. In the read-only area, in areas apart from the last row, the original data is actual data per se. In the read-only area, in the last row, the original data is parity data.
The rewriteable area stores various kinds of information, for example, remaining ink level information or usage history information for the ink cartridge 100. The ID number (identification information, which is chosen for each type (color) of ink cartridge 100, is stored on the 8 bits starting from the lead cell in the leading first row (the identification information area of Row A0) which is selected by the initial value of the address counter M13 immediately after access to the memory device 130 is initiated. In
The read-only area stores, for example, manufacturer information indicating the manufacturer of the ink cartridge 100, the date of manufacture of the ink cartridge, the ink cartridge 100 capacity, the type of ink cartridge, and so on. The control area stores increment flag information and write lock information.
One bit of increment flag information is provided for each row on the memory map. A row whose associated increment flag information is set to “1” represents an area in which the row is allowed to be overwritten with only a larger numerical value than the numerical value already stored in the row (incremental overwrite), but the row is not allowed to be overwritten with a smaller numerical value than the numerical value already stored in the row (decremental overwrite). A row whose associated increment flag information is set to “0” is allowed to be overwritten freely. The decision as to whether to allow only incremental overwrites or to allow free overwriting is made by the read/write control module M14 of the memory control circuit 136, with reference to the increment flag information. Specifically, for Row A1 and Row A2 which record the aforementioned first ink consumption count value X and second ink consumption count value Y, the corresponding increment flag information is set to “1”. The reason is that it is difficult to imagine that updating of first ink consumption count value X and the second ink consumption count value Y by the printer 20 would take place in anything other than the increasing direction. This can reduce the likelihood of write errors to Row A1 and Row A2. Hereinbelow, memory areas for which, like Row A1 and Row A2, the corresponding increment flag information is set to “1” is also referred to as increment areas. Overwriting to a row may be allowed in instances where the data overwrite is an incremental overwrite made in 16-bit original data units rather than in row units. Where remaining ink level, rather than ink consumption, is saved in a row of the memory, this row may be controlled by a flag value that indicates whether to allow only decremental overwriting or to allow free overwriting.
One bit of write lock flag information is provided for each row in the identification information area, the rewriteable area, and the read-only area. A row whose associated write lock flag information is set to “1” represents an area that is not allowed to be overwritten through external access. A row whose associated write lock flag information is set to “0” represents an area that is allowed to be overwritten through external access. The decision as to whether to allow overwriting is made by the read/write control module M14 of the memory control circuit 136, with reference to the write lock flag information. For the rewriteable area, i.e. Rows A1 to Am−1, the corresponding write lock flag information is set to “0” at the factory prior to shipping, so as to permit erasing and/or rewriting of data by the communication process module 55 of the printer 20. On the other hand, for the identification information area, i.e. Row A0, and for the read-only area, i.e. Rows Am to An−1, the corresponding write lock flag information is set to “1” at the factory prior to shipping, so as to prohibit erasing and/or rewriting of data by the communication process module 55 of the printer 20. Such memory areas for which the write lock flag information is set to “1” is also referred to as write-locked areas.
The sensor 110, which is not depicted in detail in the drawings, is furnished with a cavity (resonance portion) that defines part of the ink flow channel in proximity to the ink delivery section; an oscillator plate forming part of the wall of the cavity; and a piezoelectric element arranged on the oscillator plate. The sensor process module 52 of the printer 20 can apply a sensor drive signal DS to the piezoelectric element via the sensor drive terminals 230, 270, and thereby induce oscillation of the oscillator plate through the agency of the piezoelectric element. Then, by receiving from the piezoelectric element a response signal RS having the frequency of the residual vibration of the oscillator plate, the sensor process module 52 can detect if ink is present or absent in the cavity. Specifically, if the ink contained in the main body 101 is consumed so that the condition of the cavity interior changes from a condition filled with ink to a condition filled with air, the frequency of the residual vibration of the oscillator plate changes. This change in frequency is reflected in a change in frequency of the response signal RS. By measuring the frequency of the response signal RS, the sensor process module 52 can detect if ink is present or absent in the cavity. Detecting that ink is “absent” in the cavity means that the remaining ink level contained in the main body 101 is equal to or less than the first threshold value Vref1 (this corresponds to the amount of ink remaining downstream from the cavity). Detecting that ink is “present” in the cavity means that the remaining ink level contained in the main body 101 is greater than the first threshold value Vref1.
Read Operation from Memory Device:
The main controller 40 of the printer 20, via the bus BS, sends the sub-controller 50 a Read command instructing that a read operation from the memory device 130 of the ink cartridge 100 be carried out. The communication process module 55 supplies the power supply voltage CVDD to each of the ink cartridges 100 via the first power supply line LCV. Specifically, the memory device 130 of each of the ink cartridges 100 is supplied with operating voltage, thereby placing the memory device 130 in the operational state. After supplying the power supply voltage CVDD, a low level reset signal is supplied to initialize the memory devices 130. Because the reset signal remains at low level since the time that the previous access ended, it is at low level even before the power supply voltage CVDD is supplied to the memory device 130. When the communication process module 55 of the sub-controller 50 receives the Read command, the read operation depicted in the flowchart of
When the read operation starts, the communication process module 55 transitions the reset signal CRST from low level to high level, and transmits a clock signal CSCK of prescribed frequency (
The communication process module 55 first transmits SOF (Start Of Frame) data as a data signal CSDA (
Following the SOF data, the communication process module 55 sends an operation code. An operation code is a sequence of identification data and command data. Command data is data for indicating a particular type of access (e.g. a read or write operation) to the memory device 130. The communication process module 55 sends identification data as a data signal CSDA (
Following the identification data, the communication process module 55 sends command data as a data signal CSDA (
In synchronization with the next rise of the clock signal CSCK following the end of transmission of the command data, reception of the read data sent from the memory device 130 starts. The communication process module 55 receives read data including data that is read out from a row of the memory device 130. To discuss in more detail, the communication process module 55 receives a unit of read data equivalent to 8 bits×8=64 bits, doing so sequentially one bit at a time in sync with rise of the clock signal CSCK (
The 16-bit data having the original data upper 8 bits UDn as its upper bits and the original data lower 8 bits LDn as its lower bits are also referred to as original data Dn. The 16-bit data having the inverted original data upper 8 bits /UDn as its upper bits and the inverted original data lower 8 bits /LDn as its lower bits are also referred to as inverted data /Dn. The 16-bit data having the mirror data upper 8 bits Udn as its upper bits and the mirror data lower 8 bits Ldn as its lower bits are also referred to as mirror data dn. The 16-bit data having the inverted mirror data upper 8 bits /Udn as its upper bits and the inverted mirror data lower 8 bits /Ldn as its lower bits are also referred to as inverted mirror data /dn. That is, the unit of read data can be said to represent data made up of original data Dn, inverted data /Dn, mirror data dn, and inverted mirror data /dn. Ultimately, by repeating reception of units of read data n times, the communication process module 55 of the sub-controller 50 receives all of the data that is to be read (discussed later). It should be noted that the original data Dn and mirror data dn are read out from the memory cell array 132 while the inverted data /Dn and inverted mirror data /dn are generated from the original data Dn and mirror data dn by the inverted data generation module M18.
When a unit of read data is received, the communication process module 55 temporarily stores the unit of read data in a register (not shown) and executes the process described below. First, from the unit of read data, the communication process module 55 decides whether or not the exclusive OR of an m-th value of the original data Dn and an m-th value of the inverted mirror data /dn is true “1” for all values of m (1≦m≦16) (
If on the other hand the output of the exclusive OR operation is false “0” for any of the 16 bits, i.e. if not FFFF (
If the exclusive OR operation outcomes for all the m-th values of the original data Dn and all the m-th values of the inverted data /Dn are FFFF (
Once Step S120 or Step S116 is executed, the communication process module 55 decides whether all data targeted for the read operation are read out (
The discussion now turns to processing that takes place on the memory device 130 (memory device processing) in response to a read operation from the memory device 130 at the communication process module 55 discussed above. Because processing executed in the memory device 130 is the same up to step of receiving the operation code and step of parsing the command data (type of access), the discussion is not limited to read operations and includes other processes (e.g. write operations) as well. The memory device 130 receives input of power supply voltage CVDD from the sub-controller 50 and is activated. The memory device 130 then initializes itself in response to input of a low level reset signal CRST. After receiving supply of power supply voltage CVDD, because the reset signal CRST is low (
After initialization of the memory device 130 is carried out, the address counter M13 is set to its initial value at the time of initialization, and the various registers are reset to their initial values as well. Additionally, the data send/receive module M15 of the memory device 130 sets the send/receive direction for data exchanged via the data terminal to the direction in which the memory device 130 receives data from the sub-controller 50. The read/write control module M14 sets the data transfer direction vis-à-vis the ferroelectric memory array 132 to the data read direction.
As depicted in
If on the other hand the ID comparator module M11 decides that the received identification data is correct (Step S225: YES), it then decides whether the ID number (identification information) that is assigned to the memory device 130 itself matches the received identification data (
If the ID comparator module M11 decides that the ID number (identification information) assigned to the memory device does not match the received identification data (
In the event of a decision that the command data is not correct (Step S245: NO), the memory control circuit 136 terminates processing. If on the other hand it is decided that command data is correct (Step S245: YES), the command parse module M12 of the memory control circuit 136 parses the received command and determine the type of access (
If the command directed to the memory device 130 does not correspond to any of the above types of command, the command parse module M12 decides that the command data is not parsable. If the command parse module M12 decides that the command data is not parsable, the memory control circuit 136 proceeds to terminate, and do nothing (not shown).
If the command parse module M12 decides that the command indicated by the command data is a Read command, the memory control circuit 136 executes a read operation on the memory device (
From the 32 bits that were read into the register, the data send/receive module M15 first selects the upper 8 bits as the original data upper 8 bits UDn mentioned previously, and sends these to the sub-controller 50 (
After sending of the 32 bits that are read into the register is finished, if transmission of all of the data that is requested to be read by the sub-controller 50 is not completed (
In the event that the ID comparator module M11 or the command parse module M12 determines that the ID data or the command data CM includes a communication error, and the memory control circuit 136 terminates processing without any meaningful process accordingly, the memory device 130 does not transmit any data during the read data transmission period. As described previously, the data signal line LD1 is maintained at a low level by the resistor R1 of the sub-controller 50 when there is no data transmission between the sub-controller 50 and the memory device 130. Then the communication process module 55 receives low level data during the entire period for receiving the original data Dn and the inverted data /Dn, whereby the decision of Step S112 in
Write Operation to Memory Device:
Via the bus BS, the main controller 40 of the printer 20 writes to the SRAM 551 in the sub-controller 50, the data that is to be written into the memory device 130 of a particular ink cartridge 100. Specifically, this data is written into write target rows which are allocated in the SRAM 551 for writing of original data corresponding to the ferroelectric memory cell array 132 of the memory device 130. During a write operation, the main controller 40 recognizes that the memory device 130 is a memory in which one row equals 16 bits. Thus, the data that is to be written into the memory device 130 is divided into 16-bit units, in which 16-bit unit the upper 15 bits are actual data and the lower 1 bit is parity data. The parity data may also be generated by the main controller 40, appended to the upper 15 bit actual data, and written into the SRAM 551 as data of 16 bits in total. Alternatively, the parity data may also be generated by the sub-controller 50, and appended each time that 15-bit data is written into the SRAM 551 by the main controller 40. The main controller 40 then transmits to the sub-controller 50 via the bus a Write command instructing that the write-targeted memory device 130 be notified, and that the data that is written into the SRAM 551 be written into the memory device 130 that is targeted for the write operation. Upon receiving the Write command, the sub-controller 50 supplies each ink cartridge 100 with the power supply voltage CVDD via the first power supply line LCV, placing the memory device 130 of each ink cartridge 100 in the operable state. After the power supply voltage CVDD is supplied by the sub-controller 50, a low level reset signal CRST is supplied by the sub-controller 50 and the memory devices 130 is initialized. Because the reset signal remains at low level since the time that the previous access ended, it is at low level even before the power supply voltage CVDD is supplied to the memory devices 130. The communication process module 55 of the sub-controller 50 then initiates the write operation shown in the flowchart of
During write operations, the communication process module 55 recognizes the memory map depicted in
When the write operation starts, the communication process module 55 transitions the reset signal CRST from low level to high level, and transmits a clock signal CSCK of a prescribed frequency (
As in the read operation described earlier, the communication process module 55 first transmits SOF data as a data signal CSDA (
In sync with the next rise of the clock signal CSCK following the end of transmission of the command data, the communication process module 55 sends the write data so that the memory control circuit 136 of the memory device 130 receives the data one bit at a time. The write data is sent in row order starting from the data to be written into Row A1. Specifically, the communication process module 55 sequentially sends unit write data equivalent to 8 bits×4=32 bits (
In sync with the next rise of the clock signal CSCK following the end of transmission of a unit of write data, the communication process module 55 receives a 1-bit (either a “1” or a “0”) response signal from the memory control circuit 136 (
If the received response signal is not affirmative (
If on the other hand the received response signal is affirmative (
The discussion now turns to processing that takes place on the memory device 130 (memory device processing) in response to a write operation to the memory device 130 on the printer 20 side discussed above. The memory device processing in response to the write operation is the same as that during a read operation from S210 to S250 in
When one unit of the 32-bit write data is received, the data determination module M19 decides whether or not the exclusive OR of an m-th value of the original data Dn and an m-th value of the inverted mirror data /dn is true “1” for all values of m (1≦m≦16), i.e. whether or not it is FFFF (
If the output of the exclusive OR operation (determination outcome by the data determination module M19) is false “0” for any of the 16 bits, i.e. if it is not FFFF (
If on the other hand the output of the exclusive OR operation (determination outcome by the data determination module M19) is affirmative (true “1’) for all 16 bits, i.e. if it is FFFF (
The response signal (either an NG response signal or an OK response signal) is transmitted in sync with the next rise of the clock signal CSCK following reception of a unit of the 32-bit write data (
If an OK response signal is sent, the copy data generation module M17 of the memory control circuit 136 generates mirror data dn which is a copy of the received 16-bit original data (
Next, the read/write control module M14 reads the previously stored data from the memory area targeted for writing (write-targeted memory area) of the original data Dn and the mirror data dn, whereupon the data determination module M19 performs a parity check of the read out previously stored data (
Once the parity check is finished, the read/write control module M14 carries out writing of data to the write-targeted memory area (
When performing writing of data to a write-targeted memory area, the command parse module M12 of the memory control circuit 136 decides whether all of the data for writing has been received (
As described above, during a write operation (
In the initial phase of a write operation, from the time that reception of identification data ID starts until reception of the first set of write data D1 and inverted write data /D1 is finished, no data consistency determination results are sent to the communication process module 55, and thus the number of times that determination results are sent from the memory device 130 to the communication process module 55 is reduced, and the write operation as a whole is carried out efficiently. Moreover, in write operations, consistency of the identification data ID and inverted identification data /ID, and consistency of the write command data CM and the inverted write command data /CM, are determined as in read operations (see Steps S220 to S245 of
Additionally, as depicted in
The actual data of the original data in the present embodiment corresponds to the first actual data in the present invention, and the parity data for the actual data in the present embodiment corresponds to the first parity data in the present invention. The mirror data of the actual data of the original data in the present embodiment corresponds to the second actual data in the present invention, and the mirror data of the parity data for the actual data in the present embodiment corresponds to the second parity data in the present invention. The actual data area in the present embodiment corresponds to the first memory area in the present invention, and the mirror data area in the present embodiment corresponds to the second memory area in the present invention.
Memory Device Write Lock Operation:
As in the read operation and write operation discussed above, the communication process module 55 first sends SOF data as a data signal CSDA (
In sync with the next rise of the clock signal CSCK following completion of transmission of the write lock-targeted address data AD and inverted write lock-targeted address data /AD, the communication process module 55 receives a 1-bit response signal (either a “1” or a “0”) from the memory device 130 (
If the received response signal is an NG response signal, the communication process module 55 carries out a prescribed error process and terminate the write lock operation. The error process is a process identical to the error process that takes place when an NG response signal is received in the write operation described above, for example. On the other hand, if the received response signal is an OK response signal, the communication process module 55 sends EOF (End of Frame) data to the memory device 130 and terminate the process (
The discussion now turns to processing that takes place on the memory device 130 (memory device processing) in response to the write lock operation to the memory device 130 at the printer 20 discussed above. The memory device processing in response to the write lock operation is described in
When the write lock operation starts, the read/write control module M14 of the memory control circuit 136, in sync with rise of the clock signal CSCK, sequentially receives signals (1's or 0's) that appear on the data signal line LD1 following the command data, and sequentially stores these in the register. As a result, the memory control circuit 136 sequentially receives the write lock-targeted address data AD and inverted write lock-targeted address data /AD.
The data determination module M19 decides whether or not the output of an exclusive OR operation for the received write lock-targeted address data AD and inverted write lock-targeted address data /AD is true for all 8 bits of these data, i.e. whether or not it is 11111111 (FF). If it is found that the output of the exclusive OR operation is not FF, the data send/receive module M15 sends an NG response signal (low level) to the communication process module 55 of the sub-controller 50. Once the NG response signal is sent, the write lock operation on the memory device terminates (abnormal termination).
If on the other hand the output of the exclusive OR operation is true “1” for all 8 bits, i.e. if it is FF, the read/write control module M14 changes the row of the rewriteable area identified by the write lock-targeted address data AD of the control area to a write lock area. Specifically, after receiving the operation code, if the type of access is write lock, the counter control module M16 sets the counter value of the address counter M13 so as to select the lead row of the control area. The count then advances to select a row that includes a cell storing a flag for the write lock-targeted address data AD in the control area. After the row that includes a cell storing a flag for the write lock-targeted address data AD is selected by the address counter M13 as the row targeted for the write operation, the read/write control module M14 updates the row so that the flag information of the cell corresponding to the write lock-targeted address data AD changes from “0” to “1”. The read/write control module M14 updates the cell of the control area storing the flag for the row of the rewriteable area identified by the write lock-targeted address data AD, thereby changing the row of the rewriteable area identified by the write lock-targeted address data AD to a write lock area, and terminate the write lock operation. Specifically, the read/write control module M14 changes the write lock flag information corresponding to the row identified by the write lock-targeted address data AD from “0” to “1”.
Printer Printing Operation:
In light of the processes relating to the memory devices 130 discussed above, the discussion now turns to the printing operation in the printer 20.
The printing operation is initiated when the main controller 40 receives a print request from the user via the computer 90 or the console portion 70 (
When the main controller 40 reads out the ink information, it decides whether the value of the ink end information M indicates either the full state, the low state, or the end state mentioned previously (
If the main controller 40 decides that the ink end information M indicates the low state (
On the other hand, if the main controller 40 decides that the ink end information M indicates the full state (
Once the predetermined amount of printing is carried out, the main controller 40 calculates a new ink consumption count value (
Once the new ink consumption count value is calculated, the main controller 40 drives the sensor 110 (
If the remaining ink level in the ink cartridge 100 is determined to be equal to or greater than the first threshold value Vref1 (
On the other hand, if the remaining ink level in the ink cartridge 100 is determined to be less than the first threshold value Vref1 (
When the second ink consumption count value lock operation is completed, the main controller 40 executes the write operation discussed earlier on the first ink consumption count value X in the memory device 130, thereby updating it to the new ink consumption count value that was calculated in Step S516 (
When the first ink consumption count value X is updated, the main controller 40 decides whether the value of the difference (X-Y) between the first ink consumption count value X and the second ink consumption count value Y is equal to or greater than a second threshold value Vref2 (
After the first ink consumption count value X and the second ink consumption count value Y are updated in Step S522, or if in Step S528 the value of (X-Y) is found to be less than the second threshold value Vref2 (
According to the present embodiment discussed above, during a write operation to the memory device 130, the memory device 130 verifies the consistency of the original data Dn that is to be written to the memory cell array 132 and the inverted data /Dn, and for each 16 bits of original data Dn transmits a response signal indicating if there is consistency. As a result, reliability of communication between the sub-controller 50 and the memory device 130 is enhanced. If the original data Dn and the inverted data /Dn lack consistency, the memory device 130 does not write the original data Dn to the ferroelectric memory array 132, so erroneous updating of the ferroelectric memory array 132 is avoided. Moreover, during write operations to the memory device 130, because the original data Dn and the inverted data /Dn have an inverted bit relationship to one another, if for example there is encountered a communication error such that only low level or high level appears on the data signal line LD1 owing to a contact fault between the data terminal 260 of the ink cartridge 100 and the corresponding terminal on the printer 20, the communication error is detected in a reliable manner. Moreover, because consistency (presence or lack of communication errors) of the original data Dn and the inverted data /Dn is determined through an exclusive OR operation carried out on each bit of the original data Dn and the inverted data /Dn, highly reliable detection of communication errors is accomplished easily.
Furthermore, according to the present embodiment, during a read operation from the memory device 130 original data Dn, together with inverted data /Dn which is equal in size to the original data Dn but with each bit inverted, are sent from the memory device 130 to the sub-controller 50. At the sub-controller 50, the presence or lack of communication errors is then determined by checking the consistency of the original data Dn and the inverted data /Dn. As a result, reliability of communication between the sub-controller 50 and the memory device 130 is enhanced. Consequently, problems such as erroneous operation of the printer 20 are kept to a minimum. Moreover, during read operations from the memory device 130, because the original data Dn and the inverted data /Dn have an inverted bit relationship to one another, if for example there is encountered a communication error such that only low level or high level appears on the data signal line LD1 owing to a contact fault between the data terminal 260 of the ink cartridge 100 and the corresponding terminal on the printer 20, the communication error is detected in a reliable manner. Further, during read operations from the memory device 130, because the memory device 130 sends the sub-controller 50 mirror data dn which is substantially identical to the original data Dn, and inverted mirror data /dn which is substantially identical to the inverted data /Dn, even if the original data Dn and the inverted data /Dn lack consistency owing to a communication error for example, as long as the mirror data dn and the inverted mirror data /dn have consistency, processing can continue on the printer 20 using either the mirror data dn or the inverted mirror data /dn, thus enhancing the robustness of the system with respect to communication errors. Further, in the memory device 130, mirror data dn is stored together with original data Dn in the ferroelectric memory array 132, and both are sent to the printer 20. As a result, even if a cell error is occurred in either the original data area or the mirror data area of the ferroelectric memory array 132, normal operation may continue on the printer 20, using the data stored in the area in which the cell error did not occur. Robustness of the system with respect to cell errors is enhanced thereby, thus dramatically reducing memory device 130 failure rates.
Further, when the printer 20 in the present embodiment receives original data Dn, inverted data /Dn, mirror data dn, and inverted mirror data /dn, it first performs a consistency check of the original data Dn and the inverted mirror data /dn; and if consistency is lacking, checks the consistency of the original data Dn and the inverted data /Dn, and the consistency of the mirror data dn and the inverted mirror data /dn. Then, if the original data Dn and the inverted mirror data /dn lack consistency, but the original data Dn and the inverted data /Dn have consistency and the mirror data dn and the inverted mirror data /dn have consistency, it determines that a cell error is occurred. If the original data Dn and the inverted mirror data /dn lack consistency, and moreover the original data Dn and the inverted data /Dn lack consistency or the mirror data dn and the inverted mirror data /dn lack consistency, it determines that a communication error is occurred. By so doing the printer 20 can correctly ascertain the type of the error, and perform appropriate processing according to the error type.
Further, in the present embodiment, in the memory map of the ferroelectric memory array 132 (
In write operations in the present embodiment, for previously stored data in a write-targeted area, the memory device 130 carries out a parity check of the 16 bits stored in the original data area and the 16 bits stored in the mirror data area, respectively. As a result, in an area in which a parity error is detected, the previously stored data is rewritten; whereas in an area in which no parity error is detected, new data is written. Because an area in which a parity error is detected can be assumed to have a problem with a memory cell, the parity check may also be recognized as a means for detecting memory area problem. As a result, data updating is not performed in an area in which a problem is occurred, so unanticipated difficulties that may result from updating data in an area that includes a problem may be avoided. Moreover, in a cell that is experiencing a cell error, by rewriting previously stored data to an area in which a parity error is detected, change in data due to a data retention fault may be avoided. A data retention fault refers to a fault whereby the saved data value in a memory cell changes due to gradual dissipation of charge. If owing to a data retention fault, data changes in an area in which a cell error is assumed to have occurred, parity consistency may happen by chance, posing a risk that the cell error is not correctly detected.
Further, in the printer 20 according to the present embodiment, if through driving of the sensor 110 it is determined that the remaining ink level of the ink cartridge 100 is less than the first threshold value Vref1, a prohibit request (write lock operation) is carried out for the memory area of the memory device 130 storing the second ink consumption count value Y, so that the second ink consumption count value Y will not be updated. As a result, after the prohibit request is issued, the memory device 130 no longer accepts requests to update the second ink consumption count value Y. As a result, the second ink consumption count value Y is maintained at the ink consumption count value that obtained just prior to the time that the sensor detected that the remaining ink level was lower than the first threshold value Vref1. The second ink consumption count value Y is thus prevented from being updated in error. Further, because the first ink consumption count value X continues to be updated even after updating of the second ink consumption count value Y is suspended, the ink consumption level is accurately recognized from the value of (X-Y) even after the sensor 110 detects that the remaining ink level is lower than the first threshold value Vref1. As a result, an ink end point is determined with good accuracy, making it possible for the ink contained in the ink cartridge 100 to be used to the end without any waste. The copy data generation module M17 in the present embodiment corresponds to the data copy section in the present invention, and the data determination module M19 in the present embodiment corresponds to the first and second detection section in the present invention.
B. Modified Embodiments:
Modified Embodiment 1:
In the preceding embodiment, inverted data /Dn is used as an example of “the data generated on the basis of the original data Dn”, but no limitation thereto is implied. For example, a value obtained through addition of a given value to the original data Dn, a value obtained through subtraction of a given value, a value obtained through multiplication by a given value, or the like may also be used as data for checking consistency with the original data Dn. Generally, it suffices for the original data Dn and the data generated from the original data Dn to have a prescribed correlation such that the presence or lack of this prescribed correlation between the original data Dn and the data generated from the original data Dn can be determined. In preferred practice, the original data Dn and the data generated from the original data Dn have identical data size.
Modified Embodiment 2:
In the write operation of the preceding embodiment, 32 bit data composed of original data upper 8 bits UDn, inverted mirror data upper 8 bits /Udn, original data lower 8 bits LDn, and inverted mirror data lower 8 bits /Ldn are transmitted in that order from the sub-controller 50 to the memory device 130; however, the order of transmission may be modified as desired, and it is acceptable to first transmit 16 bits of original data Dn1, followed by transmission of 16 bits of inverted data /Dn. Also, the inverted data may be sent first, and the original data sent afterwards.
Modified Embodiment 3:
In the write operation of the preceding embodiment, 32 bits of original data and inverted data are employed as a single unit of data, and each time that transmission of one unit of data from the sub-controller 50 to the memory device is finished, a response signal is returned from the memory device to the sub-controller 50; however, the data length of the unit of data is may be modified as desired, and a single data unit may include 64 bits of original data and inverted data, or a single data unit may include 16 bits of original data and inverted data.
Modified Embodiment 4:
In the preceding embodiment, the sub-controller 50 of the printer 20 is used as the host circuit; however, any circuit, such as a computor, may be used as the host circuit. In the preceding embodiment, the memory device 130 of an ink cartridge 100 is used as the memory device, but any nonvolatile memory device may be used. In this case, the invention may be implemented effectively in an arrangement whereby the host circuit and the memory device are electrically connected via circuit terminals that are electrically connected to the host circuit, and memory device terminals that are electrically connected to the memory device and that are detachably attachable to the circuit terminals. By so doing, communication errors arising from faulty contact between memory device terminals and circuit terminals may be detected, and the reliability of communication between the host circuit and the memory device may be enhanced.
Modified Embodiment 5:
In the preceding embodiment, the ferroelectric memory array 132 is provided with both an original data area and a mirror data area; however, only an original data would suffice. In this case, the memory control circuit 136 may be provided with a read copy data generation section adapted to copy data stored in the original data area to generate mirror data dn (copy data), and with an inverted data generation section adapted to invert each bit of the data stored in the original data area to generate inverted data /Dn and inverted mirror data /dn. Then, during the read operation at the memory device 130, the data send/receive module M15 of the memory control circuit 136 sends the data that is stored in the original data area as original data Dn to the sub-controller 50; and sends the sub-controller 50 the mirror data dn, the inverted data /Dn, and the inverted mirror data /dn which are generated from the original data Dn. The data send/receive module M15, after storing the data read out from the original data area in a register, may send it as original data, and then send other data stored in the register as mirror data.
Modified Embodiment 6:
In the preceding embodiment, the ferroelectric memory array 132 has an original data area and a mirror data area; however, the ferroelectric memory array 132 may instead have an original data area and an inverted data area. In this case, the read/write control module M14 writes the original data Dn in the original data area, and writes the inverted data /Dn in the inverted data area. During read operations, the data send/receive module M15 of the memory control circuit 136 sends to the sub-controller 50 as original data Dn the data stored in the original data area, and as inverted data /Dn the data stored in the inverted data area; and sends to the sub-controller 50 as mirror data dn the data which is read from this same original data area, and as inverted mirror data /dn the data which is read from this same inverted data area. In this case as well, the host circuit is able to detect communication errors through exclusive OR operations. It is possible to detect the occurrence of memory cell errors by carrying out a parity check.
Modified Embodiment 7:
In the preceding embodiment, the ferroelectric memory array 132 has an original data area and a mirror data area; however, the ferroelectric memory array 132 may instead have an original data area for storing original data Dn, and inverted data area for storing inverted data /Dn of the original data Dn, a mirror data area for storing mirror data dn of the original data Dn, and an inverted mirror data area for storing inverted mirror data /dn which is inverted data of the mirror data dn. In this case, the read/write control module M14 and the data send/receive module M15 of the memory control circuit 136 read out the stored data as-is and transmit it.
Modified Embodiment 8:
In the read operation in the preceding embodiment, original data Dn, inverted data /Dn, mirror data dn, and inverted mirror data /dn are transmitted from the memory device 130 to the sub-controller 50; however, it would suffice to transmit original data Dn and inverted data /Dn only, omitting transmission of mirror data dn and inverted mirror data /dn. Alternatively, it would suffice to transmit original data Dn and mirror data dn only, omitting transmission of inverted data /Dn and inverted mirror data /dn.
Modified Embodiment 9:
In the write operation in the preceding embodiment, both actual data and parity data for storage in the memory map of the ferroelectric memory array 132 are generated on the printer 20 and transmitted to the memory device 130. As an alternative, it is permissible that the printer 20 generates only the actual data and transmits it to the memory device 130, while the parity data is generated on the memory device 130. In this case, the memory control circuit 136 may be provided with a parity acquisition module for generating 1-bit parity data matching the 15 bits of actual data sent from the printer 20.
Modified Embodiment 10:
In the write operation in the preceding embodiment, the memory device 130 performs rewriting of the previously stored data to areas in which parity errors are detected, but a possible alternative would be to not write data to areas in which parity errors are detected.
Modified Embodiment 11:
In the preceding embodiment, the ferroelectric memory array 132 of the memory device 130 stores a first ink consumption count value X and a second ink consumption count value Y that represent the amount of ink consumption; however, remaining level information representing the remaining ink level may also be stored. In this case, the initial value of the remaining level information represents the amount of ink filling the ink cartridge 100. During printing operations, the printer 20 overwrites the remaining level information stored in the ferroelectric memory array 132 with remaining level information in the direction of decreasing the remaining level, according to the amount of ink consumed in printing. In this case, it is preferable for the memory area storing the remaining level information to be established in a decrement area. A decrement area refers to an area that only allows numerical values to be overwritten in the decreasing direction, and does not allow numerical values to be overwritten in the increasing direction. Like the increment area in the embodiment, such a decrement area is preferably established by writing decrement flag information to the read-only area.
Modified Embodiment 12:
In the preceding embodiment, the second ink consumption count value Y and the first ink consumption count value X are respectively stored in the ferroelectric memory array 132, and ink end is determined on the basis of the difference between the first ink consumption count value X and the second ink consumption count value Y. Alternatively, only the second ink consumption count value Y may be stored in the ferroelectric memory array 132. In this case, processes would take place in the same manner as the embodiment, but with the first ink consumption count value X stored in nonvolatile memory provided on the printer 20.
Modified Embodiment 13:
While the preceding embodiment employs a printer and ink cartridges of ink-jet format, it would also be acceptable to employ a liquid jetting apparatus adapted to jet or eject a liquid other than ink, and liquid receptacles for supplying the liquid to the liquid jetting apparatus. Herein, the term liquid is used to include a liquid state body containing particles of a functional material dispersed in a medium; or a gel or similar fluid state body. For example, there may be employed a liquid jetting apparatus adapted to jet a liquid containing an electrode material, coloring matter, or other matter in dispersed or dissolved form, that is used in the manufacture of liquid crystal displays, EL (electroluminescence) displays, field emission displays, or color filters; a liquid jetting apparatus adapted to jet bioorganic substances used in biochip manufacture; or a liquid jetting apparatus adapted to jet a liquid as a specimen used as a precision pipette. Additional examples are a liquid jetting apparatus for pinpoint jetting of a lubricant into a precision instrument such as a clock or camera; a liquid jetting apparatus adapted to jet a solution of an ultraviolet-curing resin or other transparent resin onto a substrate for the purpose of forming a micro semi-spherical lens (optical lens) for use in an optical communication component etc.; or a liquid jetting apparatus adapted to jet an acid or alkali etchant solution for etching a circuit board, etc.; as well as liquid receptacles adapted to supply liquid to these kinds of liquid jetting apparatus. The present invention may be implemented in any one of the above types of jetting devices and liquid receptacles. No limitation to printers of ink-jet format is imposed, and a laser printer and toner cartridge for printing with printing material such as toner may also be employed.
Modified Embodiment 14:
Some of the arrangements that are implemented through hardware in the preceding embodiment may instead be implemented through software, and conversely some of the arrangements that are implemented through software may instead be implemented through hardware.
Modified Embodiment 15:
In the preceding embodiment, a sensor 110 that uses a piezoelectric element is employed, but it would be possible for example to instead employ an oscillator device such as an oscillator circuit designed to constantly return a response signal whose frequency indicates that ink is present; or to employ a processor such as a CPU or ASIC, or a simpler IC, to carry out exchanges with the sub-controller 50. The present invention may also be implemented in an ink cartridge 100 of a type lacking a sensor, and having only a memory device.
Modified Embodiment 16:
In the preceding embodiment, a single ink tank constitutes a single ink cartridge, but instead a plurality of ink tanks may constitute a single ink cartridge.
Modified Embodiment 17:
In the preceding embodiment, the liquid supply unit is an ink cartridge to whose receptacle body the board is secured, and the board thusly unified with the receptacle body is installed in the holder provided to the print head unit; however, the liquid supply unit embodying the present invention may instead be an ink cartridge of a design in which a cover to which the board is secured, and a receptacle body containing the liquid, are installed separately in the holder. In one exemplary arrangement, after the cover having the board secured thereto is inserted and installed in the holder in a prescribed insertion direction, the receptacle body is then installed in the holder. In this case, there may be employed in arrangement whereby only the ink receptacle body is replaced when the ink inside the receptacle body is depleted, and the ink consumption information (the first second ink consumption count value X and the second ink consumption count value Y) saved in the memory device 130 is reset in association with replacement.
Modified Embodiment 18:
In the preceding embodiment, the liquid supply unit is installed in the holder of the print head unit and supplies ink directly to the print head from the ink supply portion; however in another possible arrangement, the liquid supply unit may be installed at a location inside the liquid jetting apparatus situated away from the head, and ink may be supplied to the head through a tube connecting the liquid supply unit to the ink supply portion.
Modified Embodiment 19:
In the preceding embodiment, the memory device 130 is described as being a semiconductor memory device furnished with a ferroelectric memory cell array 132, but is not limited thereto and may instead be a semiconductor memory device that does not use ferroelectric memory cells (e.g. EEPROM or flash memory). Memory devices other than semiconductor memory devices may also be used.
Modified Embodiment 20:
In the preceding embodiment, the main controller 40 and the communication process module 55 are separate arrangements, but they may instead be implemented as an integrated controller.
Modified Embodiment 21:
In the preceding embodiment, in the course of communications between the memory device 130 and sub-controller 50, the memory device 130 is presented with a reset signal CRST from the sub-controller 50; however, the element of supplying a reset signal CRST may be omitted. In this case, the reset terminal 240 of the memory device 130, the terminal 440 on the printer 20 corresponding to the reset terminal 240, and the reset signal line LR1 would be dispensed with. In this case, initialization of the memory device 130 may take place autonomously when the memory device 130 is supplied with power supply voltage CVDD and starts up for example. Having initialized at startup, the memory device 130 may subsequently operate in response to the clock signal CSCK and data signals CSDA received from the sub-controller 50, in the same way as in the embodiment.
Modified Embodiment 22:
In the preceding embodiment, the memory control circuit 136 of the memory device 130 includes the ID comparator module M11, the command parse module M12, and the data determination module M19. However, the ID comparator module M11, the command parse module M12, and the data determination module M19 may be implemented as respective separate hardware circuits. Alternatively, a part of or the entirety of these modules may be implemented as common hardware circuitry.
While the present invention is shown herein in terms of a preferred embodiment and modified embodiments thereof, the present invention is not limited to the embodiment and modified embodiments herein, and may be embodied in various other forms without departing from the spirit thereof.
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