Patent Application
20240064986
Embodiments described herein relate generally to a memory device.
A NAND flash memory is known as a memory device for storing data in a non-volatile manner. A memory device such as a NAND flash memory employs a three-dimensional memory structure to increase the capacity and the degree of integration.
According to one embodiment, a memory device includes: a first conductive layer; a first conductive film extending in a first direction above the first conductive layer; a first semiconductor film extending in the first direction between the first conductive layer and the first conductive film and intersecting the first conductive layer; a second semiconductor film that is in contact with the first semiconductor film, extends in the first direction between the first conductive layer and the first conductive film, and faces the first conductive film; a first insulating film provided between the first conductive layer and the first semiconductor film; and a second insulating film provided between the first conductive film and each of the first semiconductor film and the second semiconductor film.
Hereinafter, embodiments will be described with reference to the accompanying drawings. The dimensions, scales, etc., used in the drawings are not binding on actual products.
Note that in the following description, the same reference numerals denote components having almost the same functions and configurations. Especially when components having the same or substantially the same configuration are to be distinguished from each other, different characters or numerals may be added to the common reference symbol.
A memory device according to a first embodiment will be described.
First, a configuration of the memory device according to the first embodiment will be described.
The memory controller 2 is configured as, for example, an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on a request from the host device. More specifically, for example, the memory controller 2 writes data which the host device has requested the memory controller 2 to write to the memory device 3. Also, the memory controller 2 reads data which the host device has requested the memory controller 2 to read from the memory device 3 and transmits the data to the host device.
The memory device 3 is a memory that stores data in a nonvolatile manner. The memory device 3 is, for example, a NAND flash memory.
Communication between the memory controller 2 and the memory device 3 is based on, for example, a single data rate (SDR) interface, a toggle double data rate (DDR) interface, or an open NAND flash interface (ONFI).
Hereinafter, an internal configuration of the memory device according to the first embodiment will be described with reference to the block diagram shown in
The memory cell array 10 includes a plurality of blocks BLK0 through BLKn (where n is an integer equal to or greater than 1). A block BLK is a group of a plurality of memory cells capable of storing data in a non-volatile manner, and is used as, for example, a data erasure unit. The memory cell array 10 is provided with a plurality of bit lines and a plurality of word lines. In one example, each memory cell is associated with one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.
The command register 11 stores a command CMD received by the memory device 3 from the memory controller 2. Examples of the command CMD include instructions to cause the sequencer 13 to conduct read, write, and erase operations, etc.
The address register 12 stores address information ADD received by the memory device 3 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used to select a block BLK, a word line, and a bit line, respectively.
The sequencer 13 controls the operation of the entire memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, and the like based on the command CMD stored in the command register 11, thereby executing the write operation, the read operation, the erase operation, and the like.
The driver module 14 generates a voltage to be used in the read operation, the write operation, the erase operation, and the like. Then, the driver module 14 applies the generated voltage to a signal line corresponding to a selected word line based on, for example, the page address PAd stored in the address register 12.
Based on the block address BAd stored in the address register 12, the row decoder module 15 selects one corresponding block BLK in the memory cell array 10. Then, for example, the row decoder module 15 transfers the voltage that has been applied to the signal line corresponding to the selected word line to this selected word line in the selected block BLK.
The sense amplifier module 16, in a write operation, applies a certain voltage to each bit line in accordance with write data DAT received from the memory controller 2. In a read operation, the sense amplifier module 16 determines data stored in a memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 2 as the data DAT.
Each string unit SU includes a plurality of NAND strings NS associated with respective bit lines BL0 through BLm (m is an integer equal to or greater than 1). The NAND strings NS each include, for example, memory cell transistors MT0 through MT7 and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge accumulating film, and stores data in a non-volatile manner. The select transistors ST1 and ST2 are each used to select a string unit SU in various operations.
In each NAND string NS, the memory cell transistors MT0 through MT7 are coupled in series. A drain of the select transistor ST1 is coupled to a bit line BL associated therewith, and a source of the select transistor ST1 is coupled to one end of a set of memory cell transistors MT0 through MT7 coupled in series. A drain of the select transistor ST2 is coupled to the other end of the set of memory cell transistors MT0 through MT7 coupled in series. A source of the select transistor ST2 is coupled to a source line SL.
Control gates of the memory cell transistors MT0 through MT7 in the same block BLK are respectively coupled to the word lines WL0 through WL7. Gates of the select transistors ST1 in the string units SU0 through SU3 are respectively coupled to the select gate lines SGD0 through SGD3. Gates of the select transistors ST2 are coupled to a select gate line SGS.
The bit lines BL0 through BLm are assigned respective column addresses differing from one another. Each bit line BL is shared by the NAND strings NS to which the same column address is assigned among a plurality of blocks BLK. The word lines WL0 through WL7 are provided for each block BLK. The source line SL is shared by, for example, a plurality of blocks BLK.
A set of memory transistors MT coupled to a common word line WL in each string unit SU is referred to as, for example, a “cell unit CU”. For example, the storage capacity of the cell unit CU including the memory cell transistors MT each of which stores 1-bit data is defined as “1-page data”. The cell unit CU can have a storage capacity of 2-page data or more in accordance with the number of bits of data to be stored in the memory cell transistors MT.
Note that the circuit configuration of the memory cell array 10 provided in the memory device 3 according to the first embodiment is not limited to the above described configuration. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and the number of select transistors ST1 and ST2 included in each NAND string NS can be designed to be any numbers.
An example of the structure of the memory cell array included in the memory device according to the first embodiment will be described below. Note that in the drawings to be referred to below, an X direction corresponds to the extending direction of the word line WL. A Y direction corresponds to the extending direction of the bit line BL. A Z direction corresponds to a direction vertical to the surface of a semiconductor substrate used to form the memory device 3. In the plan views, hatching is appropriately added to make the drawing easier to view. The hatching added to the plan views is not necessarily associated with the material or characteristics of a component to which the hatching is added. In the sectional views, some components are appropriately omitted to make the drawing easier to view.
As shown in
The memory pillar MP includes a pillar-shaped electrode SP. The select gate line SGD0 includes a plurality of sub-select gate lines SGD0a, SGD0b, SGD0c, and SGD0d. The select gate line SGD1 includes a plurality of sub-select gate lines SGD1a, SGD1b, SGD1c, and SGD0d. The select gate line SGD2 includes a plurality of sub-select gate lines SGD2a, SGD2b, SGD2c, and SGD2d. The select gate line SGD3 includes a plurality of sub-select gate lines SGD3a, SGD3b, SGD3c, and SGD3d. The plurality of interconnects M1 include interconnects M1-0, M1-1, M1-2, and M1-3.
Each of the memory pillars MP functions as, for example, one NAND string NS. In the region between the two adjacent members SLT, the plurality of memory pillars MP are arranged in, for example, a staggered pattern of sixteen rows. The pillar-shaped electrode SP is provided in a central portion of the memory pillar MP in a plan view.
The plurality of sub-select gate lines SGD0a through SGD3d each extend in the X direction and are arranged in the Y direction. The sub-select gate lines SGD0a through SGD3d are electrically coupled to the corresponding pillar-shaped electrodes SP, respectively. In the example of
The interconnects M1 are disposed in a region where the memory pillars MP are not provided. Each of the interconnects M1 extends in the Y direction. To be specific, the interconnect M1-0 is electrically coupled to the sub-select gate lines SGD0a through SGD0d via the contacts VYB. The interconnect M1-1 is electrically coupled to the sub-select gate lines SGD1a through SGD1d via the contacts VYB. The interconnect M1-2 is electrically coupled to the sub-select gate lines SGD0a through SGD2d via the contacts VYB. The interconnect M1-3 is electrically coupled to the sub-select gate lines SGD3a through SGD3d via the contacts VYB.
That is, the memory pillars MP commonly coupled to the interconnect M1-0 via the sub-select gate lines SGD0a through SGD0d are included in the string unit SU0. The memory pillars MP commonly coupled to the interconnect M1-1 via the sub-select gate lines SGD1a through SGD0d are included in the string unit SU1. The memory pillars MP commonly coupled to the interconnect M1-2 via the sub-select gate lines SGD2a through SGD2d are included in the string unit SU2. The memory pillars MP commonly coupled to the interconnect M1-3 via the sub-select gate lines SGD3a through SGD3d are included in the string unit SU3.
Each of the current path selection portions CNL extends in a direction different from the X direction in an XY plane above the memory pillar MP. Each of the current path selection portions CNL is arranged to intersect the memory pillars MP respectively arranged in the rows adjacent to each other. In the drawings referred to below, directions in which the current path selection portions CNL extend in the XY plane are defined as a P direction and a Q direction. That is, the P direction and the Q direction are directions intersecting the X direction and parallel to the XY plane.
In the example of
Each of the contacts CV is provided to correspond to one current path selection portion CNL. Each of the contacts CV is disposed between two memory pillars MP electrically coupled by the current path selection portion CNL among the corresponding current path selection portions CNL.
Each of the contacts VYA is provided to correspond to one contact CV. Each of the contacts VYA is arranged to overlap the corresponding contact CV.
The plurality of bit lines BL each extend in the Y direction, and are arranged in the X direction. Each bit line BL is electrically coupled to the corresponding current path selection portion CNL via the contacts VYA and CV. In the example of
The semiconductor substrate 20 is, for example, a silicon substrate. The conductive layer 21 is provided above the semiconductor substrate 20 via an intervening insulating layer (not shown). The conductive layer 21 is, for example, formed in a plate shape spreading along the XY plane. The conductive layer 21 is used as the source line SL. The conductive layer 21 contains, for example, silicon doped with phosphorus.
Although not shown, circuits corresponding to, for example, the row decoder module 15 and the sense amplifier module 16, are provided in the semiconductor substrate 20 and in the insulating layer between the semiconductor substrate 20 and the conductive layer 21.
The conductive layer 22 is provided above the conductive layer 21 via an intervening insulating layer (not shown). In one example, the conductive layer 22 is formed in a plate shape spreading along the XY plane. The conductive layer 22 serves as the select gate line SGS. The conductive layer 22 contains, for example, tungsten.
Above the conductive layer 22, insulating layers (not shown) and the conductive layers 23 are alternately stacked. In one example, the conductive layer 23 is formed in a plate shape spreading along the XY plane. The stacked conductive layers 23 are used as word lines WL0 through WL7, respectively, sequentially from the side of the semiconductor substrate 20. The conductive layers 23 contain, for example, tungsten.
The conductive layers 24 are provided above the uppermost conductive layer 23 via an intervening insulating layer (not shown). Each of the conductive layers 24 is formed, for example, in a line shape extending in the Y direction. The conductive layer 24 is used as the bit line BL. The conductive layer 24 contains, for example, copper.
Each of the memory pillars MP extends in the Z direction. Each memory pillar MP penetrates the conductive layers 22 and 23. The lower end of each memory pillar MP is in contact with the conductive layer 21. The upper end of each memory pillar MP is located between the uppermost conductive layer 23 and the conductive layer 24.
A portion where each memory pillar MP and the conductive layer 22 intersect functions as the select transistor ST2. A portion where each memory pillar MP and one conductive layer 23 intersect functions as one memory cell transistor MT.
Each memory pillar MP includes, for example, a core film 30, a semiconductor film 31, a stacked film 32, a conductive film 33, an insulating film 34, a semiconductor film 35, a conductive layer 36, an insulating layer 37, and an insulating film 38.
The core film 30 extends in the Z direction. For example, the upper end of the core film 30 is located above the uppermost conductive layer 23. The lower end of the core film 30 is located above the conductive layer 21. The semiconductor film 31 surrounds the core film 30. A portion of the semiconductor film 31 is in contact with the conductive layer 21 in a lower portion of the memory pillar MP. The stacked film 32 covers the side surface and the bottom surface of the semiconductor film 31 excluding a portion where the semiconductor film 31 and the conductive layer 21 are in contact. The upper end of the stacked film 32 is aligned with the upper end of the semiconductor film 31. The core film 30 contains, for example, an insulator made of silicon oxide, etc. The semiconductor film 31 contains, for example, silicon.
The conductive film 33 includes a portion extending in the Z direction and a portion extending in the X direction. The portion of the conductive film 33 extending in the Z direction functions as a pillar-shaped electrode SP. The portion of the conductive film 33 extending in the X direction functions as one of the sub-select gate lines SGD0a to SGD3d. In the illustrated region, four conductive films 33 respectively including portions functioning as the sub-select gate lines SGD2c, SGD3c, SGD2d, and SGD3d are indicated. The lower end of the portion of the conductive film 33 extending in the Z direction is not in contact with the upper end of the semiconductor film 31. The upper end of the portion of the conductive film 33 extending in the Z direction is in contact with and continuous with the lower end of the portion of the same conductive film 33 extending in the X direction. The conductive film 33 contains, for example, silicon doped with boron.
The insulating film 34 includes a portion extending in the Z direction and a portion spreading in the XY plane. The portion of the insulating film 34 extending in the Z direction covers the side surface and the bottom surface of the portion of the conductive film 33 extending in the Z direction. The upper end of the portion of the insulating film 34 extending in the Z direction is in contact with and continuous with the lower end of the portion of the insulating film 34 spreading in the XY plane. The portion of the insulating film 34 spreading in the XY plane is located below the portion of the conductive film 33 extending in the X direction. The insulating film 34 contains, for example, an insulator made of silicon oxide, etc.
The semiconductor film 35 includes a portion extending in the Z direction and a portion extending in the P direction or the Q direction. In the illustrated region, one semiconductor film 35 having a portion extending in the P direction and two semiconductor films 35 having a portion extending in the Q direction are indicated. The portion of the semiconductor film 35 extending in the Z direction covers the bottom surface and the side surface of the portion of the insulating film 34 extending in the Z direction. The lower end of the portion of the semiconductor film 35 extending in the Z direction is in contact with the upper end of the semiconductor film 31. The upper end of the portion of the semiconductor film 35 extending in the Z direction is in contact with and continuous with the lower end of the portion of the semiconductor film 35 extending in the P direction or the Q direction. The portion of the semiconductor film 35 extending in the P direction or the Q direction is shared by two memory pillars MP. The semiconductor film 35 contains, for example, silicon. A portion of the memory pillar MP, in which the conductive film 33, the insulating film 34, and the semiconductor film 35 extend in the Z direction, functions as the select transistor ST1. For this reason, the semiconductor film 35 in which the portion extending in the P direction or the Q direction is shared by the two memory pillars MP functions as the current path selection portion CNL for causing a current to flow to one of the two memory pillars MP.
The conductive layer 36 is provided on the upper surface of the portion of the conductive film 33 extending in the X direction. The conductive layer 36 contains, for example, tungsten or tungsten silicide and titanium nitride.
The insulating layer 37 is provided on the upper surface of the conductive layer 36. The insulating film 38 is provided on the side surfaces of the portion of the conductive film 33 extending in the X direction, the conductive layer 36, and the insulating layer 37. The insulating layer 37 and the insulating film 38 contain, for example, silicon nitride.
The members SLT include an insulating film 39. The insulating film 39 separates the conductive layers 22 and 23. The lower end of the insulating film 39 reaches the conductive layer 21.
The conductive layer 25 is provided on the upper surface of the portion of the semiconductor film 35 extending in the P direction or the Q direction. The conductive layer 26 is provided on the upper surface of the conductive layer 25. The conductive layers 25 and 26 are used as the contacts CV and VYA, respectively. In the illustrated region, one contact CV and one contact VYA corresponding to the portion of the semiconductor film 35 extending in the P direction are indicated. One conductive layer 24 is provided on the upper surface of the conductive layer 26. The conductive layer 24 functions as the bit line BL.
In the cross section including the conductive layer 23, the core film 30 is provided, for example, in the central portion of the memory pillar MP. The semiconductor film 31 surrounds the side surface of the core film 30. The tunnel insulating film 32a surrounds the side surface of the semiconductor film 31. The charge accumulating film 32b surrounds the side surface of the tunnel insulating film 32a. The block insulating film 32c surrounds the side surface of the charge accumulating film 32b. The conductive layer 23 surrounds the side surface of the block insulating film 32c.
The semiconductor film 31 is used as a current path of the memory cell transistors MT0 through MT7 and the select transistor ST2. The tunnel insulating film 32a and the block insulating film 32c contain, for example, silicon oxide. The charge accumulating film 32b has a function of accumulating electric charges and contains, for example, silicon nitride.
As shown in
The portion of the semiconductor film 35 extending in the Z direction is used as a current path of the select transistor ST1. With these components, the memory pillars MP are each capable of functioning as one NAND string NS.
Each of
First, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, a replacement process for the sacrificial members of the stacked structure is performed. Thus, as shown in
The conductor formed inside the slits is removed by an etch-back process. Therefore, the conductors formed in the adjacent interconnect layers are separated from each other. Accordingly, the conductive layer 22 functioning as the select gate line SGS and the plurality of conductive layers 23 respectively functioning as the word lines WL0 through WL7 are formed. The slits are filled with the insulating film 39. Thus, the members SLT are formed.
Next, as shown in
Next, as shown in
Simultaneously with the step of forming the contacts CV and VYA, the contacts VYB are formed in a region (not shown). Thereafter, an insulating layer 52 is formed on the upper surface of the insulating layer 51 and the upper surface of the conductive layer 26. A mask having openings in regions corresponding to the bit lines BL is formed by photolithography or the like. Then, holes penetrating the insulating layer 52 are formed by anisotropic etching using the mask. At the bottom of each of the holes, the corresponding conductive layer 26 is exposed. Then, the holes are filled with the conductive layer 24.
The memory cell array 10 is thus formed by the manufacturing process described above.
According to the first embodiment, the conductive film 33 has a portion extending in the Z direction above the conductive layer 23. The semiconductor film 31 has a portion that extends in the Z-direction between the conductive layer 23 and the portion of the conductive film 33 extending in the Z-direction and intersects the conductive layer 23. The semiconductor film 35 has a portion that is in contact with the semiconductor film 31, extends in the Z direction between the conductive layer 23 and the portion of the conductive film 33 extending in the Z direction, and faces the conductive film 33. The stacked film 32 is provided between the conductive layer 23 and the semiconductor film 31. The insulating film 34 is provided between the conductive film 33 and the semiconductor films 31 and 35. As a result, the select transistor ST1 of the memory pillar MP has a structure including the pillar-shaped electrode SP provided in the central portion of the memory pillar MP in a plan view and the current path selection portion CNL provided so as to surround the pillar-shaped electrode SP. Therefore, the select gate line SGD can be arranged at a height different from that of the select transistor ST1. Therefore, it is possible to improve the integration degree of the memory cell while suppressing the manufacturing load of the select gate line SGD and the select transistor ST1.
The upper surface of the semiconductor film 31 is in contact with the lower surface of the semiconductor film 35. Specifically, the contact area between the semiconductor film 31 and the semiconductor film 35 corresponds to the XY cross-sectional area of the memory pillar MP. Thus, the contact area between the semiconductor film 31 and the semiconductor film 35 can be increased. Therefore, the resistance of the current path in the memory pillar MP can be reduced.
The portion of the semiconductor film 35 extending in the P direction or the Q direction is shared by two memory pillars MP belonging to different string units SU. Thus, the number of contacts CV and VYA electrically coupling the memory pillar MP and the bit line BL can be reduced to half of the number of memory pillars MP. For this reason, it is possible to suppress the manufacturing load compared to a case where the same number of contacts as the number of memory pillars MP are provided.
Next, a second embodiment will be described.
In the first embodiment, a case where the interconnect layer spreading in the XY plane is not formed in the layer in which the select transistor ST1 is formed has been described. The second embodiment is different from the first embodiment in that an interconnect layer spreading in the XY plane is formed as a back gate in the layer in which the select transistor ST1 is formed. In the following explanation, a description of the same configuration and manufacturing method as in the first embodiment will be omitted, and a configuration and a manufacturing method different from the first embodiment will mainly be described.
A configuration of a memory device according to the second embodiment will be described.
As shown in
Gates of the select transistors ST1a and ST1b in the string units SU0 through SU3 are commonly coupled to select gate lines SGD0 to SGD3, respectively. In the same block BLK, the back gates of the select transistors ST1a and ST1b are coupled to select back gate lines BSGDa and BSGDb, respectively.
An example of the structure of the memory cell array included in the memory device according to the second embodiment will be described below.
As shown in
Each of the current path selection portions CNL is arranged so as to intersect a total of sixteen memory pillars MP respectively arranged in the sixteen rows. The current path selection portions CNL all extend in the P direction.
Four contacts CV are associated with one current path selection portion CNL. Each contact CV is electrically coupled to four consecutively adjacent memory pillars MP among the sixteen memory pillars MP arranged to intersect the current path selection portion CNL via the corresponding current path selection portion CNL. Specifically, the first one of the four contacts CV corresponding to the same current path selection portion CNL is electrically coupled to the four memory pillars MP respectively arranged in the first to fourth rows. The second one of the four contacts CV corresponding to the same current path selection portion CNL is electrically coupled to the four memory pillars MP respectively arranged in the fifth to eighth rows. The third one of the four contacts CV corresponding to the same current path selection portion CNL is electrically coupled to the four memory pillars MP respectively arranged in the ninth to twelfth rows. The fourth one of the four contacts CV corresponding to the same current path selection unit CNL is electrically coupled to the four memory pillars MP arranged in the thirteenth to sixteenth rows.
Each bit line BL is arranged so as to overlap one contact VYA in each block BLK. That is, each bit line BL is electrically connected to four memory pillars MP via one contact VYA in each block BLK. The four memory pillars MP electrically coupled to one bit line BL in each block BLK are included in mutually different string units SU0 to SU3.
The conductive layer 27 is provided above the uppermost conductive layer 23 via an intervening insulating layer (not shown). The conductive layer 28 is provided above the conductive layer 27 via an intervening insulating layer (not shown). A plurality of conductive layers 24 are provided above the conductive layer 28 with an insulating layer (not shown) interposed therebetween. The conductive layers 27 and 28 are formed, for example, in a plate shape spreading along the XY plane. The conductive layers 27 and 28 are used as the select back gate lines BSGDa and BSGDb, respectively. The conductive layers 27 and 28 contain, for example, tungsten.
Each memory pillar MP penetrates through the conductive layers 22, 23, 27, and 28. The upper end of the memory pillar MP is located between the conductive layer 28 and the conductive layer 24.
A portion where each memory pillar MP and the conductive layer 27 intersect functions as the select transistor SIM. A portion where each memory pillar MP and the conductive layer 28 intersect functions as the select transistor ST1a.
Each memory pillar MP includes, for example, a core film 30, a semiconductor film 31, a stacked film 32, a conductive film 33, an insulating film 34, a conductive layer 36, an insulating layer 37, and an insulating film 38. Since the configurations of the conductive layer 36, the insulating layer 37, and the insulating film 38 are the same as those in the first embodiment, description thereof will be omitted.
The upper end of the core film 30 is located above the uppermost conductive layer 23 and below the conductive layer 27.
The conductive film 33 includes a portion extending in the Z direction and a portion extending in the X direction. The portion of the conductive film 33 extending in the Z direction functions as the pillar-shaped electrode SP. The portion of the conductive film 33 extending in the X direction functions as one of the sub-select gate lines SGD0a through SGD3d. In the illustrated region, four conductive films 33 including portions respectively functioning as the sub-select gate lines SGD0d, SGD1d, SGD2d, and SGD3d are indicated. The lower end of the portion of the conductive film 33 extending in the Z direction is located below the upper surface of the conductive layer 27. The upper end of the portion of the conductive film 33 extending in the Z direction is in contact with and continuous with the lower end of the portion of the same conductive film 33 extending in the X direction.
The insulating film 34 includes a portion extending in the Z direction and a portion spreading in the XY plane. The portion of the insulating film 34 extending in the Z direction covers the side surface and the bottom surface of the portion of the conductive film 33 extending in the Z direction. The lower end of the portion of the insulating film 34 extending in the Z direction is in contact with the upper end of the core film 30. The upper end of the portion of the insulating film 34 extending in the Z direction is in contact with and continuous with the lower end of the portion of the insulating film 34 spreading in the XY plane. The portion of the insulating film 34 spreading in the XY plane is located below the portion of the conductive film 33 extending in the X direction.
The semiconductor film 31 includes a portion extending in the Z direction and a portion extending in the P direction. The portion of the semiconductor film 31 extending in the Z direction covers the bottom surface and the side surface of the core film 30 and the side surface of the portion of the insulating film 34 extending in the Z direction. The upper end of the portion of the semiconductor film 31 extending in the Z direction is in contact with and continuous with the lower end of the portion of the semiconductor film 31 extending in the P direction. The portion of the semiconductor film 31 extending in the P direction is shared by sixteen memory pillars MP. In the illustrated region, among the portions extending in the P direction of the semiconductor film 31, a portion shared by four memory pillars MP is indicated.
The stacked film 32 covers the side surface and the bottom surface of the semiconductor film 31 excluding a portion where the semiconductor film 31 and the conductive layer 21 are in contact. The upper end of the stacked film 32 is aligned with the upper end of the portion of the semiconductor film 31 extending in the Z direction.
The conductive layer 25 is provided on the upper surface of the portion of the semiconductor film 31 extending in the P direction. The conductive layer 26 is provided on the upper surface of the conductive layer 25. The conductive layers 25 and 26 are used as the contacts CV and VYA, respectively. In the illustrated region, one of four sets of contacts CV and VYA corresponding to portions of the semiconductor film 31 extending in the P direction is indicated. One conductive layer 24 is provided on the upper surface of the conductive layer 26. The conductive layer 24 functions as the bit line BL.
As shown in
In the cross section including the conductive layer 27, the portion of the conductive film 33 extending in the Z-direction is provided, for example, in the central portion of the memory pillar MP. The portion of the insulating film 34 extending in the Z direction surrounds the side surface of the portion of the insulating film 33 extending in the Z direction. The portion of the semiconductor film 31 extending in the Z direction surrounds the side surface of the portion of the insulating film 34 extending in the Z direction. The tunnel insulating film 32a surrounds the side surface of the portion of the semiconductor film 31 extending in the Z direction. The charge accumulating film 32b surrounds the side surface of the tunnel insulating film 32a. The block insulating film 32c surrounds the side surface of the charge accumulating film 32b. The conductive layer 27 surrounds the side surface of the block insulating film 32c.
The semiconductor film 31 is used as a current path of the select transistors ST1a, SIM, and ST2 and the memory cell transistors MT0 through MT7. With these components, the memory pillars MP are each capable of functioning as one NAND string NS.
Next, a selection operation of the select transistor of the memory device according to the second embodiment will be described.
As shown in
On the other hand, in the case where the string unit SU2 is selected, the row decoder module 15 applies a voltage VSS to the select gate lines SGD0, SGD1, and SGD3. The voltage VSS is a voltage that turns the select transistors ST1a and ST1b to an OFF state. The voltage VSS is lower than, for example, the voltage VSG (VSS<VSG). Accordingly, in the memory pillars MP belonging to the string units SU0, SU1, and SU3, no channel is formed in a region in contact with the insulating film 34 in the portion of the semiconductor film 31 extending in the Z direction.
Further, the row decoder module 15 applies a voltage Vb0 to the select back gate line BSGDb. The voltage Vb is a voltage that turns the select transistor ST1b to the ON state. Accordingly, a channel (path (2) in
Further, the row decoder module 15 applies a voltage Va to the select back gate line BSGDa. The voltage Va is a voltage that turns the select transistor ST1a to the OFF state. The voltage Va is, for example, lower than the voltage Vb (Va<Vb). Accordingly, a channel (path (4) in
Each of
First, as shown in
Next, as shown in
Then, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, a replacement process for the sacrificial members of the stacked structure is performed. Thus, as shown in
The conductor formed inside the slits is removed by an etch-back process. Therefore, the conductors formed in the adjacent interconnect layers are separated from each other. Thus, the conductive layer 22 functioning as the select gate line SGS, the conductive layers 23 respectively functioning as the word lines WL0 through WL7, the conductive layer 27 functioning as the select back gate line BSGDa, and the conductive layer 28 functioning as the select back gate line BSGDb are formed. The slits are filled with the insulating film 39. Thus, the members SLT are formed.
Next, as shown in
Next, as shown in
The memory cell array 10 is thus formed by the manufacturing process described above.
According to the second embodiment, the conductive layers 27 and 28 are provided so as to be spaced apart from each other above the uppermost conductive layer 23. Each of the conductive layers 27 and 28 intersects the semiconductor film 31 and the conductive film 33. Thus, the select transistor ST1 includes a select transistor ST1b using the conductive layer 27 as a select back gate line BSGDb and a select transistor ST1a using the conductive layer 28 as a select back gate line BSGDa. Therefore, in the semiconductor film 31 of the memory pillar MP, a current path can be formed in both the region on the conductive film 33 side and the region on the conductive layers 27 and 28 side. Specifically, at the time of the write operation or the read operation, in the memory pillar MP belonging to the selected string unit SU, it is possible to block the current from flowing through the path (4) while causing the current to flow through the paths (1), (2), and (3) shown in
The portion of the semiconductor film 31 extending in the P direction is shared by the sixteen memory pillars MP. The conductive layer 25 is shared by the four memory pillars MP belonging to different string units SU. Thus, the number of contacts CV and VYA that electrically couple the memory pillars MP and the bit lines BL can be reduced to one fourth of the number of memory pillars MP. For this reason, it is possible to suppress the manufacturing load compared to the case where the same number of contacts as the number of memory pillars MP are provided.
Next, a third embodiment will be described.
The third embodiment is equivalent to the first embodiment in that each current path selection portion CNL is configured to intersect two memory pillars MP. The third embodiment is also equivalent to the second embodiment in that the back gate is formed in the layer in which the select transistor ST1 is formed. However, the third embodiment is different from the first embodiment and the second embodiment in that each of a plurality of sub-select gate lines SGD extending in the X direction is formed to intersect a plurality of rows of memory pillars MP. In the following explanation, a description of the same configuration, operation, and manufacturing method as in the second embodiment will be omitted, and a configuration, operation, and manufacturing method different from the second embodiment will mainly be described.
A configuration of a memory device according to the third embodiment will be described.
An example of the structure of a memory cell array included in a memory device according to the third embodiment will be described below.
The select gate line SGD0 includes a plurality of sub-select gate lines SGD0a, SGD0b, and SGD0c. The select gate line SGD1 includes a plurality of sub-select gate lines SGD1a and SGD1b. The select gate line SGD2 includes a plurality of sub-select gate lines SGD2a and SGD2b. The select gate line SGD3 includes a plurality of sub-select gate lines SGD3a and SGD3b.
The sub-select gate lines SGD0a through SGD0c are electrically coupled to the pillar-shaped electrodes SP arranged in the first row, the fourth row, the fifth row, and the sixteenth row, respectively. The sub-selection gate lines SGD1a and SGD1b are electrically coupled to the pillar-shaped electrodes SP arranged in the second and third rows and the sixth and seventh rows, respectively. The sub-selection gate lines SGD2a and SGD2b are electrically coupled to the pillar-shaped electrodes SP arranged in the eighth and ninth rows and the twelfth and thirteenth rows, respectively. The sub-selection gate lines SGD3a and SGD3b are electrically coupled to the pillar-shaped electrodes SP arranged in the tenth and eleventh rows and the fourteenth and fifteenth rows, respectively.
The contacts CVB are provided to correspond to the sub-select gate lines SGD0a through SGD3b, respectively. Each of the contacts CVB extends in the X direction. The contacts CVB are arranged between one of the two members SLT and the pillar-shaped electrodes SP arranged in the first row, between the pillar-shaped electrodes SP arranged in the 2k-th row and the pillar-shaped electrodes SP arranged in the (2k+1)-th row, and between the other of the two members SLT and the pillar-shaped electrodes SP arranged in the sixteenth row (1≤k≤7).
Each of the plurality of contacts VYB is provided to correspond to one sub-select gate line. Each of the contacts VYB is arranged to overlap the corresponding contact CVB.
The interconnect M1-0 is electrically coupled to the sub-select gate lines SGD0a through SGD0c via the contacts VYB and CVB. The interconnect M1-1 is electrically coupled to the sub-select gate lines SGD1a and SGD1b via the contacts VYB and CVB. The interconnect M1-2 is electrically coupled to the sub-select gate lines SGD2a and SGD2b via the contacts VYB and CVB. The interconnect M1-3 is electrically coupled to the sub-select gate lines SGD3a and SGD3b via the contacts VYB and CVB.
Each of the current path selection portions CNL extends in one direction in the XY plane above the memory pillar MP. Each of the current path selection portions CNL is arranged to intersect the memory pillars MP respectively arranged in the rows adjacent to each other. In the example of
Each of the contacts CVA is provided to correspond to one current path selection portion CNL. Each of the contacts CVA is disposed between two memory pillars MP electrically coupled by the current path selection portion CNL among the corresponding current path selection portions CNL and between two adjacent sub-selection gate lines.
Each of the contacts VYA is provided to correspond to one contact CVA. Each of the contacts VYA is arranged to overlap the corresponding contact CVA.
Each of the bit lines BL is electrically coupled to the corresponding current path selection portion CNL via the contacts VYA and CVA.
Each memory pillar MP includes, for example, a core film 30, a semiconductor film 31, a stacked film 32, a conductive film 33, and an insulating film 34. Since the configurations of the core film 30, the stacked film 32, and the insulating film 34 are the same as those in the second embodiment, description thereof will be omitted.
The semiconductor film 31 includes a portion extending in the Z direction and a portion extending in the P direction or the Q direction. In the illustrated region, one semiconductor film 31 having a portion extending in the P direction and two semiconductor films 31 having a portion extending in the Q direction are indicated. The portion of the semiconductor film 31 extending in the P direction or the Q direction is shared by two memory pillars MP.
The conductive layer 25 is provided on the upper surface of the portion of the semiconductor film 31 extending in the P direction or the Q direction. The conductive layer 26 is provided on the upper surface of the conductive layer 25. The conductive layers 25 and 26 are used as the contacts CVA and VYA, respectively. In the illustrated region, one contact CVA and one contact VYA corresponding to a portion of the semiconductor film 31 extending in the P direction are shown. One conductive layer 24 is provided on the upper surface of the conductive layer 26. The conductive layer 24 functions as the bit line BL.
The conductive film 33 includes a portion extending in the Z direction and a portion extending in the X direction. The portion of the conductive film 33 extending in the Z direction functions as the pillar-shaped electrode SP. The portion of the conductive film 33 extending in the X direction functions as one of the sub-select gate lines SGD0a through SGD3b. Each of the portions extending in the X direction of the seven conductive films 33 functioning as the sub-select gate line SGD0b and SGD1a through SGD3b is shared by the memory pillars MP in two adjacent rows. Each of the portions extending in the X direction of the two conductive films 33 functioning as the sub-select gate lines SGD0a and SGD0c is shared by the memory pillars MP in one row. In the illustrated region, three conductive films 33 including portions functioning as the sub-select gate lines SGD2b, SGD3b, and SGD0c are indicated.
The conductive layer 29 is provided on the upper surface of the portion of the conductive film 33 extending in the X direction. The conductive layer 29 is used as the contact CVB. In the illustrated region, three contacts CVB corresponding to the sub-selection gate lines SGD2b, SGD3b, and SGD0c are indicated.
Each of
First, a structure including the core film 30A, the semiconductor film 31A, and the stacked film 32 is formed on the stacked structure through steps equivalent to those shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, a replacement process for the sacrificial members of the stacked structure is performed. Thus, as shown in
Next, as shown in
Next, as shown in
The memory cell array 10 is thus formed by the manufacturing process described above.
According to the third embodiment, each of the portions of the seven conductive films 33 extending in the X direction and respectively corresponding to the sub-select gate lines SGD0b and SGD1a through SGD3b is shared by the plurality of memory pillars MP in two rows. Thus, the number of sub-select gate lines can be made smaller than the number of rows of the memory pillars MP. For this reason, it is possible to suppress the manufacturing load compared to the case where the same number of the sub-select gate lines as the number of memory pillars MP are provided.
Note that various modifications can be applied to the first through third embodiments described above.
For example, in the first through third embodiments described above, a case where the plurality of memory pillars MP are arranged in a staggered manner has been described, but the embodiments are not limited to this case. For example, the plurality of memory pillars MP may be arranged in a lattice pattern. In this case, the P direction and the Q direction may coincide with the Y direction.
In the second embodiment described above, a case where the conductive layer 25 is shared by the four memory pillars MP belonging to different string units SU has been described, but the embodiments are not limited to this case. For example, the conductive layer 25 may be shared by three or fewer and five or more memory pillars MP. In this case, the memory pillars MP sharing the conductive layer 25 belong to string units SU different from each other. Therefore, the number of rows of the plurality of memory pillars MP in one block BLK is the square of the number of memory pillars MP sharing the conductive layer 25.
The manufacturing steps described in the first through third embodiments are merely examples, and the present invention is not limited thereto. For example, other processing steps may be inserted in the course of the manufacturing steps, or some of the processing steps may be omitted or integrated together.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The embodiments and their modifications are covered by the accompanying claims and their equivalents, as would fall within the scope and gist of the inventions.
This application is a Continuation Application of PCT Application No. PCT/JP2021/019228, filed May 20, 2021, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2021/019228 | May 2021 | US |
| Child | 18497435 | US |
