Claims
- 1. A system comprising:
- a plurality of one-chip semiconductor integrated circuit devices each including:
- a plurality of semiconductor memory elements,
- terminals which are supplied with operation designation signals arbitrarily designating any one of a plurality of operations, and
- a control unit which is coupled to said memory elements and said terminals and which sets a plurality of bits of said memory elements into a predetermined logic level according to a predetermined operation designated by said operation designation signals; and
- an external device coupled to said one-chip semiconductor integrated circuit device for supplying said operation designation signals to said terminals of said plurality of one-chip semiconductor integrated circuit devices at substantially the same time,
- wherein each of said control units of each of said plurality of one-chip semiconductor integrated circuit devices, in response to said operation designation signals commonly supplied from said external device, sets said plurality of bits of each of said memory elements into said predetermined logic level,
- wherein said predetermined logic level is data other than data provided by said external device, and
- wherein said operation designation signals are control command data bits which are supplied from said terminals.
- 2. A system comprising:
- a plurality of one-chip semiconductor integrated circuit device each including:
- a plurality of semiconductor memory elements,
- terminals which are supplied with operation designation signals arbitrarily designating any one of a plurality of operations, and
- a control unit which is coupled to said memory elements and said terminals and which sets a plurality of bits of said memory elements into a predetermined logic level according to a predetermined operation designated by said operation designation signals; and
- an external device coupled to said one-chip semiconductor integrated circuit device;
- the method comprising the steps of:
- supplying commonly said operation designation signals to terminals of said plurality of one-chip semiconductor integrated circuit devices at substantially the same time, and
- setting said plurality of bits of each of said memory elements into said predetermined logic level, in response to said operation designation signals commonly supplied from said external device, by each of said control units of each of said plurality of one-chip semiconductor integrated circuit devices, and
- wherein said predetermined logic level is data other than data provided by said external device.
- 3. A system comprising:
- a plurality of one-chip semiconductor integrated circuit devices each including:
- a plurality of semiconductor memory elements,
- terminals which are supplied with operation designation signals arbitrarily designating any one of a plurality of operations, and
- a control unit which is coupled to said memory elements and said terminals and which sets a plurality of bits of said memory elements into a predetermined logic level according to a predetermined operation designated from said plurality of operations by said operation designation signals; and
- an external device coupled to said plurality of one-chip semiconductor integrated circuit devices via a bus for commonly supplying said operation designation signals to said terminals of said plurality of one-chip semiconductor integrated circuit devices at substantially the same time;
- wherein each of said control units of each of said plurality of one-chip semiconductor integrated circuit devices, in response to said operation designation signals commonly supplied from said external device, sets said plurality of bits of each of said memory elements into said predetermined logic level,
- wherein said predetermined logic level is data other than data provided by said external device, and
- wherein said operation designation signals are control command data bits which are supplied from said terminals.
- 4. A system according to claim 1, wherein said predetermined logic level is any one of logic "0" and logic "1".
- 5. A system according to claim 1, wherein said external device is a microprocessor.
- 6. A system according to claim 3, wherein said predetermined logic level is any one of logic "0" and logic "1".
- 7. A system according to claim 3, wherein said external device is a microprocessor.
Priority Claims (5)
Number |
Date |
Country |
Kind |
59-208266 |
Oct 1984 |
JPX |
|
60-105844 |
May 1985 |
JPX |
|
60-105845 |
May 1985 |
JPX |
|
60-105847 |
May 1985 |
JPX |
|
60-105850 |
May 1985 |
JPX |
|
Parent Case Info
This is a continuation of application Ser. No. 08/294,407, filed Aug. 23, 1994, now U.S. Pat. No. 5,448,519; which is a continuation of application Ser. No. 07/855,843, filed Mar. 20, 1992, now U.S. Pat. No. 5,450,342; which is a continuation-in-part of application Ser. No. 07/349,403, filed May 8, 1989, now U.S. Pat. No. 5,175,838; which is a continuation of application Ser. No. 07/240,380, filed Aug. 29, 1988, now U.S. Pat. No. 4,868,781; which is a continuation of application Ser. No. 06/779,676, filed Sep. 24, 1985; said U.S. Pat. No. 4,868,781 being reissued by application Ser. No. 07/542,028, filed Jun. 21, 1990 filed Mar. 20, 1992, now Re. No. 33,922; said Application Ser. No. 07/855,843 now U.S. Pat. No. 5,450,342 also being a continuation-in-part of Ser. No. 07/816,583, filed Jan. 3, 1992; which is a continuation of application Ser. No. 07/314,238, filed Feb. 22, 1989, now U.S. Pat. No. 5,113,487; which is a continuation of application Ser. No. 06/864,502, filed May 19, 1986, now abandoned; said application Ser. No. 07/816,583 also being a continuation-in-part of application Ser. No. 07/349,403, filed May 8, 1989, now U.S. Pat. No. 5,175,838; which is a continuation of application Ser. No. 07/240,380, filed Aug. 29, 1988, now U.S. Pat. No. 4,868,781; which is a continuation of application Ser. No. 06/779,676, filed Sep. 24, 1985, now abandoned; said U.S. Pat. No. 4,868,781 being reissued by application Ser. No. 07/542,028, filed Jun. 21, 1990, now Re. No. 33,922.
US Referenced Citations (40)
Foreign Referenced Citations (10)
Number |
Date |
Country |
3437896 |
Apr 1985 |
DEX |
58-115673 |
Jul 1983 |
JPX |
58-196671 |
Nov 1983 |
JPX |
0208845 |
Dec 1983 |
JPX |
59-60658 |
Apr 1984 |
JPX |
59-95669 |
Jun 1984 |
JPX |
0005339 |
Jan 1986 |
JPX |
61-264378 |
Nov 1986 |
JPX |
61-264379 |
Nov 1986 |
JPX |
2103339 |
Feb 1983 |
GBX |
Non-Patent Literature Citations (3)
Entry |
IEEE Transactions on Software Engineering, vol. 528, No. 2, Mar. 1982, pp. 137-146 "A Local Network Based on the UNIX Operating System". |
Alexandridis N. A., "Microprocessor System Design Concepts," Computer Science Press, 1984, pp. 1-12, 29-34. |
IBM-TDB vol. 26 No. 10A Mar. 1984 "Efficient Bit String Handling with Standard Processing Units" by E. Mumprecht pp. 4912-4914. |
Continuations (8)
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Number |
Date |
Country |
Parent |
294407 |
Aug 1994 |
|
Parent |
855843 |
Mar 1992 |
|
Parent |
240380 |
Aug 1988 |
|
Parent |
779676 |
Sep 1985 |
|
Parent |
314238 |
Feb 1989 |
|
Parent |
864502 |
May 1986 |
|
Parent |
240380 |
Aug 1988 |
|
Parent |
779676 |
Sep 1985 |
|
Continuation in Parts (3)
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Number |
Date |
Country |
Parent |
349403 |
May 1989 |
|
Parent |
816583 |
Jan 1992 |
|
Parent |
349403 |
May 1989 |
|