I/O unit 120 may include bit line drivers to write values to cells of an associated row of array 110. I/O unit 120 may also include sense amplifiers to determine voltage changes within associated rows of memory cell array 110, as well as devices to control pre-charging. Horizontal decoder 130 may include word line drivers to activate a column of memory cells array 110 based on a received x address. Timer 140 may provide clocking for various signals described herein.
According to some embodiments, memory cell array 110 is operated at a higher supply voltage (VLastLevelCache or VLLC) than surrounding functional blocks (e.g., other logic on the same chip). Since the surrounding blocks may operate at a lower VCC (e.g., VCORE), an interface between the blocks and array 110 provides signal translation from the lower supply voltage domain to the higher supply voltage domain. Such signal translation may be necessary to ensure correct operation of the logic (in case VCORE<<VLLC) and/or to prevent a short-circuit path in the receiving gate.
Memory cell line driver 200 includes a first input line to receive a clock-gated signal associated with a first supply power level (VCC1), a second input line to receive an information signal associated with a second supply power level (VCC2), and an output to drive a memory cell line according to the first supply power level (VCC1) based on the clock-gated signal and the information signal. In some embodiments, the first supply power is greater than the second supply power.
In some embodiments, memory cell line driver 200 comprises a word line driver, the clock-gated signal comprises a word line enable signal and the information signal comprises a pre-decoder signal.
More specifically, driver 400 includes p-type metal oxide semiconductor (PMOS) transistor 415, a gate of which is coupled to input line 405, and a source of which is coupled to VLLC. A gate of n-type metal oxide semiconductor (NMOS) 420 is also coupled to the input line 405, and a source of NMOS transistor 420 is coupled to ground.
Input line 410 is coupled to a gate of NMOS transistor 425. A source of NMOS transistor 425 is coupled to a drain of NMOS transistor 420, and a drain of NMOS transistor coupled to a drain of PMOS transistor 415. PMOS transistor 430 includes a gate coupled to input line 410 and a source coupled to VLLC. A source of PMOS transistor 435 is coupled to a drain of PMOS transistor 430. A drain of PMOS transistor 435 is coupled to a drain of NMOS transistor 420 and to a drain of PMOS transistor 415.
Circuit 400 also includes inverter 440. An input of inverter 440 is coupled to the drain of PMOS transistor 435, the drain of NMOS transistor 420 and the drain of PMOS transistor 415. An output of inverter 440 is coupled to a gate of PMOS transistor 435.
In some embodiments, memory cell line driver 200 of
Driver 600 includes NOR gate 615 coupled to the VCORE supply power, where a first input of NOR gate 615 is coupled to input line 605 and a second input of NOR gate 615 is coupled to input line 610. Accordingly, NOR gate 615 is to receive both the clock-gated signal “we” associated with the VLLC domain, and the information signal “data” associated the VCORE domain.
Driver 600 also includes inverter 620 coupled to the VCORE supply power, with an input of inverter 620 coupled to input line 610. NOR gate 625 is also coupled to the VCORE supply power. A first input of NOR gate 625 is coupled to input line 605 and a second input of NOR gate 625 is coupled to an output of inverter 620. Inverter 630 is coupled to the VLLC supply power, and an input of inverter 630 is coupled to input line 610.
NMOS transistor 635 includes a gate coupled to an output of NOR gate 615 and a source transistor coupled to ground. A drain of PMOS transistor 640 is coupled to a drain of NMOS transistor 635 and a source of PMOS transistor 640 is coupled to the VLLC supply power. A drain of PMOS transistor 645 is coupled to a drain of NMOS transistor 635 and to a drain of PMOS transistor 640. A gate of PMOS transistor 645 is coupled to an output of inverter 630, and a source of PMOS transistor 645 is coupled to the VLLC supply power.
PMOS transistor 650 includes a drain coupled to a gate of PMOS transistor 640, a gate coupled to the output of inverter 630 and to the gate of PMOS transistor 645, and a source coupled to the VLLC supply power. A gate of NMOS transistor 655 is coupled to an output of NOR gate 625, a source of NMOS transistor 655 is coupled to ground, and a drain of NMOS transistor 655 is coupled to the drain of PMOS transistor 650 and the gate of PMOS transistor 640. PMOS transistor 660 includes a drain coupled to a drain of NMOS transistor 655, a source coupled to the VLLC supply power, and a gate coupled to the drain of PMOS transistor 645, the drain of NMOS transistor 635, and the drain of PMOS transistor 640.
Integrated circuit 702 communicates with off-die cache 706 according to some embodiments. Off-die cache 706 may also comprise a memory such as memory 100. Integrated circuit 702 may communicate with system memory 708 via a host bus and chipset 710. System memory 708 may comprise any type of memory, including but not limited to Single Data Rate Random Access Memory and Double Data Rate Random Access Memory. Other off-die functional units, such as graphics controller 712 and Network Interface Controller (NIC) 714, may communicate with integrated circuit 702 via appropriate busses or ports.
The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.