The present invention relates generally to memory management in time-division multiplexing (TDM) switches. More particularly, the present invention relates to the storage of incoming grains in a TDM switch prior to retransmission.
In telecommunication switching, time-division multiplex switching is commonly implemented. In such a system, a plurality of ingress ports provide a switch with grains containing data, and the received grains are multiplexed to one or more egress ports. The multiplexing of grains from ingress to egress ports is commonly done using a fixed mapping. Such time division multiplexed switches are commonly used to cross-connect lower rate signals (grains) that are contained within a higher rate signal, also referred to as a grain group. A grain group is composed of a fixed number of grains. In a standard synchronous optical network (SONET) based STS-48 channel carrying a VT1.5 virtual tributary, for example, each VT1.5 is a grain and the 1344 VT1.5s in the channel form a grain group.
It is common for switches to have a plurality of ingress and egress ports, though, using current technology, it is not practical to build fast memories with more than 3 or 4 ports. Generally, building a switch with multiple ingress and egress ports requires a slightly different architecture than the simplified illustration of
The flip-flop based implementation of an N×N memory switch, as illustrated in
Area CostN×N=AreaFF+AreaMUX (1.1)
Area CostN×N=Order (NG)+Order (N2G log2(NG)) (1.2)
Where N=number of ports
The random access memory (RAM) based implementation of an N×N memory switch works with the same two operational steps. First, the switch buffers all the incoming grains, received on the ingress ports 110, in RAMs, one of which is labelled 132. It then multiplexes the grains out onto the egress ports 112 according to the connection memory configuration 130. Double buffering is employed to store one set of ingress grains while the other set is being multiplexed out. The main difference from the flip-flop based implementation is all the ingress grains are stored in RAMs 132 instead of flip-flops. A RAM is more area efficient, but only one grain can be accessed at a time. Consequently, each ingress grain must be stored on a per egress port basis rather then on a per switch basis. Thus, the RAM based implementation minimizes the width of the egress multiplexer 134 to N:1 per egress port but requires NG storage elements 132 per egress port. The order of the area cost of a memory based N×N memory switch is governed by the following equations:
Area CostN×N=AreaRAM+AreaMUX (2.1)
Area CostN×N=Order(N2G)+Order(N2 log2(N)) (2.2)
Where N=number of ports
Telecommunication systems typically have a maximum physical area and cost budget for printed circuit boards. Minimizing the physical area and cost of a printed circuit boards allows network equipment vendors to minimize equipment cost in order to gain market share. Since both physical area and cost are derived from both the number and physical dimension of integrated components, reducing the number and size of those components will have a positive effect on both the physical area and cost of the printed circuit board. In particular, memory switch area grows with switch capacity, thus it is important to reduce area in switching components to enable the design of large switching systems with a minimal number of components.
Both the implementation of
In the flip-flop based implementation of
Utilization %N×N=[Tot egress mux−Inactive egress mux]/[Tot egress mux] (3.1)
Utilization %N×N=[N2G log2(NG)−N(N−1)G log2((N−1)G)]/[N2G log2(NG)] (3.2)
Where N=number of ports
For N=18 and G=1344 Utilization % N×N=6.1%
(i.e. 45G SONET/SDH VT/TU cross connect)
In the RAM based implementation of
Utilization %N×N=[Tot storage−Unused storage]/[Tot storage] (4.1)
Utilization %N×N=[N2G−N(N−1)G]/[N2G] (4.2)
Utilization %N×N=1/N (4.3)
Where N=number of ports
For N=18 and G=1344 Utilization % N×N=5.5%
(i.e. 45G SONET/SDH VT/TU cross connect)
Though the RAM and flip-flop architectures allow for multiplexing the grains received by the ingress ports to the egress ports in a time efficient manner, their space consumption requires large implementations in chips and on printed circuit boards. These two factors increase their cost. The large implementation area is related to the poor utilization of multiplexing capacity and RAM storage. It is, therefore, desirable to provide a multiplexing egress structure that reduces the implementation size and increases the utilization percentage.
It is an object of the present invention to obviate or mitigate at least one disadvantage of previous time division multiplexing switches.
In a first aspect of the present invention, there is provided a time division multiplexing switch. The TDM switch comprises a plurality of ingress ports and at least one memory egress self selection (MESS) egress port. Each of the ingress ports in the plurality synchronously receives data grains at fixed time intervals. The received data grains are ordered as grain groups. The at least one MESS egress port receives the data grains from the plurality of ingress ports, preferably as an aggregate, and transmits stored data grains in a predetermined order. The at least one MESS egress port has a data grain selector for selecting data grains from the received data grains in accordance with at least one predetermined criterion prior to storing the selected grains for transmission by the MESS egress port.
In an embodiment of the first aspect of the present invention the plurality of ingress ports and the at least one memory egress self selection egress ports are equal in number, so that the switch is a symmetrical switch. In another embodiment of the present invention, the switch includes a grain aggregator, operatively connected to the plurality of ingress ports, for aggregating the data grains received by each of the ingress ports and for providing the aggregate to the at least one MESS egress port.
In a further embodiment of the first aspect of the present invention, the data grain selector includes an ingress processor for both receiving the aggregate and for selecting data grains from the aggregate for storage in accordance with the at least one predetermined criterion. In a presently preferred embodiment, the ingress processor includes both an interest memory for storing a grain mask corresponding to the predetermined grain selection criterion and a finite state machine for selecting grains from the aggregate for storage in accordance with the grain mask. In a further embodiment, the grain mask is based on the associated ingress port and the position of the grain the respective grain group.
In another embodiment, each of the MESS egress ports includes a memory and an egress processor. The memory stores the data grains selected by the ingress processor. The egress processor reads and transmits the stored data grains from the memory in a predetermined order. In other embodiments the ingress processor includes a memory compactor for addressing the selected data grains for storage in the memory without memory fragmentation, the memory compactor preferably including, or using an already existing finite state machine for selecting the first available location in memory as well as a plurality of multiplexers for multiplexing the selected data grains into the memory. In other embodiments, the memory stores only the selected data grains and is preferably sized to store exactly one grain group. In other embodiments the egress processor includes an egress processing memory for storing the predetermined order for reading and transmitting the stored data grains and optionally the egress processor is connected to a connection memory for storing connection information which additionally provides the interest RAM with the predetermined criterion and the egress processing memory with the predetermined order in accordance with the stored connection information.
In a further embodiment, the egress processor includes an N:1 multiplexer attached to the memory for reading and sequentially transmitting the stored data grains in the predetermined order, where N is the number of ingress ports. In another embodiment, the egress processor includes an N:M multiplexer attached to the memory for reading and sequentially transmitting a plurality of data grains in the predetermined order, where N is the number of ingress ports and M≧1.
In another aspect of the present invention, there is provided a method of time division multiplex switching received data grains to at least one egress port. The method comprises the steps of: receiving and aggregating a plurality of data grains received in a single timeslot at a number of ingress ports, each of the plurality of data grains being associated with a grain group; transferring the aggregate of the received data grains to the at least one egress port; selecting from the aggregate the data grains to be transmitted by the at least one egress port; storing the selected data grains at the least one egress port; and transmitting the stored data grains from the at least one egress port in a predetermined order.
In embodiments of the present invention the step of selecting includes applying a mask to the aggregate to select grains in accordance with the ingress port associated with the position of the grain in the aggregate and the position of the grain in its respective grain group and the step of storing the selected grains includes storing only the selected grains. In another embodiment, the step of storing the selected grains includes compactly storing the selected grains in a memory and the step of transmitting includes reading stored grains from the memory in a predetermined order.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.
Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:
Generally, the present invention provides a method and system for multiplexing data grains received on a number of ingress ports to a number of egress ports. For the purposes of illustration, the number of ingress ports and egress ports will be identical, though one skilled in the art will readily appreciate that the teachings below can be applied to asymmetrical switching systems.
The present invention provides a time division multiplex (TDM) switch that increases the percentage utilization of components in comparison to many prior art switches. The present invention also provides a novel method of multiplexing data grains received on ingress ports to egress ports. The present invention provides a system and method of time division multiplex switching data grains received on ingress ports to a number of egress ports, each egress port storing selected received grains in a memory for transmission by the egress port.
In operation, as well as in structure, the system illustrated in
Area CostN×N=AreaRAM+AreaMUX+AreaINGRESS PROC+Area CostEGRESS PROC (5.1)
Area CostN×N=Order(NG)+Order(N2 log2(N))+Order(N2G+N3 log2(N))+Order(NG log2(N)+NG log2(G/N)) (5.2)
Where N=number of ports
The MESS based implementation of an N×N memory switch illustrated in
The ingress processor 206 writes data into data RAMs A and B 208 sequentially starting from (RAM#1, Addr#0) to (RAM#N, Addr#0) then from (RAM #1, Addr#1) to (RAM#N, Addr#1) and then from (RAM #1, Addr#G/N−1) to (RAM#N, Addr#G/N−1). This results in a compact memory usage which avoids memory fragmentation, and results in complete usage of each memory location, one of which is labelled as 232. This technique is analogous to creating a brick wall, and as a result the memory structure is referred to as a “brick wall”. The brick wall is restarted at the next grain group boundary in the companion data RAM B. 0 to N bytes can be written simultaneously in data RAM 208 since only the selected ingress grains are stored. As an example of multiple writes to data RAM 208,
The ingress processor 206 selects and formats the ingress grains to be stored in data RAM 208.
The ingress processor 206 selects and formats the ingress grains presented on the wide ingress data bus in order to build a compact brick wall in the data RAMs 208. The wide ingress data bus is obtained by merging all the ingress ports.
The selection of grains by ingress processor 206 is performed so that grains meeting at least one criterion are selected. In a switch having N inputs, ingress processor 206 receives N grains simultaneously. Each N grain block received corresponds to the grains received in a given timeslot. The particular timeslot that grains are received in defines the position of the grain in the grain group. Interest RAM 236 is preferably used by ingress processor 206 to store the criteria on which grains are selected. In a presently preferred embodiment, a grain is selected in accordance with the ingress port that it was received on, and the position of the grain in its grain group. Thus, interest RAM 236 can provide a selection mask to ingress processor 206 indicating the grains that should be selected from the N grain block. The interest RAM 236, thus would store G different masks, each mask corresponding to the grains to select in each of the G timeslots in the grain group.
Interest RAM 236 is preferably synchronized with the wide ingress data bus, which can be achieved by monitoring the frame reference of the data bus. In one embodiment, interest RAM 236 sequentially reads each of the G words it stores after achieving synchronization. In this embodiment, each of the G words stored in interest RAM 236 acts as a selection mask for the grains arriving at each time slot. After reading the final word in interest RAM 236 the reading is cycled back to the first word. Thus, each of the words is associated with a timeslot in a grain group. Each of the G words stored in interest RAM 236 is read at the same timeslot as the grains of that timeslot are received by compactor 234. In a presently preferred embodiment, if the interest bit is set to one, the grain is selected. Otherwise, the grain is discarded. In other words, interest RAM 236 has G bits set to one (out of NG RAM bits) and those G bits correspond to the G ingress grains (out of NG ingress grains) that must be selected by the egress port. Interest RAM 236 can be configured from the connection memory RAM 214 (shown in
Compactor 234 does the data formatting of selected grains. The compactor 234 receives all the ingress grains from the wide ingress data bus and the selection flags from the interest RAM 236. Between 0 and N grains can be selected in any timeslot. If 0 grains are selected then the compactor does nothing. If n grains (1≦n≦N) are selected, compactor 234 removes the gaps between the selected grains in order to compact the data on the data bus. Then, the compacted data on the bus is barrel shifted to properly build the compact brick wall in data RAM 208. The selection of the desired grains, and the discarding of the other grains can be simply implemented through the use of a simple ‘AND’ operation.
FSM 240 keeps track of the last location in the data RAMs 208 that contains valid data. At the next time-slot it controls compactor 234 to steer the first selected grain to the next free location and subsequently selected bytes to the adjacent locations, which will also be free. In a presently preferred embodiment, the location of a cell in data RAM 208 is defined by the doublet (RAM number, RAM word address).
The egress processor 212 serves to extract the grains from data RAMs 208 and properly formats the egress grain group prior to transmission.
bits (rounded up to the nearest bit). Table 2 compares the MESS implementation of the present invention to the requirements of flip-flop and RAM based implementations of the prior art.
Egress processor 212 extracts the grains from the data RAMs 208 and properly formats the egress grain group. Egress processing RAM 242 is preferably synchronized with the wide ingress data bus. Synchronization can be achieved by monitoring the frame reference. Once synchronized, egress processing RAM 242 sequentially reads each of its G words. Each word represents the address of a grain in data RAM 208. The address, as before, is the doublet of the RAM number (1 to N) and the address location (0 to G/N−1) in the indicated RAM. Egress processing RAM 242 contains an in-order list of the addresses corresponding to the grains to be extracted and presented on the egress port. Random access from data RAMs 208 allows the grains to be accessed in order to form a proper egress grain group. The egress processing RAM 242 can be configured from the connection memory RAM 214 (shown in
The present invention provides a reduced implementation area for a switch by reducing the memory footprint and complex multiplexing circuitry. This reduction requires the implementation of additional logic such as ingress processor 206 and egress processor 212. However, the area occupied by these logic blocks is negligible when the grain count G is large. The area savings attributable to memory and multiplexing reduction and simplification more than offsets the area occupied by the additional logic. To demonstrate the area savings, the following sets of equations show the area required for a SONET/SDH application (a 45 G VT/TU wideband cross connect where the grain number G equals 1344 and the port number N equals 18).
Equations 6.1 through 6.4 define the required area for a flip-flop based implementation of an N×N memory switch (or a wideband cross connect). With a flip-flop based implementation, the wideband cross connect requires 54 600 000 gates.
AreaFF=N{10×2×[Storage]+[Muxing]} (6.1)
AreaFF=N{10×2×[8 bit Grains]+[8 bit Egress Muxing]} (6.2)
AreaFF=N{10×2×[8G]+[8NG log2(NG)]} (6.3)
Where N=18
The factor 10 before the storage element accounts for the 10 gates required per flip-flop, while the factor 2 before the storage element accounts for the double buffering.
Equations 7.1 through 7.4 define the required area for a RAM based implementation of an N×N memory switch (or a wideband cross connect). With a RAM based implementation, the wideband cross connect requires 20 900 000 gates.
AreaRAM=N{3×2×[Storage]+[Muxing]} (7.1)
AreaRAM=N{3×2×[8 bit Grains]+[8 bit Egress Muxing]} (7.2)
AreaRAM=N{3×2×[8NG]+[8N log2(N)]} (7.3)
Where N=18
The factor 3 before the storage element accounts for the 3 gates required per RAM bit, while the factor 2 before the storage element accounts for the double buffering.
Equations 8.1 through 8.4 define the required area for a MESS based implementation of an N×N memory switch (or a wideband cross connect). With a MESS based implementation, the wideband cross connect requires 5 500 000 gates.
AreaMESS=N{3×2×[Storage]+[Muxing]} (8.1)
AreaMESS=N{3×2×[8 bit Grains+interest+Egress]+[8 bit compactor+8 bit Egress Muxing]} (8.2)
AreaMESS=N{3×2×[8G+NG+G log2(N)+G log2(G/N)]+[8N2 Log2(N)+8N log2(N)]} (8.3)
Where N=18
The factor 3 before the storage element accounts for the 3 gates required per RAM bit, while the factor 2 before the storage element accounts for the double buffering.
Using the above calculated values, the area saving in relation to the prior art is at least a 73% area reduction in comparison to either the flip-flop or the RAM based implementation when the grain count G is large.
The embodiment of the invention as described above utilizes a connection memory RAM 214 to allow an operator to configure the interest RAM 236 and the egress processing RAM 242. One skilled in the art will appreciate that the connection memory RAM 214 is merely preferably employed in the system of the present invention. The connection memory RAM 214 provides a convenient tool to allow the user to program the memory switch by defining the egress doublet (egress grain, ingress grain) for each egress grain. Nevertheless, the connection memory RAM 214 can easily be removed and both the interest RAM 236 and the egress processing RAM 242 can be configured directly via a microprocessor interface.
One skilled in the art will also appreciate that the MESS egress port 204 can be implemented with an N:M multiplexer in place of N:1 multiplexer 210. This allows for a single MESS egress port 204 to replace a plurality of egress ports, which avoids duplicating control logic such as frame counters and synchronizing circuitry. Such an implementation requires the interest RAM 236 and the egress processing RAM 242 to be accordingly adjusted. The interest RAM 236 should store a mask that selects all grains destined for one of the plurality of egress ports served by the MESS egress port 204. In this embodiment, the egress processing RAM 242 stores M-plets of data for selecting the addresses of the M grains required at a single time. This implementation preferably utilizes a multiple read data RAM 208 that allows M addresses to be read simultaneously. This can be implemented through a number of known memory configurations.
The above described system can be used in conjunction with any system where data must be switched from ingress sources to egress destinations. One skilled in the art will appreciate that it is preferably used in systems where the number of grains in a grain group is sufficiently large so as to provide an area savings. However, if area consumption is not a concern, it can be used in very small grain group scenarios.
The above-described embodiments of the present invention are intended to be examples only. Alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.
This application claims the benefit of priority of U.S. Provisional Application No. 60/458,375 filed Mar. 31, 2003, which is incorporated herein by reference.
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