Claims
- 1. A memory interface unit for coupling a microprocessor to memory external to said microprocessor, wherein said memory can be one of two types, a first type providing data on a first number of data provision lines, and a second type providing data on a second number of data provision lines, wherein said second number is less than said first number, comprising:
- a plurality of address lines;
- a first strobe line and a second strobe line,
- a control unit storing an indication to indicate the type of memory to which the memory interface unit is connected;
- an address provision unit connected to said address lines and to said first and second strobe lines for providing an address and for providing at least one strobe signal;
- the address provision unit responding to said indication such that when said control unit indicates that said first type of memory is connected to said memory interface unit said address lines function as address lines, and said first strobe line and said second strobe line both function as strobe lines, but such that when said control unit indicates that said second type of memory is connected to said memory interface unit said address lines function as address lines, and said first strobe line functions as a strobe line, but said second strobe line functions as an address line; and
- wherein, when said control unit indicates that said second type of memory is connected said address provision unit responds by providing the address on said address lines shifted by one bit position, as compared with the address as provided when said control unit indicates that said first type of memory is connected.
- 2. A memory interface unit for coupling a microprocessor to memory external to said microprocessor having thirty two interface data exchange lines, wherein said memory can be one of three types, a first type providing data on thirty two memory data exchange lines, and a second type providing data on sixteen memory data exchange lines and a third type providing data on eight memory data exchange lines, comprising:
- a plurality of address lines;
- a first strobe line, a second strobe line, a third strobe line and a fourth strobe line;
- A control unit storing an indication to indicate the type of memory to which the memory interface unit is connected, said first type, said second type or said third type:
- an address provision unit connected to said address lines and to said first and second strobe lines for providing an address and for providing at least one strobe signal:
- the address provision unit responding to said indication such that when said control unit indicates that said first type of memory is connected said address lines function as address lines, and said strobe lines function as strobe lines, but such that when said control unit indicates that said second type of memory is connected said address lines function as address lines, and said first strobe line and said second strobe line function as strobe lines, but said third strobe line functions as an address line, and such that when said control unit indicates that said third type of memory is connected said address lines function as address lines, and said first strobe line functions as a strobe line, but said third strobe line and said fourth strobe line function as address lines;
- wherein, when said control unit indicates that said second type of memory is connected said address provision unit responds by providing the address on said address lines shifted by one bit position, as compared with the address as provided when said control unit indicates that said first type of memory is connected.
- 3. A memory interface unit for coupling a microprocessor to memory external to said microprocessor, having thirty two interface data exchange lines. wherein said memory can be one of three types, a first type providing data on thirty two memory data exchange lines, and a second type providing data on sixteen memory data exchange lines and a third type providing data on eight memory data exchange lines, comprising:
- a plurality of address lines:
- a first strobe line, a second strobe line, a third strobe line and a fourth strobe line;
- a control unit storing an indication to indicate the type of memory to which the memory interface unit is connected, said first type, said second type or said third type;
- an address provision unit connected to said address lines and to said first and second strobe lines for providing an address and for providing at least one strobe signal;
- the address provision unit responding to said indication such that when said control unit indicates that said first type of memory is connected said address lines function as address lines, and said strobe lines function as strobe lines, but such that when said control unit indicates that said second type of memory is connected said address lines function as address lines, and said first strobe line and said second strobe line function as strobe lines, but said third strobe line functions as an address line, and such that when said control unit indicates that said third type of memory is connected said address lines function as address lines, and said first strobe line functions as a strobe line, but said third strobe line and said fourth strobe line function as address lines;
- wherein, when said control unit indicates that said third type of memory is connected said address provision unit responds by providing the address on said address lines shifted by two bit positions, as compared with the address as provided when said control unit indicates that said first type of memory is connected.
- 4. A memory interface unit for coupling a microprocessor to memory external to said microprocessor, having thirty two interface data exchange lines, wherein said memory can be one of three types, a first type providing data on thirty two memory data exchange lines, and a second type providing data on sixteen memory data exchange lines and a third type providing data on eight memory data exchange lines, comprising:
- a plurality of address lines;
- a first strobe line, a second strobe line, a third strobe line and a fourth strobe line
- a control unit storing an indication to indicate the type of memory to which the memory interface unit is connected, said first type, said second type or said third type;
- an address provision unit connected to said address lines and to said first and second strobe lines for providing an address and for providing at least one strobe signal;
- the address provision unit responding to said indication such that when said control unit indicates that said first type of memory is connected said address lines function as address lines, and said strobe lines function as strobe lines, but such that when said control unit indicates that said second type of memory is connected said address lines function as address lines, and said first strobe line and said second strobe line function as strobe lines, but said third strobe line functions as an address line, and such that when said control unit indicates that said third type of memory is connected said address lines function as address lines, and said first strobe line functions as a strobe line, but said third strobe line and said fourth strobe line function as address lines;
- wherein said indication is a field in a control register.
- 5. A memory interface unit for coupling a microprocessor to memory external to said microprocessor, having thirty two interface data exchange lines, wherein said memory can be one of three types, a first type providing data on thirty two memory data exchange lines, and a second type providing data on sixteen memory data exchange lines and a third type providing data on eight memory data exchange lines, comprising:
- a plurality of address lines;
- a first strobe line, a second strobe line, a third strobe line and a fourth strobe line;
- a control unit storing an indication to indicate the type of memory to which the memory interface unit is connected, said first type, said second type or said third type;
- an address provision unit connected to said address lines and to said first and second strobe lines for providing an address and for providing at least one strobe signal;
- the address provision unit responding to said indication such that when said control unit indicates that said first type of memory is connected said address lines function as address lines, and said strobe lines function as strobe lines, but such that when said control unit indicates that said second type of memory is connected said address lines function as address lines, and said first strobe line and said second strobe line function as strobe lines, but said third strobe line functions as an address line, and such that when said control unit indicates that said third type of memory is connected said address lines function as address lines, and said first strobe line functions as a strobe line, but said third strobe line and said fourth strobe line function as address lines;
- the memory interface unit further comprising:
- a bus, for providing data received on said interface data exchange lines to said microprocessor; and
- a fill unit responsive to said control unit that, when said control unit indicates that said second type of memory is connected, provides predetermined bit values on the lines in said bus corresponding to the interface data exchange lines not connected to memory data exchange lines.
- 6. A memory interface unit for coupling a microprocessor to memory external to said microprocessor, wherein said memory can be one of two types, a first type providing data on a first number of data provision lines, and a second type providing data on a second number of data provision lines, wherein said second number is less than said first number, comprising:
- a plurality of address lines;
- a first strobe line and a second strobe line;
- a control unit storing an indication to indicate the type of memory to which the memory interface unit is connected;
- an address provision unit connected to said address lines and to said first and second strobe lines for providing an address and for providing at least one strobe signal;
- the address provision unit responding to said indication such that when said control unit indicates that said first type of memory is connected to said memory interface unit said address lines function as address lines, and said first strobe line and said second strobe line both function as strobe lines, but such that when said control unit indicates that said second type of memory is connected to said memory interface unit said address lines function as address lines, and said first strobe line functions as a strobe line, but said second strobe line functions as an address line; and
- wherein said indication is a field in a control register.
- 7. A memory interface unit as in claim 6 wherein said field is a value that may be stored under control of a program instruction.
Parent Case Info
This is a division, of application Ser. No. 08/354,182, filed Dec. 12, 1994, now abandoned.
Non-Patent Literature Citations (2)
Entry |
Intel, "Intel 386 DX Microprocessor Hardware Reference Manual", 1991, pp. 3-8. |
Intel, "Intel 386 DX Microprocessor Hardware Reference Manual", 1991, pp. 3-19 to 3-22, 8-17 to 8-19. |
Divisions (1)
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Number |
Date |
Country |
Parent |
354182 |
Dec 1994 |
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